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-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c2210
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c2182
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h2
4 files changed, 2214 insertions, 2182 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 9f363e0c4b60..cf8b4bc3e73d 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -70,7 +70,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
70 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ 70 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
71 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ 71 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
72 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ 72 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
73 radeon_trace_points.o ni.o cayman_blit_shaders.o 73 radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o
74 74
75radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 75radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
76radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o 76radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
new file mode 100644
index 000000000000..36274fac48ac
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -0,0 +1,2210 @@
1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32extern int atom_debug;
33
34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38
39static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40{
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54 return true;
55 default:
56 return false;
57 }
58}
59
60static struct drm_connector *
61radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
62{
63 struct drm_device *dev = encoder->dev;
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_connector *connector;
66 struct radeon_connector *radeon_connector;
67
68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69 radeon_connector = to_radeon_connector(connector);
70 if (radeon_encoder->devices & radeon_connector->devices)
71 return connector;
72 }
73 return NULL;
74}
75
76static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77 struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
79{
80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81 struct drm_device *dev = encoder->dev;
82 struct radeon_device *rdev = dev->dev_private;
83
84 /* set the active encoder to connector routing */
85 radeon_encoder_set_active_device(encoder);
86 drm_mode_set_crtcinfo(adjusted_mode, 0);
87
88 /* hw bug */
89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
92
93 /* get the native mode for LVDS */
94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
95 radeon_panel_mode_fixup(encoder, adjusted_mode);
96
97 /* get the native mode for TV */
98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
100 if (tv_dac) {
101 if (tv_dac->tv_std == TV_STD_NTSC ||
102 tv_dac->tv_std == TV_STD_NTSC_J ||
103 tv_dac->tv_std == TV_STD_PAL_M)
104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
105 else
106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
107 }
108 }
109
110 if (ASIC_IS_DCE3(rdev) &&
111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
114 radeon_dp_set_link_config(connector, mode);
115 }
116
117 return true;
118}
119
120static void
121atombios_dac_setup(struct drm_encoder *encoder, int action)
122{
123 struct drm_device *dev = encoder->dev;
124 struct radeon_device *rdev = dev->dev_private;
125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
126 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
127 int index = 0;
128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
129
130 memset(&args, 0, sizeof(args));
131
132 switch (radeon_encoder->encoder_id) {
133 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
136 break;
137 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
140 break;
141 }
142
143 args.ucAction = action;
144
145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
146 args.ucDacStandard = ATOM_DAC1_PS2;
147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
148 args.ucDacStandard = ATOM_DAC1_CV;
149 else {
150 switch (dac_info->tv_std) {
151 case TV_STD_PAL:
152 case TV_STD_PAL_M:
153 case TV_STD_SCART_PAL:
154 case TV_STD_SECAM:
155 case TV_STD_PAL_CN:
156 args.ucDacStandard = ATOM_DAC1_PAL;
157 break;
158 case TV_STD_NTSC:
159 case TV_STD_NTSC_J:
160 case TV_STD_PAL_60:
161 default:
162 args.ucDacStandard = ATOM_DAC1_NTSC;
163 break;
164 }
165 }
166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
167
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
169
170}
171
172static void
173atombios_tv_setup(struct drm_encoder *encoder, int action)
174{
175 struct drm_device *dev = encoder->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178 TV_ENCODER_CONTROL_PS_ALLOCATION args;
179 int index = 0;
180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
181
182 memset(&args, 0, sizeof(args));
183
184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
185
186 args.sTVEncoder.ucAction = action;
187
188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
190 else {
191 switch (dac_info->tv_std) {
192 case TV_STD_NTSC:
193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
194 break;
195 case TV_STD_PAL:
196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
197 break;
198 case TV_STD_PAL_M:
199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
200 break;
201 case TV_STD_PAL_60:
202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
203 break;
204 case TV_STD_NTSC_J:
205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
206 break;
207 case TV_STD_SCART_PAL:
208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
209 break;
210 case TV_STD_SECAM:
211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
212 break;
213 case TV_STD_PAL_CN:
214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
215 break;
216 default:
217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
218 break;
219 }
220 }
221
222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
223
224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
225
226}
227
228union dvo_encoder_control {
229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
232};
233
234void
235atombios_dvo_setup(struct drm_encoder *encoder, int action)
236{
237 struct drm_device *dev = encoder->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
240 union dvo_encoder_control args;
241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
242
243 memset(&args, 0, sizeof(args));
244
245 if (ASIC_IS_DCE3(rdev)) {
246 /* DCE3+ */
247 args.dvo_v3.ucAction = action;
248 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
249 args.dvo_v3.ucDVOConfig = 0; /* XXX */
250 } else if (ASIC_IS_DCE2(rdev)) {
251 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
252 args.dvo.sDVOEncoder.ucAction = action;
253 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
254 /* DFP1, CRT1, TV1 depending on the type of port */
255 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
256
257 if (radeon_encoder->pixel_clock > 165000)
258 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
259 } else {
260 /* R4xx, R5xx */
261 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
262
263 if (radeon_encoder->pixel_clock > 165000)
264 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
265
266 /*if (pScrn->rgbBits == 8)*/
267 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
268 }
269
270 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
271}
272
273union lvds_encoder_control {
274 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
275 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
276};
277
278void
279atombios_digital_setup(struct drm_encoder *encoder, int action)
280{
281 struct drm_device *dev = encoder->dev;
282 struct radeon_device *rdev = dev->dev_private;
283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
284 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
285 union lvds_encoder_control args;
286 int index = 0;
287 int hdmi_detected = 0;
288 uint8_t frev, crev;
289
290 if (!dig)
291 return;
292
293 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
294 hdmi_detected = 1;
295
296 memset(&args, 0, sizeof(args));
297
298 switch (radeon_encoder->encoder_id) {
299 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
300 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
301 break;
302 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
304 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
305 break;
306 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
307 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
308 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
309 else
310 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
311 break;
312 }
313
314 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
315 return;
316
317 switch (frev) {
318 case 1:
319 case 2:
320 switch (crev) {
321 case 1:
322 args.v1.ucMisc = 0;
323 args.v1.ucAction = action;
324 if (hdmi_detected)
325 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
326 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
327 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
328 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
329 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
330 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
331 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
332 } else {
333 if (dig->linkb)
334 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
335 if (radeon_encoder->pixel_clock > 165000)
336 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
337 /*if (pScrn->rgbBits == 8) */
338 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
339 }
340 break;
341 case 2:
342 case 3:
343 args.v2.ucMisc = 0;
344 args.v2.ucAction = action;
345 if (crev == 3) {
346 if (dig->coherent_mode)
347 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
348 }
349 if (hdmi_detected)
350 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
351 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
352 args.v2.ucTruncate = 0;
353 args.v2.ucSpatial = 0;
354 args.v2.ucTemporal = 0;
355 args.v2.ucFRC = 0;
356 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
357 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
358 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
359 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
360 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
361 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
362 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
363 }
364 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
365 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
366 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
367 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
368 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
369 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
370 }
371 } else {
372 if (dig->linkb)
373 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
374 if (radeon_encoder->pixel_clock > 165000)
375 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
376 }
377 break;
378 default:
379 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
380 break;
381 }
382 break;
383 default:
384 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
385 break;
386 }
387
388 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
389}
390
391int
392atombios_get_encoder_mode(struct drm_encoder *encoder)
393{
394 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
395 struct drm_device *dev = encoder->dev;
396 struct radeon_device *rdev = dev->dev_private;
397 struct drm_connector *connector;
398 struct radeon_connector *radeon_connector;
399 struct radeon_connector_atom_dig *dig_connector;
400
401 /* dp bridges are always DP */
402 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
403 return ATOM_ENCODER_MODE_DP;
404
405 /* DVO is always DVO */
406 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
407 return ATOM_ENCODER_MODE_DVO;
408
409 connector = radeon_get_connector_for_encoder(encoder);
410 /* if we don't have an active device yet, just use one of
411 * the connectors tied to the encoder.
412 */
413 if (!connector)
414 connector = radeon_get_connector_for_encoder_init(encoder);
415 radeon_connector = to_radeon_connector(connector);
416
417 switch (connector->connector_type) {
418 case DRM_MODE_CONNECTOR_DVII:
419 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
420 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
421 /* fix me */
422 if (ASIC_IS_DCE4(rdev))
423 return ATOM_ENCODER_MODE_DVI;
424 else
425 return ATOM_ENCODER_MODE_HDMI;
426 } else if (radeon_connector->use_digital)
427 return ATOM_ENCODER_MODE_DVI;
428 else
429 return ATOM_ENCODER_MODE_CRT;
430 break;
431 case DRM_MODE_CONNECTOR_DVID:
432 case DRM_MODE_CONNECTOR_HDMIA:
433 default:
434 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
435 /* fix me */
436 if (ASIC_IS_DCE4(rdev))
437 return ATOM_ENCODER_MODE_DVI;
438 else
439 return ATOM_ENCODER_MODE_HDMI;
440 } else
441 return ATOM_ENCODER_MODE_DVI;
442 break;
443 case DRM_MODE_CONNECTOR_LVDS:
444 return ATOM_ENCODER_MODE_LVDS;
445 break;
446 case DRM_MODE_CONNECTOR_DisplayPort:
447 dig_connector = radeon_connector->con_priv;
448 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
449 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
450 return ATOM_ENCODER_MODE_DP;
451 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
452 /* fix me */
453 if (ASIC_IS_DCE4(rdev))
454 return ATOM_ENCODER_MODE_DVI;
455 else
456 return ATOM_ENCODER_MODE_HDMI;
457 } else
458 return ATOM_ENCODER_MODE_DVI;
459 break;
460 case DRM_MODE_CONNECTOR_eDP:
461 return ATOM_ENCODER_MODE_DP;
462 case DRM_MODE_CONNECTOR_DVIA:
463 case DRM_MODE_CONNECTOR_VGA:
464 return ATOM_ENCODER_MODE_CRT;
465 break;
466 case DRM_MODE_CONNECTOR_Composite:
467 case DRM_MODE_CONNECTOR_SVIDEO:
468 case DRM_MODE_CONNECTOR_9PinDIN:
469 /* fix me */
470 return ATOM_ENCODER_MODE_TV;
471 /*return ATOM_ENCODER_MODE_CV;*/
472 break;
473 }
474}
475
476/*
477 * DIG Encoder/Transmitter Setup
478 *
479 * DCE 3.0/3.1
480 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
481 * Supports up to 3 digital outputs
482 * - 2 DIG encoder blocks.
483 * DIG1 can drive UNIPHY link A or link B
484 * DIG2 can drive UNIPHY link B or LVTMA
485 *
486 * DCE 3.2
487 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
488 * Supports up to 5 digital outputs
489 * - 2 DIG encoder blocks.
490 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
491 *
492 * DCE 4.0/5.0
493 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
494 * Supports up to 6 digital outputs
495 * - 6 DIG encoder blocks.
496 * - DIG to PHY mapping is hardcoded
497 * DIG1 drives UNIPHY0 link A, A+B
498 * DIG2 drives UNIPHY0 link B
499 * DIG3 drives UNIPHY1 link A, A+B
500 * DIG4 drives UNIPHY1 link B
501 * DIG5 drives UNIPHY2 link A, A+B
502 * DIG6 drives UNIPHY2 link B
503 *
504 * DCE 4.1
505 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
506 * Supports up to 6 digital outputs
507 * - 2 DIG encoder blocks.
508 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
509 *
510 * Routing
511 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
512 * Examples:
513 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
514 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
515 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
516 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
517 */
518
519union dig_encoder_control {
520 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
521 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
522 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
523 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
524};
525
526void
527atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
528{
529 struct drm_device *dev = encoder->dev;
530 struct radeon_device *rdev = dev->dev_private;
531 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
532 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
533 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
534 union dig_encoder_control args;
535 int index = 0;
536 uint8_t frev, crev;
537 int dp_clock = 0;
538 int dp_lane_count = 0;
539 int hpd_id = RADEON_HPD_NONE;
540 int bpc = 8;
541
542 if (connector) {
543 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
544 struct radeon_connector_atom_dig *dig_connector =
545 radeon_connector->con_priv;
546
547 dp_clock = dig_connector->dp_clock;
548 dp_lane_count = dig_connector->dp_lane_count;
549 hpd_id = radeon_connector->hpd.hpd;
550 bpc = connector->display_info.bpc;
551 }
552
553 /* no dig encoder assigned */
554 if (dig->dig_encoder == -1)
555 return;
556
557 memset(&args, 0, sizeof(args));
558
559 if (ASIC_IS_DCE4(rdev))
560 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
561 else {
562 if (dig->dig_encoder)
563 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
564 else
565 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
566 }
567
568 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
569 return;
570
571 args.v1.ucAction = action;
572 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
573 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
574 args.v3.ucPanelMode = panel_mode;
575 else
576 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
577
578 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
579 args.v1.ucLaneNum = dp_lane_count;
580 else if (radeon_encoder->pixel_clock > 165000)
581 args.v1.ucLaneNum = 8;
582 else
583 args.v1.ucLaneNum = 4;
584
585 if (ASIC_IS_DCE5(rdev)) {
586 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
587 if (dp_clock == 270000)
588 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
589 else if (dp_clock == 540000)
590 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
591 }
592 args.v4.acConfig.ucDigSel = dig->dig_encoder;
593 switch (bpc) {
594 case 0:
595 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
596 break;
597 case 6:
598 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
599 break;
600 case 8:
601 default:
602 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
603 break;
604 case 10:
605 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
606 break;
607 case 12:
608 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
609 break;
610 case 16:
611 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
612 break;
613 }
614 if (hpd_id == RADEON_HPD_NONE)
615 args.v4.ucHPD_ID = 0;
616 else
617 args.v4.ucHPD_ID = hpd_id + 1;
618 } else if (ASIC_IS_DCE4(rdev)) {
619 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
620 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
621 args.v3.acConfig.ucDigSel = dig->dig_encoder;
622 switch (bpc) {
623 case 0:
624 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
625 break;
626 case 6:
627 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
628 break;
629 case 8:
630 default:
631 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
632 break;
633 case 10:
634 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
635 break;
636 case 12:
637 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
638 break;
639 case 16:
640 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
641 break;
642 }
643 } else {
644 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
645 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
646 switch (radeon_encoder->encoder_id) {
647 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
648 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
649 break;
650 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
652 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
653 break;
654 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
655 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
656 break;
657 }
658 if (dig->linkb)
659 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
660 else
661 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
662 }
663
664 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
665
666}
667
668union dig_transmitter_control {
669 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
670 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
671 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
672 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
673};
674
675void
676atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
677{
678 struct drm_device *dev = encoder->dev;
679 struct radeon_device *rdev = dev->dev_private;
680 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
681 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
682 struct drm_connector *connector;
683 union dig_transmitter_control args;
684 int index = 0;
685 uint8_t frev, crev;
686 bool is_dp = false;
687 int pll_id = 0;
688 int dp_clock = 0;
689 int dp_lane_count = 0;
690 int connector_object_id = 0;
691 int igp_lane_info = 0;
692 int dig_encoder = dig->dig_encoder;
693
694 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
695 connector = radeon_get_connector_for_encoder_init(encoder);
696 /* just needed to avoid bailing in the encoder check. the encoder
697 * isn't used for init
698 */
699 dig_encoder = 0;
700 } else
701 connector = radeon_get_connector_for_encoder(encoder);
702
703 if (connector) {
704 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
705 struct radeon_connector_atom_dig *dig_connector =
706 radeon_connector->con_priv;
707
708 dp_clock = dig_connector->dp_clock;
709 dp_lane_count = dig_connector->dp_lane_count;
710 connector_object_id =
711 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
712 igp_lane_info = dig_connector->igp_lane_info;
713 }
714
715 /* no dig encoder assigned */
716 if (dig_encoder == -1)
717 return;
718
719 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
720 is_dp = true;
721
722 memset(&args, 0, sizeof(args));
723
724 switch (radeon_encoder->encoder_id) {
725 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
726 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
727 break;
728 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
730 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
731 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
732 break;
733 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
734 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
735 break;
736 }
737
738 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
739 return;
740
741 args.v1.ucAction = action;
742 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
743 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
744 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
745 args.v1.asMode.ucLaneSel = lane_num;
746 args.v1.asMode.ucLaneSet = lane_set;
747 } else {
748 if (is_dp)
749 args.v1.usPixelClock =
750 cpu_to_le16(dp_clock / 10);
751 else if (radeon_encoder->pixel_clock > 165000)
752 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
753 else
754 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
755 }
756 if (ASIC_IS_DCE4(rdev)) {
757 if (is_dp)
758 args.v3.ucLaneNum = dp_lane_count;
759 else if (radeon_encoder->pixel_clock > 165000)
760 args.v3.ucLaneNum = 8;
761 else
762 args.v3.ucLaneNum = 4;
763
764 if (dig->linkb)
765 args.v3.acConfig.ucLinkSel = 1;
766 if (dig_encoder & 1)
767 args.v3.acConfig.ucEncoderSel = 1;
768
769 /* Select the PLL for the PHY
770 * DP PHY should be clocked from external src if there is
771 * one.
772 */
773 if (encoder->crtc) {
774 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
775 pll_id = radeon_crtc->pll_id;
776 }
777
778 if (ASIC_IS_DCE5(rdev)) {
779 /* On DCE5 DCPLL usually generates the DP ref clock */
780 if (is_dp) {
781 if (rdev->clock.dp_extclk)
782 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
783 else
784 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
785 } else
786 args.v4.acConfig.ucRefClkSource = pll_id;
787 } else {
788 /* On DCE4, if there is an external clock, it generates the DP ref clock */
789 if (is_dp && rdev->clock.dp_extclk)
790 args.v3.acConfig.ucRefClkSource = 2; /* external src */
791 else
792 args.v3.acConfig.ucRefClkSource = pll_id;
793 }
794
795 switch (radeon_encoder->encoder_id) {
796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
797 args.v3.acConfig.ucTransmitterSel = 0;
798 break;
799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
800 args.v3.acConfig.ucTransmitterSel = 1;
801 break;
802 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
803 args.v3.acConfig.ucTransmitterSel = 2;
804 break;
805 }
806
807 if (is_dp)
808 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
809 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
810 if (dig->coherent_mode)
811 args.v3.acConfig.fCoherentMode = 1;
812 if (radeon_encoder->pixel_clock > 165000)
813 args.v3.acConfig.fDualLinkConnector = 1;
814 }
815 } else if (ASIC_IS_DCE32(rdev)) {
816 args.v2.acConfig.ucEncoderSel = dig_encoder;
817 if (dig->linkb)
818 args.v2.acConfig.ucLinkSel = 1;
819
820 switch (radeon_encoder->encoder_id) {
821 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
822 args.v2.acConfig.ucTransmitterSel = 0;
823 break;
824 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
825 args.v2.acConfig.ucTransmitterSel = 1;
826 break;
827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
828 args.v2.acConfig.ucTransmitterSel = 2;
829 break;
830 }
831
832 if (is_dp) {
833 args.v2.acConfig.fCoherentMode = 1;
834 args.v2.acConfig.fDPConnector = 1;
835 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
836 if (dig->coherent_mode)
837 args.v2.acConfig.fCoherentMode = 1;
838 if (radeon_encoder->pixel_clock > 165000)
839 args.v2.acConfig.fDualLinkConnector = 1;
840 }
841 } else {
842 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
843
844 if (dig_encoder)
845 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
846 else
847 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
848
849 if ((rdev->flags & RADEON_IS_IGP) &&
850 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
851 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
852 if (igp_lane_info & 0x1)
853 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
854 else if (igp_lane_info & 0x2)
855 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
856 else if (igp_lane_info & 0x4)
857 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
858 else if (igp_lane_info & 0x8)
859 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
860 } else {
861 if (igp_lane_info & 0x3)
862 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
863 else if (igp_lane_info & 0xc)
864 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
865 }
866 }
867
868 if (dig->linkb)
869 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
870 else
871 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
872
873 if (is_dp)
874 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
875 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
876 if (dig->coherent_mode)
877 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
878 if (radeon_encoder->pixel_clock > 165000)
879 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
880 }
881 }
882
883 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
884}
885
886bool
887atombios_set_edp_panel_power(struct drm_connector *connector, int action)
888{
889 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
890 struct drm_device *dev = radeon_connector->base.dev;
891 struct radeon_device *rdev = dev->dev_private;
892 union dig_transmitter_control args;
893 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
894 uint8_t frev, crev;
895
896 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
897 goto done;
898
899 if (!ASIC_IS_DCE4(rdev))
900 goto done;
901
902 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
903 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
904 goto done;
905
906 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
907 goto done;
908
909 memset(&args, 0, sizeof(args));
910
911 args.v1.ucAction = action;
912
913 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
914
915 /* wait for the panel to power up */
916 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
917 int i;
918
919 for (i = 0; i < 300; i++) {
920 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
921 return true;
922 mdelay(1);
923 }
924 return false;
925 }
926done:
927 return true;
928}
929
930union external_encoder_control {
931 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
932 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
933};
934
935static void
936atombios_external_encoder_setup(struct drm_encoder *encoder,
937 struct drm_encoder *ext_encoder,
938 int action)
939{
940 struct drm_device *dev = encoder->dev;
941 struct radeon_device *rdev = dev->dev_private;
942 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
943 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
944 union external_encoder_control args;
945 struct drm_connector *connector;
946 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
947 u8 frev, crev;
948 int dp_clock = 0;
949 int dp_lane_count = 0;
950 int connector_object_id = 0;
951 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
952 int bpc = 8;
953
954 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
955 connector = radeon_get_connector_for_encoder_init(encoder);
956 else
957 connector = radeon_get_connector_for_encoder(encoder);
958
959 if (connector) {
960 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
961 struct radeon_connector_atom_dig *dig_connector =
962 radeon_connector->con_priv;
963
964 dp_clock = dig_connector->dp_clock;
965 dp_lane_count = dig_connector->dp_lane_count;
966 connector_object_id =
967 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
968 bpc = connector->display_info.bpc;
969 }
970
971 memset(&args, 0, sizeof(args));
972
973 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
974 return;
975
976 switch (frev) {
977 case 1:
978 /* no params on frev 1 */
979 break;
980 case 2:
981 switch (crev) {
982 case 1:
983 case 2:
984 args.v1.sDigEncoder.ucAction = action;
985 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
986 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
987
988 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
989 if (dp_clock == 270000)
990 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
991 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
992 } else if (radeon_encoder->pixel_clock > 165000)
993 args.v1.sDigEncoder.ucLaneNum = 8;
994 else
995 args.v1.sDigEncoder.ucLaneNum = 4;
996 break;
997 case 3:
998 args.v3.sExtEncoder.ucAction = action;
999 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1000 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1001 else
1002 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1003 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1004
1005 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1006 if (dp_clock == 270000)
1007 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1008 else if (dp_clock == 540000)
1009 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1010 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1011 } else if (radeon_encoder->pixel_clock > 165000)
1012 args.v3.sExtEncoder.ucLaneNum = 8;
1013 else
1014 args.v3.sExtEncoder.ucLaneNum = 4;
1015 switch (ext_enum) {
1016 case GRAPH_OBJECT_ENUM_ID1:
1017 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1018 break;
1019 case GRAPH_OBJECT_ENUM_ID2:
1020 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1021 break;
1022 case GRAPH_OBJECT_ENUM_ID3:
1023 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1024 break;
1025 }
1026 switch (bpc) {
1027 case 0:
1028 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1029 break;
1030 case 6:
1031 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1032 break;
1033 case 8:
1034 default:
1035 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1036 break;
1037 case 10:
1038 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1039 break;
1040 case 12:
1041 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1042 break;
1043 case 16:
1044 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1045 break;
1046 }
1047 break;
1048 default:
1049 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1050 return;
1051 }
1052 break;
1053 default:
1054 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1055 return;
1056 }
1057 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1058}
1059
1060static void
1061atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1062{
1063 struct drm_device *dev = encoder->dev;
1064 struct radeon_device *rdev = dev->dev_private;
1065 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1067 ENABLE_YUV_PS_ALLOCATION args;
1068 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1069 uint32_t temp, reg;
1070
1071 memset(&args, 0, sizeof(args));
1072
1073 if (rdev->family >= CHIP_R600)
1074 reg = R600_BIOS_3_SCRATCH;
1075 else
1076 reg = RADEON_BIOS_3_SCRATCH;
1077
1078 /* XXX: fix up scratch reg handling */
1079 temp = RREG32(reg);
1080 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1081 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1082 (radeon_crtc->crtc_id << 18)));
1083 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1084 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1085 else
1086 WREG32(reg, 0);
1087
1088 if (enable)
1089 args.ucEnable = ATOM_ENABLE;
1090 args.ucCRTC = radeon_crtc->crtc_id;
1091
1092 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1093
1094 WREG32(reg, temp);
1095}
1096
1097static void
1098radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1099{
1100 struct drm_device *dev = encoder->dev;
1101 struct radeon_device *rdev = dev->dev_private;
1102 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1103 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1104 int index = 0;
1105
1106 memset(&args, 0, sizeof(args));
1107
1108 switch (radeon_encoder->encoder_id) {
1109 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1110 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1111 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1112 break;
1113 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1114 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1115 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1116 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1117 break;
1118 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1119 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1120 break;
1121 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1122 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1123 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1124 else
1125 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1126 break;
1127 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1128 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1129 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1130 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1131 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1132 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1133 else
1134 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1135 break;
1136 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1137 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1138 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1139 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1140 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1141 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1142 else
1143 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1144 break;
1145 default:
1146 return;
1147 }
1148
1149 switch (mode) {
1150 case DRM_MODE_DPMS_ON:
1151 args.ucAction = ATOM_ENABLE;
1152 /* workaround for DVOOutputControl on some RS690 systems */
1153 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1154 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1155 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1157 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1158 } else
1159 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1160 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1161 args.ucAction = ATOM_LCD_BLON;
1162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1163 }
1164 break;
1165 case DRM_MODE_DPMS_STANDBY:
1166 case DRM_MODE_DPMS_SUSPEND:
1167 case DRM_MODE_DPMS_OFF:
1168 args.ucAction = ATOM_DISABLE;
1169 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1170 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1171 args.ucAction = ATOM_LCD_BLOFF;
1172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1173 }
1174 break;
1175 }
1176}
1177
1178static void
1179radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1180{
1181 struct drm_device *dev = encoder->dev;
1182 struct radeon_device *rdev = dev->dev_private;
1183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1184 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1185 struct radeon_connector *radeon_connector = NULL;
1186 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1187
1188 if (connector) {
1189 radeon_connector = to_radeon_connector(connector);
1190 radeon_dig_connector = radeon_connector->con_priv;
1191 }
1192
1193 switch (mode) {
1194 case DRM_MODE_DPMS_ON:
1195 /* some early dce3.2 boards have a bug in their transmitter control table */
1196 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1197 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1198 else
1199 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1200 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1201 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1202 atombios_set_edp_panel_power(connector,
1203 ATOM_TRANSMITTER_ACTION_POWER_ON);
1204 radeon_dig_connector->edp_on = true;
1205 }
1206 if (ASIC_IS_DCE4(rdev))
1207 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1208 radeon_dp_link_train(encoder, connector);
1209 if (ASIC_IS_DCE4(rdev))
1210 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1211 }
1212 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1213 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1214 break;
1215 case DRM_MODE_DPMS_STANDBY:
1216 case DRM_MODE_DPMS_SUSPEND:
1217 case DRM_MODE_DPMS_OFF:
1218 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1219 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1220 if (ASIC_IS_DCE4(rdev))
1221 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1222 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1223 atombios_set_edp_panel_power(connector,
1224 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1225 radeon_dig_connector->edp_on = false;
1226 }
1227 }
1228 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1229 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1230 break;
1231 }
1232}
1233
1234static void
1235radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1236 struct drm_encoder *ext_encoder,
1237 int mode)
1238{
1239 struct drm_device *dev = encoder->dev;
1240 struct radeon_device *rdev = dev->dev_private;
1241
1242 switch (mode) {
1243 case DRM_MODE_DPMS_ON:
1244 default:
1245 if (ASIC_IS_DCE41(rdev)) {
1246 atombios_external_encoder_setup(encoder, ext_encoder,
1247 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1248 atombios_external_encoder_setup(encoder, ext_encoder,
1249 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1250 } else
1251 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1252 break;
1253 case DRM_MODE_DPMS_STANDBY:
1254 case DRM_MODE_DPMS_SUSPEND:
1255 case DRM_MODE_DPMS_OFF:
1256 if (ASIC_IS_DCE41(rdev)) {
1257 atombios_external_encoder_setup(encoder, ext_encoder,
1258 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1259 atombios_external_encoder_setup(encoder, ext_encoder,
1260 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1261 } else
1262 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1263 break;
1264 }
1265}
1266
1267static void
1268radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1269{
1270 struct drm_device *dev = encoder->dev;
1271 struct radeon_device *rdev = dev->dev_private;
1272 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1273 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1274
1275 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1276 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1277 radeon_encoder->active_device);
1278 switch (radeon_encoder->encoder_id) {
1279 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1280 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1281 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1282 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1283 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1284 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1285 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1286 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1287 radeon_atom_encoder_dpms_avivo(encoder, mode);
1288 break;
1289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1292 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1293 radeon_atom_encoder_dpms_dig(encoder, mode);
1294 break;
1295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1296 if (ASIC_IS_DCE5(rdev)) {
1297 switch (mode) {
1298 case DRM_MODE_DPMS_ON:
1299 atombios_dvo_setup(encoder, ATOM_ENABLE);
1300 break;
1301 case DRM_MODE_DPMS_STANDBY:
1302 case DRM_MODE_DPMS_SUSPEND:
1303 case DRM_MODE_DPMS_OFF:
1304 atombios_dvo_setup(encoder, ATOM_DISABLE);
1305 break;
1306 }
1307 } else if (ASIC_IS_DCE3(rdev))
1308 radeon_atom_encoder_dpms_dig(encoder, mode);
1309 else
1310 radeon_atom_encoder_dpms_avivo(encoder, mode);
1311 break;
1312 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1314 if (ASIC_IS_DCE5(rdev)) {
1315 switch (mode) {
1316 case DRM_MODE_DPMS_ON:
1317 atombios_dac_setup(encoder, ATOM_ENABLE);
1318 break;
1319 case DRM_MODE_DPMS_STANDBY:
1320 case DRM_MODE_DPMS_SUSPEND:
1321 case DRM_MODE_DPMS_OFF:
1322 atombios_dac_setup(encoder, ATOM_DISABLE);
1323 break;
1324 }
1325 } else
1326 radeon_atom_encoder_dpms_avivo(encoder, mode);
1327 break;
1328 default:
1329 return;
1330 }
1331
1332 if (ext_encoder)
1333 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1334
1335 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1336
1337}
1338
1339union crtc_source_param {
1340 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1341 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1342};
1343
1344static void
1345atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1346{
1347 struct drm_device *dev = encoder->dev;
1348 struct radeon_device *rdev = dev->dev_private;
1349 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1351 union crtc_source_param args;
1352 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1353 uint8_t frev, crev;
1354 struct radeon_encoder_atom_dig *dig;
1355
1356 memset(&args, 0, sizeof(args));
1357
1358 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1359 return;
1360
1361 switch (frev) {
1362 case 1:
1363 switch (crev) {
1364 case 1:
1365 default:
1366 if (ASIC_IS_AVIVO(rdev))
1367 args.v1.ucCRTC = radeon_crtc->crtc_id;
1368 else {
1369 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1370 args.v1.ucCRTC = radeon_crtc->crtc_id;
1371 } else {
1372 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1373 }
1374 }
1375 switch (radeon_encoder->encoder_id) {
1376 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1377 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1378 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1379 break;
1380 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1381 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1382 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1383 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1384 else
1385 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1386 break;
1387 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1388 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1389 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1390 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1391 break;
1392 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1394 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1395 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1396 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1397 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1398 else
1399 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1400 break;
1401 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1402 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1403 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1404 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1405 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1406 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1407 else
1408 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1409 break;
1410 }
1411 break;
1412 case 2:
1413 args.v2.ucCRTC = radeon_crtc->crtc_id;
1414 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1415 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1416
1417 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1418 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1419 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1420 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1421 else
1422 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1423 } else
1424 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1425 switch (radeon_encoder->encoder_id) {
1426 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1427 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1428 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1429 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1430 dig = radeon_encoder->enc_priv;
1431 switch (dig->dig_encoder) {
1432 case 0:
1433 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1434 break;
1435 case 1:
1436 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1437 break;
1438 case 2:
1439 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1440 break;
1441 case 3:
1442 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1443 break;
1444 case 4:
1445 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1446 break;
1447 case 5:
1448 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1449 break;
1450 }
1451 break;
1452 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1453 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1454 break;
1455 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1456 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1457 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1458 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1459 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1460 else
1461 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1462 break;
1463 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1464 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1465 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1466 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1467 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1468 else
1469 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1470 break;
1471 }
1472 break;
1473 }
1474 break;
1475 default:
1476 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1477 return;
1478 }
1479
1480 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1481
1482 /* update scratch regs with new routing */
1483 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1484}
1485
1486static void
1487atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1488 struct drm_display_mode *mode)
1489{
1490 struct drm_device *dev = encoder->dev;
1491 struct radeon_device *rdev = dev->dev_private;
1492 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1494
1495 /* Funky macbooks */
1496 if ((dev->pdev->device == 0x71C5) &&
1497 (dev->pdev->subsystem_vendor == 0x106b) &&
1498 (dev->pdev->subsystem_device == 0x0080)) {
1499 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1500 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1501
1502 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1503 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1504
1505 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1506 }
1507 }
1508
1509 /* set scaler clears this on some chips */
1510 if (ASIC_IS_AVIVO(rdev) &&
1511 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1512 if (ASIC_IS_DCE4(rdev)) {
1513 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1514 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1515 EVERGREEN_INTERLEAVE_EN);
1516 else
1517 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1518 } else {
1519 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1520 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1521 AVIVO_D1MODE_INTERLEAVE_EN);
1522 else
1523 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1524 }
1525 }
1526}
1527
1528static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1529{
1530 struct drm_device *dev = encoder->dev;
1531 struct radeon_device *rdev = dev->dev_private;
1532 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1533 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1534 struct drm_encoder *test_encoder;
1535 struct radeon_encoder_atom_dig *dig;
1536 uint32_t dig_enc_in_use = 0;
1537
1538 /* DCE4/5 */
1539 if (ASIC_IS_DCE4(rdev)) {
1540 dig = radeon_encoder->enc_priv;
1541 if (ASIC_IS_DCE41(rdev)) {
1542 /* ontario follows DCE4 */
1543 if (rdev->family == CHIP_PALM) {
1544 if (dig->linkb)
1545 return 1;
1546 else
1547 return 0;
1548 } else
1549 /* llano follows DCE3.2 */
1550 return radeon_crtc->crtc_id;
1551 } else {
1552 switch (radeon_encoder->encoder_id) {
1553 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1554 if (dig->linkb)
1555 return 1;
1556 else
1557 return 0;
1558 break;
1559 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1560 if (dig->linkb)
1561 return 3;
1562 else
1563 return 2;
1564 break;
1565 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1566 if (dig->linkb)
1567 return 5;
1568 else
1569 return 4;
1570 break;
1571 }
1572 }
1573 }
1574
1575 /* on DCE32 and encoder can driver any block so just crtc id */
1576 if (ASIC_IS_DCE32(rdev)) {
1577 return radeon_crtc->crtc_id;
1578 }
1579
1580 /* on DCE3 - LVTMA can only be driven by DIGB */
1581 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1582 struct radeon_encoder *radeon_test_encoder;
1583
1584 if (encoder == test_encoder)
1585 continue;
1586
1587 if (!radeon_encoder_is_digital(test_encoder))
1588 continue;
1589
1590 radeon_test_encoder = to_radeon_encoder(test_encoder);
1591 dig = radeon_test_encoder->enc_priv;
1592
1593 if (dig->dig_encoder >= 0)
1594 dig_enc_in_use |= (1 << dig->dig_encoder);
1595 }
1596
1597 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1598 if (dig_enc_in_use & 0x2)
1599 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1600 return 1;
1601 }
1602 if (!(dig_enc_in_use & 1))
1603 return 0;
1604 return 1;
1605}
1606
1607/* This only needs to be called once at startup */
1608void
1609radeon_atom_encoder_init(struct radeon_device *rdev)
1610{
1611 struct drm_device *dev = rdev->ddev;
1612 struct drm_encoder *encoder;
1613
1614 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1615 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1616 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1617
1618 switch (radeon_encoder->encoder_id) {
1619 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1620 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1621 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1623 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1624 break;
1625 default:
1626 break;
1627 }
1628
1629 if (ext_encoder && ASIC_IS_DCE41(rdev))
1630 atombios_external_encoder_setup(encoder, ext_encoder,
1631 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1632 }
1633}
1634
1635static void
1636radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1637 struct drm_display_mode *mode,
1638 struct drm_display_mode *adjusted_mode)
1639{
1640 struct drm_device *dev = encoder->dev;
1641 struct radeon_device *rdev = dev->dev_private;
1642 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1643 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1644
1645 radeon_encoder->pixel_clock = adjusted_mode->clock;
1646
1647 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1648 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1649 atombios_yuv_setup(encoder, true);
1650 else
1651 atombios_yuv_setup(encoder, false);
1652 }
1653
1654 switch (radeon_encoder->encoder_id) {
1655 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1657 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1658 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1659 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1660 break;
1661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1664 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1665 if (ASIC_IS_DCE4(rdev)) {
1666 /* disable the transmitter */
1667 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1668 /* setup and enable the encoder */
1669 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1670
1671 /* enable the transmitter */
1672 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1673 } else {
1674 /* disable the encoder and transmitter */
1675 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1676 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1677
1678 /* setup and enable the encoder and transmitter */
1679 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1680 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1681 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1682 }
1683 break;
1684 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1685 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1686 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1687 atombios_dvo_setup(encoder, ATOM_ENABLE);
1688 break;
1689 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1690 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1691 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1692 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1693 atombios_dac_setup(encoder, ATOM_ENABLE);
1694 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1695 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1696 atombios_tv_setup(encoder, ATOM_ENABLE);
1697 else
1698 atombios_tv_setup(encoder, ATOM_DISABLE);
1699 }
1700 break;
1701 }
1702
1703 if (ext_encoder) {
1704 if (ASIC_IS_DCE41(rdev))
1705 atombios_external_encoder_setup(encoder, ext_encoder,
1706 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1707 else
1708 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1709 }
1710
1711 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1712
1713 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1714 r600_hdmi_enable(encoder);
1715 r600_hdmi_setmode(encoder, adjusted_mode);
1716 }
1717}
1718
1719static bool
1720atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1721{
1722 struct drm_device *dev = encoder->dev;
1723 struct radeon_device *rdev = dev->dev_private;
1724 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1725 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1726
1727 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1728 ATOM_DEVICE_CV_SUPPORT |
1729 ATOM_DEVICE_CRT_SUPPORT)) {
1730 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1731 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1732 uint8_t frev, crev;
1733
1734 memset(&args, 0, sizeof(args));
1735
1736 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1737 return false;
1738
1739 args.sDacload.ucMisc = 0;
1740
1741 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1742 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1743 args.sDacload.ucDacType = ATOM_DAC_A;
1744 else
1745 args.sDacload.ucDacType = ATOM_DAC_B;
1746
1747 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1748 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1749 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1750 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1751 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1752 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1753 if (crev >= 3)
1754 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1755 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1756 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1757 if (crev >= 3)
1758 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1759 }
1760
1761 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1762
1763 return true;
1764 } else
1765 return false;
1766}
1767
1768static enum drm_connector_status
1769radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1770{
1771 struct drm_device *dev = encoder->dev;
1772 struct radeon_device *rdev = dev->dev_private;
1773 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1774 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1775 uint32_t bios_0_scratch;
1776
1777 if (!atombios_dac_load_detect(encoder, connector)) {
1778 DRM_DEBUG_KMS("detect returned false \n");
1779 return connector_status_unknown;
1780 }
1781
1782 if (rdev->family >= CHIP_R600)
1783 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1784 else
1785 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1786
1787 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1788 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1789 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1790 return connector_status_connected;
1791 }
1792 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1793 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1794 return connector_status_connected;
1795 }
1796 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1797 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1798 return connector_status_connected;
1799 }
1800 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1801 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1802 return connector_status_connected; /* CTV */
1803 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1804 return connector_status_connected; /* STV */
1805 }
1806 return connector_status_disconnected;
1807}
1808
1809static enum drm_connector_status
1810radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1811{
1812 struct drm_device *dev = encoder->dev;
1813 struct radeon_device *rdev = dev->dev_private;
1814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1815 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1816 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1817 u32 bios_0_scratch;
1818
1819 if (!ASIC_IS_DCE4(rdev))
1820 return connector_status_unknown;
1821
1822 if (!ext_encoder)
1823 return connector_status_unknown;
1824
1825 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
1826 return connector_status_unknown;
1827
1828 /* load detect on the dp bridge */
1829 atombios_external_encoder_setup(encoder, ext_encoder,
1830 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
1831
1832 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1833
1834 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1835 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1836 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1837 return connector_status_connected;
1838 }
1839 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1840 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1841 return connector_status_connected;
1842 }
1843 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1844 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1845 return connector_status_connected;
1846 }
1847 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1848 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1849 return connector_status_connected; /* CTV */
1850 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1851 return connector_status_connected; /* STV */
1852 }
1853 return connector_status_disconnected;
1854}
1855
1856void
1857radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
1858{
1859 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1860
1861 if (ext_encoder)
1862 /* ddc_setup on the dp bridge */
1863 atombios_external_encoder_setup(encoder, ext_encoder,
1864 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
1865
1866}
1867
1868static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1869{
1870 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1871 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1872
1873 if ((radeon_encoder->active_device &
1874 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
1875 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
1876 ENCODER_OBJECT_ID_NONE)) {
1877 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1878 if (dig)
1879 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1880 }
1881
1882 radeon_atom_output_lock(encoder, true);
1883 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1884
1885 if (connector) {
1886 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1887
1888 /* select the clock/data port if it uses a router */
1889 if (radeon_connector->router.cd_valid)
1890 radeon_router_select_cd_port(radeon_connector);
1891
1892 /* turn eDP panel on for mode set */
1893 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1894 atombios_set_edp_panel_power(connector,
1895 ATOM_TRANSMITTER_ACTION_POWER_ON);
1896 }
1897
1898 /* this is needed for the pll/ss setup to work correctly in some cases */
1899 atombios_set_encoder_crtc_source(encoder);
1900}
1901
1902static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1903{
1904 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1905 radeon_atom_output_lock(encoder, false);
1906}
1907
1908static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1909{
1910 struct drm_device *dev = encoder->dev;
1911 struct radeon_device *rdev = dev->dev_private;
1912 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1913 struct radeon_encoder_atom_dig *dig;
1914
1915 /* check for pre-DCE3 cards with shared encoders;
1916 * can't really use the links individually, so don't disable
1917 * the encoder if it's in use by another connector
1918 */
1919 if (!ASIC_IS_DCE3(rdev)) {
1920 struct drm_encoder *other_encoder;
1921 struct radeon_encoder *other_radeon_encoder;
1922
1923 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1924 other_radeon_encoder = to_radeon_encoder(other_encoder);
1925 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1926 drm_helper_encoder_in_use(other_encoder))
1927 goto disable_done;
1928 }
1929 }
1930
1931 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1932
1933 switch (radeon_encoder->encoder_id) {
1934 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1935 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1936 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1937 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1938 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1939 break;
1940 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1942 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1943 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1944 if (ASIC_IS_DCE4(rdev))
1945 /* disable the transmitter */
1946 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1947 else {
1948 /* disable the encoder and transmitter */
1949 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1950 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1951 }
1952 break;
1953 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1954 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1955 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1956 atombios_dvo_setup(encoder, ATOM_DISABLE);
1957 break;
1958 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1959 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1960 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1961 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1962 atombios_dac_setup(encoder, ATOM_DISABLE);
1963 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1964 atombios_tv_setup(encoder, ATOM_DISABLE);
1965 break;
1966 }
1967
1968disable_done:
1969 if (radeon_encoder_is_digital(encoder)) {
1970 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1971 r600_hdmi_disable(encoder);
1972 dig = radeon_encoder->enc_priv;
1973 dig->dig_encoder = -1;
1974 }
1975 radeon_encoder->active_device = 0;
1976}
1977
1978/* these are handled by the primary encoders */
1979static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1980{
1981
1982}
1983
1984static void radeon_atom_ext_commit(struct drm_encoder *encoder)
1985{
1986
1987}
1988
1989static void
1990radeon_atom_ext_mode_set(struct drm_encoder *encoder,
1991 struct drm_display_mode *mode,
1992 struct drm_display_mode *adjusted_mode)
1993{
1994
1995}
1996
1997static void radeon_atom_ext_disable(struct drm_encoder *encoder)
1998{
1999
2000}
2001
2002static void
2003radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2004{
2005
2006}
2007
2008static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2009 struct drm_display_mode *mode,
2010 struct drm_display_mode *adjusted_mode)
2011{
2012 return true;
2013}
2014
2015static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2016 .dpms = radeon_atom_ext_dpms,
2017 .mode_fixup = radeon_atom_ext_mode_fixup,
2018 .prepare = radeon_atom_ext_prepare,
2019 .mode_set = radeon_atom_ext_mode_set,
2020 .commit = radeon_atom_ext_commit,
2021 .disable = radeon_atom_ext_disable,
2022 /* no detect for TMDS/LVDS yet */
2023};
2024
2025static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2026 .dpms = radeon_atom_encoder_dpms,
2027 .mode_fixup = radeon_atom_mode_fixup,
2028 .prepare = radeon_atom_encoder_prepare,
2029 .mode_set = radeon_atom_encoder_mode_set,
2030 .commit = radeon_atom_encoder_commit,
2031 .disable = radeon_atom_encoder_disable,
2032 .detect = radeon_atom_dig_detect,
2033};
2034
2035static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2036 .dpms = radeon_atom_encoder_dpms,
2037 .mode_fixup = radeon_atom_mode_fixup,
2038 .prepare = radeon_atom_encoder_prepare,
2039 .mode_set = radeon_atom_encoder_mode_set,
2040 .commit = radeon_atom_encoder_commit,
2041 .detect = radeon_atom_dac_detect,
2042};
2043
2044void radeon_enc_destroy(struct drm_encoder *encoder)
2045{
2046 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2047 kfree(radeon_encoder->enc_priv);
2048 drm_encoder_cleanup(encoder);
2049 kfree(radeon_encoder);
2050}
2051
2052static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2053 .destroy = radeon_enc_destroy,
2054};
2055
2056struct radeon_encoder_atom_dac *
2057radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2058{
2059 struct drm_device *dev = radeon_encoder->base.dev;
2060 struct radeon_device *rdev = dev->dev_private;
2061 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2062
2063 if (!dac)
2064 return NULL;
2065
2066 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2067 return dac;
2068}
2069
2070struct radeon_encoder_atom_dig *
2071radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2072{
2073 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2074 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2075
2076 if (!dig)
2077 return NULL;
2078
2079 /* coherent mode by default */
2080 dig->coherent_mode = true;
2081 dig->dig_encoder = -1;
2082
2083 if (encoder_enum == 2)
2084 dig->linkb = true;
2085 else
2086 dig->linkb = false;
2087
2088 return dig;
2089}
2090
2091void
2092radeon_add_atom_encoder(struct drm_device *dev,
2093 uint32_t encoder_enum,
2094 uint32_t supported_device,
2095 u16 caps)
2096{
2097 struct radeon_device *rdev = dev->dev_private;
2098 struct drm_encoder *encoder;
2099 struct radeon_encoder *radeon_encoder;
2100
2101 /* see if we already added it */
2102 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2103 radeon_encoder = to_radeon_encoder(encoder);
2104 if (radeon_encoder->encoder_enum == encoder_enum) {
2105 radeon_encoder->devices |= supported_device;
2106 return;
2107 }
2108
2109 }
2110
2111 /* add a new one */
2112 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2113 if (!radeon_encoder)
2114 return;
2115
2116 encoder = &radeon_encoder->base;
2117 switch (rdev->num_crtc) {
2118 case 1:
2119 encoder->possible_crtcs = 0x1;
2120 break;
2121 case 2:
2122 default:
2123 encoder->possible_crtcs = 0x3;
2124 break;
2125 case 4:
2126 encoder->possible_crtcs = 0xf;
2127 break;
2128 case 6:
2129 encoder->possible_crtcs = 0x3f;
2130 break;
2131 }
2132
2133 radeon_encoder->enc_priv = NULL;
2134
2135 radeon_encoder->encoder_enum = encoder_enum;
2136 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2137 radeon_encoder->devices = supported_device;
2138 radeon_encoder->rmx_type = RMX_OFF;
2139 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2140 radeon_encoder->is_ext_encoder = false;
2141 radeon_encoder->caps = caps;
2142
2143 switch (radeon_encoder->encoder_id) {
2144 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2145 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2146 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2147 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2148 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2149 radeon_encoder->rmx_type = RMX_FULL;
2150 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2151 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2152 } else {
2153 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2154 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2155 }
2156 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2157 break;
2158 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2159 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2160 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2161 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2162 break;
2163 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2166 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2167 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2168 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2169 break;
2170 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2172 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2174 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2176 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2177 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2178 radeon_encoder->rmx_type = RMX_FULL;
2179 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2180 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2181 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2182 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2183 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2184 } else {
2185 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2186 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2187 }
2188 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2189 break;
2190 case ENCODER_OBJECT_ID_SI170B:
2191 case ENCODER_OBJECT_ID_CH7303:
2192 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2193 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2194 case ENCODER_OBJECT_ID_TITFP513:
2195 case ENCODER_OBJECT_ID_VT1623:
2196 case ENCODER_OBJECT_ID_HDMI_SI1930:
2197 case ENCODER_OBJECT_ID_TRAVIS:
2198 case ENCODER_OBJECT_ID_NUTMEG:
2199 /* these are handled by the primary encoders */
2200 radeon_encoder->is_ext_encoder = true;
2201 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2202 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2203 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2204 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2205 else
2206 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2207 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2208 break;
2209 }
2210}
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index e57fd6dab4ba..06e413e6a920 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -29,12 +29,6 @@
29#include "radeon.h" 29#include "radeon.h"
30#include "atom.h" 30#include "atom.h"
31 31
32extern int atom_debug;
33
34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) 32static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39{ 33{
40 struct drm_device *dev = encoder->dev; 34 struct drm_device *dev = encoder->dev;
@@ -156,27 +150,6 @@ radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8
156 return ret; 150 return ret;
157} 151}
158 152
159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
179
180void 153void
181radeon_link_encoder_connector(struct drm_device *dev) 154radeon_link_encoder_connector(struct drm_device *dev)
182{ 155{
@@ -229,23 +202,7 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
229 return NULL; 202 return NULL;
230} 203}
231 204
232static struct drm_connector * 205struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder)
233radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
234{
235 struct drm_device *dev = encoder->dev;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct drm_connector *connector;
238 struct radeon_connector *radeon_connector;
239
240 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
241 radeon_connector = to_radeon_connector(connector);
242 if (radeon_encoder->devices & radeon_connector->devices)
243 return connector;
244 }
245 return NULL;
246}
247
248struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
249{ 206{
250 struct drm_device *dev = encoder->dev; 207 struct drm_device *dev = encoder->dev;
251 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 208 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -268,7 +225,7 @@ struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder
268 225
269u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder) 226u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
270{ 227{
271 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder); 228 struct drm_encoder *other_encoder = radeon_get_external_encoder(encoder);
272 229
273 if (other_encoder) { 230 if (other_encoder) {
274 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder); 231 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
@@ -332,2138 +289,3 @@ void radeon_panel_mode_fixup(struct drm_encoder *encoder,
332 289
333} 290}
334 291
335static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
336 struct drm_display_mode *mode,
337 struct drm_display_mode *adjusted_mode)
338{
339 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
340 struct drm_device *dev = encoder->dev;
341 struct radeon_device *rdev = dev->dev_private;
342
343 /* set the active encoder to connector routing */
344 radeon_encoder_set_active_device(encoder);
345 drm_mode_set_crtcinfo(adjusted_mode, 0);
346
347 /* hw bug */
348 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
349 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
350 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
351
352 /* get the native mode for LVDS */
353 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
354 radeon_panel_mode_fixup(encoder, adjusted_mode);
355
356 /* get the native mode for TV */
357 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
358 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
359 if (tv_dac) {
360 if (tv_dac->tv_std == TV_STD_NTSC ||
361 tv_dac->tv_std == TV_STD_NTSC_J ||
362 tv_dac->tv_std == TV_STD_PAL_M)
363 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
364 else
365 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
366 }
367 }
368
369 if (ASIC_IS_DCE3(rdev) &&
370 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
371 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
372 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
373 radeon_dp_set_link_config(connector, mode);
374 }
375
376 return true;
377}
378
379static void
380atombios_dac_setup(struct drm_encoder *encoder, int action)
381{
382 struct drm_device *dev = encoder->dev;
383 struct radeon_device *rdev = dev->dev_private;
384 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
385 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
386 int index = 0;
387 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
388
389 memset(&args, 0, sizeof(args));
390
391 switch (radeon_encoder->encoder_id) {
392 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
393 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
394 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
395 break;
396 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
398 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
399 break;
400 }
401
402 args.ucAction = action;
403
404 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
405 args.ucDacStandard = ATOM_DAC1_PS2;
406 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
407 args.ucDacStandard = ATOM_DAC1_CV;
408 else {
409 switch (dac_info->tv_std) {
410 case TV_STD_PAL:
411 case TV_STD_PAL_M:
412 case TV_STD_SCART_PAL:
413 case TV_STD_SECAM:
414 case TV_STD_PAL_CN:
415 args.ucDacStandard = ATOM_DAC1_PAL;
416 break;
417 case TV_STD_NTSC:
418 case TV_STD_NTSC_J:
419 case TV_STD_PAL_60:
420 default:
421 args.ucDacStandard = ATOM_DAC1_NTSC;
422 break;
423 }
424 }
425 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
426
427 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
428
429}
430
431static void
432atombios_tv_setup(struct drm_encoder *encoder, int action)
433{
434 struct drm_device *dev = encoder->dev;
435 struct radeon_device *rdev = dev->dev_private;
436 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437 TV_ENCODER_CONTROL_PS_ALLOCATION args;
438 int index = 0;
439 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
440
441 memset(&args, 0, sizeof(args));
442
443 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
444
445 args.sTVEncoder.ucAction = action;
446
447 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
448 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
449 else {
450 switch (dac_info->tv_std) {
451 case TV_STD_NTSC:
452 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
453 break;
454 case TV_STD_PAL:
455 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
456 break;
457 case TV_STD_PAL_M:
458 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
459 break;
460 case TV_STD_PAL_60:
461 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
462 break;
463 case TV_STD_NTSC_J:
464 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
465 break;
466 case TV_STD_SCART_PAL:
467 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
468 break;
469 case TV_STD_SECAM:
470 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
471 break;
472 case TV_STD_PAL_CN:
473 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
474 break;
475 default:
476 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
477 break;
478 }
479 }
480
481 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
482
483 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
484
485}
486
487union dvo_encoder_control {
488 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
489 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
490 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
491};
492
493void
494atombios_dvo_setup(struct drm_encoder *encoder, int action)
495{
496 struct drm_device *dev = encoder->dev;
497 struct radeon_device *rdev = dev->dev_private;
498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
499 union dvo_encoder_control args;
500 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
501
502 memset(&args, 0, sizeof(args));
503
504 if (ASIC_IS_DCE3(rdev)) {
505 /* DCE3+ */
506 args.dvo_v3.ucAction = action;
507 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
508 args.dvo_v3.ucDVOConfig = 0; /* XXX */
509 } else if (ASIC_IS_DCE2(rdev)) {
510 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
511 args.dvo.sDVOEncoder.ucAction = action;
512 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
513 /* DFP1, CRT1, TV1 depending on the type of port */
514 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
515
516 if (radeon_encoder->pixel_clock > 165000)
517 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
518 } else {
519 /* R4xx, R5xx */
520 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
521
522 if (radeon_encoder->pixel_clock > 165000)
523 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
524
525 /*if (pScrn->rgbBits == 8)*/
526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 }
528
529 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
530}
531
532union lvds_encoder_control {
533 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
534 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
535};
536
537void
538atombios_digital_setup(struct drm_encoder *encoder, int action)
539{
540 struct drm_device *dev = encoder->dev;
541 struct radeon_device *rdev = dev->dev_private;
542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
543 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
544 union lvds_encoder_control args;
545 int index = 0;
546 int hdmi_detected = 0;
547 uint8_t frev, crev;
548
549 if (!dig)
550 return;
551
552 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
553 hdmi_detected = 1;
554
555 memset(&args, 0, sizeof(args));
556
557 switch (radeon_encoder->encoder_id) {
558 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
559 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
560 break;
561 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
563 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
564 break;
565 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
566 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
567 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
568 else
569 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
570 break;
571 }
572
573 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
574 return;
575
576 switch (frev) {
577 case 1:
578 case 2:
579 switch (crev) {
580 case 1:
581 args.v1.ucMisc = 0;
582 args.v1.ucAction = action;
583 if (hdmi_detected)
584 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
585 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
588 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
590 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
591 } else {
592 if (dig->linkb)
593 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
594 if (radeon_encoder->pixel_clock > 165000)
595 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
596 /*if (pScrn->rgbBits == 8) */
597 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
598 }
599 break;
600 case 2:
601 case 3:
602 args.v2.ucMisc = 0;
603 args.v2.ucAction = action;
604 if (crev == 3) {
605 if (dig->coherent_mode)
606 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
607 }
608 if (hdmi_detected)
609 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
610 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
611 args.v2.ucTruncate = 0;
612 args.v2.ucSpatial = 0;
613 args.v2.ucTemporal = 0;
614 args.v2.ucFRC = 0;
615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
616 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
617 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
619 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
620 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
621 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
622 }
623 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
624 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
625 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
626 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
627 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
628 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
629 }
630 } else {
631 if (dig->linkb)
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
633 if (radeon_encoder->pixel_clock > 165000)
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
635 }
636 break;
637 default:
638 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
639 break;
640 }
641 break;
642 default:
643 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
644 break;
645 }
646
647 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
648}
649
650int
651atombios_get_encoder_mode(struct drm_encoder *encoder)
652{
653 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
654 struct drm_device *dev = encoder->dev;
655 struct radeon_device *rdev = dev->dev_private;
656 struct drm_connector *connector;
657 struct radeon_connector *radeon_connector;
658 struct radeon_connector_atom_dig *dig_connector;
659
660 /* dp bridges are always DP */
661 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
662 return ATOM_ENCODER_MODE_DP;
663
664 /* DVO is always DVO */
665 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
666 return ATOM_ENCODER_MODE_DVO;
667
668 connector = radeon_get_connector_for_encoder(encoder);
669 /* if we don't have an active device yet, just use one of
670 * the connectors tied to the encoder.
671 */
672 if (!connector)
673 connector = radeon_get_connector_for_encoder_init(encoder);
674 radeon_connector = to_radeon_connector(connector);
675
676 switch (connector->connector_type) {
677 case DRM_MODE_CONNECTOR_DVII:
678 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
679 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
680 /* fix me */
681 if (ASIC_IS_DCE4(rdev))
682 return ATOM_ENCODER_MODE_DVI;
683 else
684 return ATOM_ENCODER_MODE_HDMI;
685 } else if (radeon_connector->use_digital)
686 return ATOM_ENCODER_MODE_DVI;
687 else
688 return ATOM_ENCODER_MODE_CRT;
689 break;
690 case DRM_MODE_CONNECTOR_DVID:
691 case DRM_MODE_CONNECTOR_HDMIA:
692 default:
693 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
694 /* fix me */
695 if (ASIC_IS_DCE4(rdev))
696 return ATOM_ENCODER_MODE_DVI;
697 else
698 return ATOM_ENCODER_MODE_HDMI;
699 } else
700 return ATOM_ENCODER_MODE_DVI;
701 break;
702 case DRM_MODE_CONNECTOR_LVDS:
703 return ATOM_ENCODER_MODE_LVDS;
704 break;
705 case DRM_MODE_CONNECTOR_DisplayPort:
706 dig_connector = radeon_connector->con_priv;
707 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
708 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
709 return ATOM_ENCODER_MODE_DP;
710 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
711 /* fix me */
712 if (ASIC_IS_DCE4(rdev))
713 return ATOM_ENCODER_MODE_DVI;
714 else
715 return ATOM_ENCODER_MODE_HDMI;
716 } else
717 return ATOM_ENCODER_MODE_DVI;
718 break;
719 case DRM_MODE_CONNECTOR_eDP:
720 return ATOM_ENCODER_MODE_DP;
721 case DRM_MODE_CONNECTOR_DVIA:
722 case DRM_MODE_CONNECTOR_VGA:
723 return ATOM_ENCODER_MODE_CRT;
724 break;
725 case DRM_MODE_CONNECTOR_Composite:
726 case DRM_MODE_CONNECTOR_SVIDEO:
727 case DRM_MODE_CONNECTOR_9PinDIN:
728 /* fix me */
729 return ATOM_ENCODER_MODE_TV;
730 /*return ATOM_ENCODER_MODE_CV;*/
731 break;
732 }
733}
734
735/*
736 * DIG Encoder/Transmitter Setup
737 *
738 * DCE 3.0/3.1
739 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
740 * Supports up to 3 digital outputs
741 * - 2 DIG encoder blocks.
742 * DIG1 can drive UNIPHY link A or link B
743 * DIG2 can drive UNIPHY link B or LVTMA
744 *
745 * DCE 3.2
746 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
747 * Supports up to 5 digital outputs
748 * - 2 DIG encoder blocks.
749 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
750 *
751 * DCE 4.0/5.0
752 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
753 * Supports up to 6 digital outputs
754 * - 6 DIG encoder blocks.
755 * - DIG to PHY mapping is hardcoded
756 * DIG1 drives UNIPHY0 link A, A+B
757 * DIG2 drives UNIPHY0 link B
758 * DIG3 drives UNIPHY1 link A, A+B
759 * DIG4 drives UNIPHY1 link B
760 * DIG5 drives UNIPHY2 link A, A+B
761 * DIG6 drives UNIPHY2 link B
762 *
763 * DCE 4.1
764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
765 * Supports up to 6 digital outputs
766 * - 2 DIG encoder blocks.
767 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
768 *
769 * Routing
770 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
771 * Examples:
772 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
773 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
774 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
775 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
776 */
777
778union dig_encoder_control {
779 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
780 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
781 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
782 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
783};
784
785void
786atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
787{
788 struct drm_device *dev = encoder->dev;
789 struct radeon_device *rdev = dev->dev_private;
790 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
791 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
792 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
793 union dig_encoder_control args;
794 int index = 0;
795 uint8_t frev, crev;
796 int dp_clock = 0;
797 int dp_lane_count = 0;
798 int hpd_id = RADEON_HPD_NONE;
799 int bpc = 8;
800
801 if (connector) {
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 struct radeon_connector_atom_dig *dig_connector =
804 radeon_connector->con_priv;
805
806 dp_clock = dig_connector->dp_clock;
807 dp_lane_count = dig_connector->dp_lane_count;
808 hpd_id = radeon_connector->hpd.hpd;
809 bpc = connector->display_info.bpc;
810 }
811
812 /* no dig encoder assigned */
813 if (dig->dig_encoder == -1)
814 return;
815
816 memset(&args, 0, sizeof(args));
817
818 if (ASIC_IS_DCE4(rdev))
819 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
820 else {
821 if (dig->dig_encoder)
822 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
823 else
824 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
825 }
826
827 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
828 return;
829
830 args.v1.ucAction = action;
831 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
832 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
833 args.v3.ucPanelMode = panel_mode;
834 else
835 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
836
837 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
838 args.v1.ucLaneNum = dp_lane_count;
839 else if (radeon_encoder->pixel_clock > 165000)
840 args.v1.ucLaneNum = 8;
841 else
842 args.v1.ucLaneNum = 4;
843
844 if (ASIC_IS_DCE5(rdev)) {
845 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
846 if (dp_clock == 270000)
847 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
848 else if (dp_clock == 540000)
849 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
850 }
851 args.v4.acConfig.ucDigSel = dig->dig_encoder;
852 switch (bpc) {
853 case 0:
854 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
855 break;
856 case 6:
857 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
858 break;
859 case 8:
860 default:
861 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
862 break;
863 case 10:
864 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
865 break;
866 case 12:
867 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
868 break;
869 case 16:
870 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
871 break;
872 }
873 if (hpd_id == RADEON_HPD_NONE)
874 args.v4.ucHPD_ID = 0;
875 else
876 args.v4.ucHPD_ID = hpd_id + 1;
877 } else if (ASIC_IS_DCE4(rdev)) {
878 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
879 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
880 args.v3.acConfig.ucDigSel = dig->dig_encoder;
881 switch (bpc) {
882 case 0:
883 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
884 break;
885 case 6:
886 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
887 break;
888 case 8:
889 default:
890 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
891 break;
892 case 10:
893 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
894 break;
895 case 12:
896 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
897 break;
898 case 16:
899 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
900 break;
901 }
902 } else {
903 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
904 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
905 switch (radeon_encoder->encoder_id) {
906 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
907 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
908 break;
909 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
910 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
911 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
912 break;
913 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
914 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
915 break;
916 }
917 if (dig->linkb)
918 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
919 else
920 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
921 }
922
923 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
924
925}
926
927union dig_transmitter_control {
928 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
929 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
930 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
931 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
932};
933
934void
935atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
936{
937 struct drm_device *dev = encoder->dev;
938 struct radeon_device *rdev = dev->dev_private;
939 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
940 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
941 struct drm_connector *connector;
942 union dig_transmitter_control args;
943 int index = 0;
944 uint8_t frev, crev;
945 bool is_dp = false;
946 int pll_id = 0;
947 int dp_clock = 0;
948 int dp_lane_count = 0;
949 int connector_object_id = 0;
950 int igp_lane_info = 0;
951 int dig_encoder = dig->dig_encoder;
952
953 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
954 connector = radeon_get_connector_for_encoder_init(encoder);
955 /* just needed to avoid bailing in the encoder check. the encoder
956 * isn't used for init
957 */
958 dig_encoder = 0;
959 } else
960 connector = radeon_get_connector_for_encoder(encoder);
961
962 if (connector) {
963 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
964 struct radeon_connector_atom_dig *dig_connector =
965 radeon_connector->con_priv;
966
967 dp_clock = dig_connector->dp_clock;
968 dp_lane_count = dig_connector->dp_lane_count;
969 connector_object_id =
970 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
971 igp_lane_info = dig_connector->igp_lane_info;
972 }
973
974 /* no dig encoder assigned */
975 if (dig_encoder == -1)
976 return;
977
978 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
979 is_dp = true;
980
981 memset(&args, 0, sizeof(args));
982
983 switch (radeon_encoder->encoder_id) {
984 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
985 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
986 break;
987 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
988 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
990 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
991 break;
992 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
993 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
994 break;
995 }
996
997 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
998 return;
999
1000 args.v1.ucAction = action;
1001 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1002 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1003 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1004 args.v1.asMode.ucLaneSel = lane_num;
1005 args.v1.asMode.ucLaneSet = lane_set;
1006 } else {
1007 if (is_dp)
1008 args.v1.usPixelClock =
1009 cpu_to_le16(dp_clock / 10);
1010 else if (radeon_encoder->pixel_clock > 165000)
1011 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1012 else
1013 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1014 }
1015 if (ASIC_IS_DCE4(rdev)) {
1016 if (is_dp)
1017 args.v3.ucLaneNum = dp_lane_count;
1018 else if (radeon_encoder->pixel_clock > 165000)
1019 args.v3.ucLaneNum = 8;
1020 else
1021 args.v3.ucLaneNum = 4;
1022
1023 if (dig->linkb)
1024 args.v3.acConfig.ucLinkSel = 1;
1025 if (dig_encoder & 1)
1026 args.v3.acConfig.ucEncoderSel = 1;
1027
1028 /* Select the PLL for the PHY
1029 * DP PHY should be clocked from external src if there is
1030 * one.
1031 */
1032 if (encoder->crtc) {
1033 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1034 pll_id = radeon_crtc->pll_id;
1035 }
1036
1037 if (ASIC_IS_DCE5(rdev)) {
1038 /* On DCE5 DCPLL usually generates the DP ref clock */
1039 if (is_dp) {
1040 if (rdev->clock.dp_extclk)
1041 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1042 else
1043 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1044 } else
1045 args.v4.acConfig.ucRefClkSource = pll_id;
1046 } else {
1047 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1048 if (is_dp && rdev->clock.dp_extclk)
1049 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1050 else
1051 args.v3.acConfig.ucRefClkSource = pll_id;
1052 }
1053
1054 switch (radeon_encoder->encoder_id) {
1055 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1056 args.v3.acConfig.ucTransmitterSel = 0;
1057 break;
1058 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1059 args.v3.acConfig.ucTransmitterSel = 1;
1060 break;
1061 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1062 args.v3.acConfig.ucTransmitterSel = 2;
1063 break;
1064 }
1065
1066 if (is_dp)
1067 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1068 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1069 if (dig->coherent_mode)
1070 args.v3.acConfig.fCoherentMode = 1;
1071 if (radeon_encoder->pixel_clock > 165000)
1072 args.v3.acConfig.fDualLinkConnector = 1;
1073 }
1074 } else if (ASIC_IS_DCE32(rdev)) {
1075 args.v2.acConfig.ucEncoderSel = dig_encoder;
1076 if (dig->linkb)
1077 args.v2.acConfig.ucLinkSel = 1;
1078
1079 switch (radeon_encoder->encoder_id) {
1080 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1081 args.v2.acConfig.ucTransmitterSel = 0;
1082 break;
1083 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1084 args.v2.acConfig.ucTransmitterSel = 1;
1085 break;
1086 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1087 args.v2.acConfig.ucTransmitterSel = 2;
1088 break;
1089 }
1090
1091 if (is_dp) {
1092 args.v2.acConfig.fCoherentMode = 1;
1093 args.v2.acConfig.fDPConnector = 1;
1094 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1095 if (dig->coherent_mode)
1096 args.v2.acConfig.fCoherentMode = 1;
1097 if (radeon_encoder->pixel_clock > 165000)
1098 args.v2.acConfig.fDualLinkConnector = 1;
1099 }
1100 } else {
1101 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1102
1103 if (dig_encoder)
1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1105 else
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1107
1108 if ((rdev->flags & RADEON_IS_IGP) &&
1109 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1110 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1111 if (igp_lane_info & 0x1)
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1113 else if (igp_lane_info & 0x2)
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1115 else if (igp_lane_info & 0x4)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1117 else if (igp_lane_info & 0x8)
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1119 } else {
1120 if (igp_lane_info & 0x3)
1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1122 else if (igp_lane_info & 0xc)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1124 }
1125 }
1126
1127 if (dig->linkb)
1128 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1129 else
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1131
1132 if (is_dp)
1133 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1134 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1135 if (dig->coherent_mode)
1136 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1137 if (radeon_encoder->pixel_clock > 165000)
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1139 }
1140 }
1141
1142 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1143}
1144
1145bool
1146atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1147{
1148 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1149 struct drm_device *dev = radeon_connector->base.dev;
1150 struct radeon_device *rdev = dev->dev_private;
1151 union dig_transmitter_control args;
1152 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1153 uint8_t frev, crev;
1154
1155 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1156 goto done;
1157
1158 if (!ASIC_IS_DCE4(rdev))
1159 goto done;
1160
1161 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1162 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1163 goto done;
1164
1165 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1166 goto done;
1167
1168 memset(&args, 0, sizeof(args));
1169
1170 args.v1.ucAction = action;
1171
1172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1173
1174 /* wait for the panel to power up */
1175 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1176 int i;
1177
1178 for (i = 0; i < 300; i++) {
1179 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1180 return true;
1181 mdelay(1);
1182 }
1183 return false;
1184 }
1185done:
1186 return true;
1187}
1188
1189union external_encoder_control {
1190 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1191 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1192};
1193
1194static void
1195atombios_external_encoder_setup(struct drm_encoder *encoder,
1196 struct drm_encoder *ext_encoder,
1197 int action)
1198{
1199 struct drm_device *dev = encoder->dev;
1200 struct radeon_device *rdev = dev->dev_private;
1201 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1202 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1203 union external_encoder_control args;
1204 struct drm_connector *connector;
1205 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1206 u8 frev, crev;
1207 int dp_clock = 0;
1208 int dp_lane_count = 0;
1209 int connector_object_id = 0;
1210 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1211 int bpc = 8;
1212
1213 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1214 connector = radeon_get_connector_for_encoder_init(encoder);
1215 else
1216 connector = radeon_get_connector_for_encoder(encoder);
1217
1218 if (connector) {
1219 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1220 struct radeon_connector_atom_dig *dig_connector =
1221 radeon_connector->con_priv;
1222
1223 dp_clock = dig_connector->dp_clock;
1224 dp_lane_count = dig_connector->dp_lane_count;
1225 connector_object_id =
1226 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1227 bpc = connector->display_info.bpc;
1228 }
1229
1230 memset(&args, 0, sizeof(args));
1231
1232 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1233 return;
1234
1235 switch (frev) {
1236 case 1:
1237 /* no params on frev 1 */
1238 break;
1239 case 2:
1240 switch (crev) {
1241 case 1:
1242 case 2:
1243 args.v1.sDigEncoder.ucAction = action;
1244 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1245 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1246
1247 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1248 if (dp_clock == 270000)
1249 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1250 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1251 } else if (radeon_encoder->pixel_clock > 165000)
1252 args.v1.sDigEncoder.ucLaneNum = 8;
1253 else
1254 args.v1.sDigEncoder.ucLaneNum = 4;
1255 break;
1256 case 3:
1257 args.v3.sExtEncoder.ucAction = action;
1258 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1259 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1260 else
1261 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1262 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1263
1264 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1265 if (dp_clock == 270000)
1266 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1267 else if (dp_clock == 540000)
1268 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1269 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1270 } else if (radeon_encoder->pixel_clock > 165000)
1271 args.v3.sExtEncoder.ucLaneNum = 8;
1272 else
1273 args.v3.sExtEncoder.ucLaneNum = 4;
1274 switch (ext_enum) {
1275 case GRAPH_OBJECT_ENUM_ID1:
1276 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1277 break;
1278 case GRAPH_OBJECT_ENUM_ID2:
1279 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1280 break;
1281 case GRAPH_OBJECT_ENUM_ID3:
1282 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1283 break;
1284 }
1285 switch (bpc) {
1286 case 0:
1287 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1288 break;
1289 case 6:
1290 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1291 break;
1292 case 8:
1293 default:
1294 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1295 break;
1296 case 10:
1297 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1298 break;
1299 case 12:
1300 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1301 break;
1302 case 16:
1303 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1304 break;
1305 }
1306 break;
1307 default:
1308 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1309 return;
1310 }
1311 break;
1312 default:
1313 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1314 return;
1315 }
1316 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1317}
1318
1319static void
1320atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1321{
1322 struct drm_device *dev = encoder->dev;
1323 struct radeon_device *rdev = dev->dev_private;
1324 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1325 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1326 ENABLE_YUV_PS_ALLOCATION args;
1327 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1328 uint32_t temp, reg;
1329
1330 memset(&args, 0, sizeof(args));
1331
1332 if (rdev->family >= CHIP_R600)
1333 reg = R600_BIOS_3_SCRATCH;
1334 else
1335 reg = RADEON_BIOS_3_SCRATCH;
1336
1337 /* XXX: fix up scratch reg handling */
1338 temp = RREG32(reg);
1339 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1340 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1341 (radeon_crtc->crtc_id << 18)));
1342 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1343 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1344 else
1345 WREG32(reg, 0);
1346
1347 if (enable)
1348 args.ucEnable = ATOM_ENABLE;
1349 args.ucCRTC = radeon_crtc->crtc_id;
1350
1351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1352
1353 WREG32(reg, temp);
1354}
1355
1356static void
1357radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1358{
1359 struct drm_device *dev = encoder->dev;
1360 struct radeon_device *rdev = dev->dev_private;
1361 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1362 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1363 int index = 0;
1364
1365 memset(&args, 0, sizeof(args));
1366
1367 switch (radeon_encoder->encoder_id) {
1368 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1369 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1370 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1371 break;
1372 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1373 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1374 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1375 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1376 break;
1377 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1378 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1379 break;
1380 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1381 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1382 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1383 else
1384 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1385 break;
1386 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1387 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1388 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1389 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1390 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1391 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1392 else
1393 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1394 break;
1395 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1396 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1397 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1398 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1399 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1400 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1401 else
1402 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1403 break;
1404 default:
1405 return;
1406 }
1407
1408 switch (mode) {
1409 case DRM_MODE_DPMS_ON:
1410 args.ucAction = ATOM_ENABLE;
1411 /* workaround for DVOOutputControl on some RS690 systems */
1412 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1413 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1414 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1415 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1416 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1417 } else
1418 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1419 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1420 args.ucAction = ATOM_LCD_BLON;
1421 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1422 }
1423 break;
1424 case DRM_MODE_DPMS_STANDBY:
1425 case DRM_MODE_DPMS_SUSPEND:
1426 case DRM_MODE_DPMS_OFF:
1427 args.ucAction = ATOM_DISABLE;
1428 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1429 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1430 args.ucAction = ATOM_LCD_BLOFF;
1431 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1432 }
1433 break;
1434 }
1435}
1436
1437static void
1438radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1439{
1440 struct drm_device *dev = encoder->dev;
1441 struct radeon_device *rdev = dev->dev_private;
1442 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1443 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1444 struct radeon_connector *radeon_connector = NULL;
1445 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1446
1447 if (connector) {
1448 radeon_connector = to_radeon_connector(connector);
1449 radeon_dig_connector = radeon_connector->con_priv;
1450 }
1451
1452 switch (mode) {
1453 case DRM_MODE_DPMS_ON:
1454 /* some early dce3.2 boards have a bug in their transmitter control table */
1455 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1456 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1457 else
1458 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1459 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1460 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1461 atombios_set_edp_panel_power(connector,
1462 ATOM_TRANSMITTER_ACTION_POWER_ON);
1463 radeon_dig_connector->edp_on = true;
1464 }
1465 if (ASIC_IS_DCE4(rdev))
1466 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1467 radeon_dp_link_train(encoder, connector);
1468 if (ASIC_IS_DCE4(rdev))
1469 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1470 }
1471 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1472 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1473 break;
1474 case DRM_MODE_DPMS_STANDBY:
1475 case DRM_MODE_DPMS_SUSPEND:
1476 case DRM_MODE_DPMS_OFF:
1477 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1478 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1479 if (ASIC_IS_DCE4(rdev))
1480 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1481 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1482 atombios_set_edp_panel_power(connector,
1483 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1484 radeon_dig_connector->edp_on = false;
1485 }
1486 }
1487 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1488 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1489 break;
1490 }
1491}
1492
1493static void
1494radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1495 struct drm_encoder *ext_encoder,
1496 int mode)
1497{
1498 struct drm_device *dev = encoder->dev;
1499 struct radeon_device *rdev = dev->dev_private;
1500
1501 switch (mode) {
1502 case DRM_MODE_DPMS_ON:
1503 default:
1504 if (ASIC_IS_DCE41(rdev)) {
1505 atombios_external_encoder_setup(encoder, ext_encoder,
1506 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1507 atombios_external_encoder_setup(encoder, ext_encoder,
1508 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1509 } else
1510 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1511 break;
1512 case DRM_MODE_DPMS_STANDBY:
1513 case DRM_MODE_DPMS_SUSPEND:
1514 case DRM_MODE_DPMS_OFF:
1515 if (ASIC_IS_DCE41(rdev)) {
1516 atombios_external_encoder_setup(encoder, ext_encoder,
1517 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1518 atombios_external_encoder_setup(encoder, ext_encoder,
1519 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1520 } else
1521 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1522 break;
1523 }
1524}
1525
1526static void
1527radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1528{
1529 struct drm_device *dev = encoder->dev;
1530 struct radeon_device *rdev = dev->dev_private;
1531 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1532 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1533
1534 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1535 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1536 radeon_encoder->active_device);
1537 switch (radeon_encoder->encoder_id) {
1538 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1539 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1540 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1541 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1542 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1543 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1544 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1545 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1546 radeon_atom_encoder_dpms_avivo(encoder, mode);
1547 break;
1548 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1549 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1550 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1551 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1552 radeon_atom_encoder_dpms_dig(encoder, mode);
1553 break;
1554 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1555 if (ASIC_IS_DCE5(rdev)) {
1556 switch (mode) {
1557 case DRM_MODE_DPMS_ON:
1558 atombios_dvo_setup(encoder, ATOM_ENABLE);
1559 break;
1560 case DRM_MODE_DPMS_STANDBY:
1561 case DRM_MODE_DPMS_SUSPEND:
1562 case DRM_MODE_DPMS_OFF:
1563 atombios_dvo_setup(encoder, ATOM_DISABLE);
1564 break;
1565 }
1566 } else if (ASIC_IS_DCE3(rdev))
1567 radeon_atom_encoder_dpms_dig(encoder, mode);
1568 else
1569 radeon_atom_encoder_dpms_avivo(encoder, mode);
1570 break;
1571 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1572 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1573 if (ASIC_IS_DCE5(rdev)) {
1574 switch (mode) {
1575 case DRM_MODE_DPMS_ON:
1576 atombios_dac_setup(encoder, ATOM_ENABLE);
1577 break;
1578 case DRM_MODE_DPMS_STANDBY:
1579 case DRM_MODE_DPMS_SUSPEND:
1580 case DRM_MODE_DPMS_OFF:
1581 atombios_dac_setup(encoder, ATOM_DISABLE);
1582 break;
1583 }
1584 } else
1585 radeon_atom_encoder_dpms_avivo(encoder, mode);
1586 break;
1587 default:
1588 return;
1589 }
1590
1591 if (ext_encoder)
1592 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1593
1594 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1595
1596}
1597
1598union crtc_source_param {
1599 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1600 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1601};
1602
1603static void
1604atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1605{
1606 struct drm_device *dev = encoder->dev;
1607 struct radeon_device *rdev = dev->dev_private;
1608 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1609 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1610 union crtc_source_param args;
1611 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1612 uint8_t frev, crev;
1613 struct radeon_encoder_atom_dig *dig;
1614
1615 memset(&args, 0, sizeof(args));
1616
1617 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1618 return;
1619
1620 switch (frev) {
1621 case 1:
1622 switch (crev) {
1623 case 1:
1624 default:
1625 if (ASIC_IS_AVIVO(rdev))
1626 args.v1.ucCRTC = radeon_crtc->crtc_id;
1627 else {
1628 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1629 args.v1.ucCRTC = radeon_crtc->crtc_id;
1630 } else {
1631 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1632 }
1633 }
1634 switch (radeon_encoder->encoder_id) {
1635 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1636 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1637 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1638 break;
1639 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1640 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1641 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1642 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1643 else
1644 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1645 break;
1646 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1647 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1649 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1650 break;
1651 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1652 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1653 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1654 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1655 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1656 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1657 else
1658 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1659 break;
1660 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1661 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1662 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1663 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1664 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1665 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1666 else
1667 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1668 break;
1669 }
1670 break;
1671 case 2:
1672 args.v2.ucCRTC = radeon_crtc->crtc_id;
1673 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1674 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1675
1676 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1677 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1678 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1679 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1680 else
1681 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1682 } else
1683 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1684 switch (radeon_encoder->encoder_id) {
1685 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1686 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1687 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1688 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1689 dig = radeon_encoder->enc_priv;
1690 switch (dig->dig_encoder) {
1691 case 0:
1692 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1693 break;
1694 case 1:
1695 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1696 break;
1697 case 2:
1698 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1699 break;
1700 case 3:
1701 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1702 break;
1703 case 4:
1704 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1705 break;
1706 case 5:
1707 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1708 break;
1709 }
1710 break;
1711 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1712 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1713 break;
1714 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1715 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1716 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1717 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1718 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1719 else
1720 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1721 break;
1722 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1723 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1724 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1725 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1726 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1727 else
1728 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1729 break;
1730 }
1731 break;
1732 }
1733 break;
1734 default:
1735 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1736 return;
1737 }
1738
1739 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1740
1741 /* update scratch regs with new routing */
1742 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1743}
1744
1745static void
1746atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1747 struct drm_display_mode *mode)
1748{
1749 struct drm_device *dev = encoder->dev;
1750 struct radeon_device *rdev = dev->dev_private;
1751 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1752 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1753
1754 /* Funky macbooks */
1755 if ((dev->pdev->device == 0x71C5) &&
1756 (dev->pdev->subsystem_vendor == 0x106b) &&
1757 (dev->pdev->subsystem_device == 0x0080)) {
1758 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1759 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1760
1761 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1762 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1763
1764 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1765 }
1766 }
1767
1768 /* set scaler clears this on some chips */
1769 if (ASIC_IS_AVIVO(rdev) &&
1770 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1771 if (ASIC_IS_DCE4(rdev)) {
1772 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1773 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1774 EVERGREEN_INTERLEAVE_EN);
1775 else
1776 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1777 } else {
1778 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1779 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1780 AVIVO_D1MODE_INTERLEAVE_EN);
1781 else
1782 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1783 }
1784 }
1785}
1786
1787static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1788{
1789 struct drm_device *dev = encoder->dev;
1790 struct radeon_device *rdev = dev->dev_private;
1791 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1792 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1793 struct drm_encoder *test_encoder;
1794 struct radeon_encoder_atom_dig *dig;
1795 uint32_t dig_enc_in_use = 0;
1796
1797 /* DCE4/5 */
1798 if (ASIC_IS_DCE4(rdev)) {
1799 dig = radeon_encoder->enc_priv;
1800 if (ASIC_IS_DCE41(rdev)) {
1801 /* ontario follows DCE4 */
1802 if (rdev->family == CHIP_PALM) {
1803 if (dig->linkb)
1804 return 1;
1805 else
1806 return 0;
1807 } else
1808 /* llano follows DCE3.2 */
1809 return radeon_crtc->crtc_id;
1810 } else {
1811 switch (radeon_encoder->encoder_id) {
1812 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1813 if (dig->linkb)
1814 return 1;
1815 else
1816 return 0;
1817 break;
1818 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1819 if (dig->linkb)
1820 return 3;
1821 else
1822 return 2;
1823 break;
1824 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1825 if (dig->linkb)
1826 return 5;
1827 else
1828 return 4;
1829 break;
1830 }
1831 }
1832 }
1833
1834 /* on DCE32 and encoder can driver any block so just crtc id */
1835 if (ASIC_IS_DCE32(rdev)) {
1836 return radeon_crtc->crtc_id;
1837 }
1838
1839 /* on DCE3 - LVTMA can only be driven by DIGB */
1840 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1841 struct radeon_encoder *radeon_test_encoder;
1842
1843 if (encoder == test_encoder)
1844 continue;
1845
1846 if (!radeon_encoder_is_digital(test_encoder))
1847 continue;
1848
1849 radeon_test_encoder = to_radeon_encoder(test_encoder);
1850 dig = radeon_test_encoder->enc_priv;
1851
1852 if (dig->dig_encoder >= 0)
1853 dig_enc_in_use |= (1 << dig->dig_encoder);
1854 }
1855
1856 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1857 if (dig_enc_in_use & 0x2)
1858 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1859 return 1;
1860 }
1861 if (!(dig_enc_in_use & 1))
1862 return 0;
1863 return 1;
1864}
1865
1866/* This only needs to be called once at startup */
1867void
1868radeon_atom_encoder_init(struct radeon_device *rdev)
1869{
1870 struct drm_device *dev = rdev->ddev;
1871 struct drm_encoder *encoder;
1872
1873 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1874 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1875 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1876
1877 switch (radeon_encoder->encoder_id) {
1878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1881 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1882 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1883 break;
1884 default:
1885 break;
1886 }
1887
1888 if (ext_encoder && ASIC_IS_DCE41(rdev))
1889 atombios_external_encoder_setup(encoder, ext_encoder,
1890 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1891 }
1892}
1893
1894static void
1895radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1896 struct drm_display_mode *mode,
1897 struct drm_display_mode *adjusted_mode)
1898{
1899 struct drm_device *dev = encoder->dev;
1900 struct radeon_device *rdev = dev->dev_private;
1901 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1902 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1903
1904 radeon_encoder->pixel_clock = adjusted_mode->clock;
1905
1906 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1907 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1908 atombios_yuv_setup(encoder, true);
1909 else
1910 atombios_yuv_setup(encoder, false);
1911 }
1912
1913 switch (radeon_encoder->encoder_id) {
1914 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1915 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1916 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1917 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1918 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1919 break;
1920 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1921 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1922 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1923 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1924 if (ASIC_IS_DCE4(rdev)) {
1925 /* disable the transmitter */
1926 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1927 /* setup and enable the encoder */
1928 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1929
1930 /* enable the transmitter */
1931 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1932 } else {
1933 /* disable the encoder and transmitter */
1934 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1935 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1936
1937 /* setup and enable the encoder and transmitter */
1938 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1939 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1940 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1941 }
1942 break;
1943 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1944 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1945 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1946 atombios_dvo_setup(encoder, ATOM_ENABLE);
1947 break;
1948 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1949 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1950 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1951 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1952 atombios_dac_setup(encoder, ATOM_ENABLE);
1953 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1954 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1955 atombios_tv_setup(encoder, ATOM_ENABLE);
1956 else
1957 atombios_tv_setup(encoder, ATOM_DISABLE);
1958 }
1959 break;
1960 }
1961
1962 if (ext_encoder) {
1963 if (ASIC_IS_DCE41(rdev))
1964 atombios_external_encoder_setup(encoder, ext_encoder,
1965 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1966 else
1967 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1968 }
1969
1970 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1971
1972 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1973 r600_hdmi_enable(encoder);
1974 r600_hdmi_setmode(encoder, adjusted_mode);
1975 }
1976}
1977
1978static bool
1979atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1980{
1981 struct drm_device *dev = encoder->dev;
1982 struct radeon_device *rdev = dev->dev_private;
1983 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1984 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1985
1986 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1987 ATOM_DEVICE_CV_SUPPORT |
1988 ATOM_DEVICE_CRT_SUPPORT)) {
1989 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1990 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1991 uint8_t frev, crev;
1992
1993 memset(&args, 0, sizeof(args));
1994
1995 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1996 return false;
1997
1998 args.sDacload.ucMisc = 0;
1999
2000 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2001 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2002 args.sDacload.ucDacType = ATOM_DAC_A;
2003 else
2004 args.sDacload.ucDacType = ATOM_DAC_B;
2005
2006 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2007 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2008 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2009 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2010 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2011 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2012 if (crev >= 3)
2013 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2014 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2015 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2016 if (crev >= 3)
2017 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2018 }
2019
2020 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2021
2022 return true;
2023 } else
2024 return false;
2025}
2026
2027static enum drm_connector_status
2028radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2029{
2030 struct drm_device *dev = encoder->dev;
2031 struct radeon_device *rdev = dev->dev_private;
2032 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2033 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2034 uint32_t bios_0_scratch;
2035
2036 if (!atombios_dac_load_detect(encoder, connector)) {
2037 DRM_DEBUG_KMS("detect returned false \n");
2038 return connector_status_unknown;
2039 }
2040
2041 if (rdev->family >= CHIP_R600)
2042 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2043 else
2044 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2045
2046 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2047 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2048 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2049 return connector_status_connected;
2050 }
2051 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2052 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2053 return connector_status_connected;
2054 }
2055 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2056 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2057 return connector_status_connected;
2058 }
2059 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2060 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2061 return connector_status_connected; /* CTV */
2062 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2063 return connector_status_connected; /* STV */
2064 }
2065 return connector_status_disconnected;
2066}
2067
2068static enum drm_connector_status
2069radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2070{
2071 struct drm_device *dev = encoder->dev;
2072 struct radeon_device *rdev = dev->dev_private;
2073 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2074 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2075 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2076 u32 bios_0_scratch;
2077
2078 if (!ASIC_IS_DCE4(rdev))
2079 return connector_status_unknown;
2080
2081 if (!ext_encoder)
2082 return connector_status_unknown;
2083
2084 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2085 return connector_status_unknown;
2086
2087 /* load detect on the dp bridge */
2088 atombios_external_encoder_setup(encoder, ext_encoder,
2089 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2090
2091 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2092
2093 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2094 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2095 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2096 return connector_status_connected;
2097 }
2098 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2099 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2100 return connector_status_connected;
2101 }
2102 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2103 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2104 return connector_status_connected;
2105 }
2106 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2107 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2108 return connector_status_connected; /* CTV */
2109 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2110 return connector_status_connected; /* STV */
2111 }
2112 return connector_status_disconnected;
2113}
2114
2115void
2116radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2117{
2118 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
2119
2120 if (ext_encoder)
2121 /* ddc_setup on the dp bridge */
2122 atombios_external_encoder_setup(encoder, ext_encoder,
2123 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2124
2125}
2126
2127static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2128{
2129 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2130 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2131
2132 if ((radeon_encoder->active_device &
2133 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2134 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2135 ENCODER_OBJECT_ID_NONE)) {
2136 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2137 if (dig)
2138 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2139 }
2140
2141 radeon_atom_output_lock(encoder, true);
2142 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2143
2144 if (connector) {
2145 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2146
2147 /* select the clock/data port if it uses a router */
2148 if (radeon_connector->router.cd_valid)
2149 radeon_router_select_cd_port(radeon_connector);
2150
2151 /* turn eDP panel on for mode set */
2152 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2153 atombios_set_edp_panel_power(connector,
2154 ATOM_TRANSMITTER_ACTION_POWER_ON);
2155 }
2156
2157 /* this is needed for the pll/ss setup to work correctly in some cases */
2158 atombios_set_encoder_crtc_source(encoder);
2159}
2160
2161static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2162{
2163 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2164 radeon_atom_output_lock(encoder, false);
2165}
2166
2167static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2168{
2169 struct drm_device *dev = encoder->dev;
2170 struct radeon_device *rdev = dev->dev_private;
2171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2172 struct radeon_encoder_atom_dig *dig;
2173
2174 /* check for pre-DCE3 cards with shared encoders;
2175 * can't really use the links individually, so don't disable
2176 * the encoder if it's in use by another connector
2177 */
2178 if (!ASIC_IS_DCE3(rdev)) {
2179 struct drm_encoder *other_encoder;
2180 struct radeon_encoder *other_radeon_encoder;
2181
2182 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2183 other_radeon_encoder = to_radeon_encoder(other_encoder);
2184 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2185 drm_helper_encoder_in_use(other_encoder))
2186 goto disable_done;
2187 }
2188 }
2189
2190 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2191
2192 switch (radeon_encoder->encoder_id) {
2193 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2194 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2195 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2196 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2197 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2198 break;
2199 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2200 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2201 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2202 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2203 if (ASIC_IS_DCE4(rdev))
2204 /* disable the transmitter */
2205 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2206 else {
2207 /* disable the encoder and transmitter */
2208 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2209 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2210 }
2211 break;
2212 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2213 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2214 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2215 atombios_dvo_setup(encoder, ATOM_DISABLE);
2216 break;
2217 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2218 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2219 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2220 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2221 atombios_dac_setup(encoder, ATOM_DISABLE);
2222 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2223 atombios_tv_setup(encoder, ATOM_DISABLE);
2224 break;
2225 }
2226
2227disable_done:
2228 if (radeon_encoder_is_digital(encoder)) {
2229 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2230 r600_hdmi_disable(encoder);
2231 dig = radeon_encoder->enc_priv;
2232 dig->dig_encoder = -1;
2233 }
2234 radeon_encoder->active_device = 0;
2235}
2236
2237/* these are handled by the primary encoders */
2238static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2239{
2240
2241}
2242
2243static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2244{
2245
2246}
2247
2248static void
2249radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2250 struct drm_display_mode *mode,
2251 struct drm_display_mode *adjusted_mode)
2252{
2253
2254}
2255
2256static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2257{
2258
2259}
2260
2261static void
2262radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2263{
2264
2265}
2266
2267static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2268 struct drm_display_mode *mode,
2269 struct drm_display_mode *adjusted_mode)
2270{
2271 return true;
2272}
2273
2274static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2275 .dpms = radeon_atom_ext_dpms,
2276 .mode_fixup = radeon_atom_ext_mode_fixup,
2277 .prepare = radeon_atom_ext_prepare,
2278 .mode_set = radeon_atom_ext_mode_set,
2279 .commit = radeon_atom_ext_commit,
2280 .disable = radeon_atom_ext_disable,
2281 /* no detect for TMDS/LVDS yet */
2282};
2283
2284static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2285 .dpms = radeon_atom_encoder_dpms,
2286 .mode_fixup = radeon_atom_mode_fixup,
2287 .prepare = radeon_atom_encoder_prepare,
2288 .mode_set = radeon_atom_encoder_mode_set,
2289 .commit = radeon_atom_encoder_commit,
2290 .disable = radeon_atom_encoder_disable,
2291 .detect = radeon_atom_dig_detect,
2292};
2293
2294static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2295 .dpms = radeon_atom_encoder_dpms,
2296 .mode_fixup = radeon_atom_mode_fixup,
2297 .prepare = radeon_atom_encoder_prepare,
2298 .mode_set = radeon_atom_encoder_mode_set,
2299 .commit = radeon_atom_encoder_commit,
2300 .detect = radeon_atom_dac_detect,
2301};
2302
2303void radeon_enc_destroy(struct drm_encoder *encoder)
2304{
2305 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2306 kfree(radeon_encoder->enc_priv);
2307 drm_encoder_cleanup(encoder);
2308 kfree(radeon_encoder);
2309}
2310
2311static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2312 .destroy = radeon_enc_destroy,
2313};
2314
2315struct radeon_encoder_atom_dac *
2316radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2317{
2318 struct drm_device *dev = radeon_encoder->base.dev;
2319 struct radeon_device *rdev = dev->dev_private;
2320 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2321
2322 if (!dac)
2323 return NULL;
2324
2325 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2326 return dac;
2327}
2328
2329struct radeon_encoder_atom_dig *
2330radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2331{
2332 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2333 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2334
2335 if (!dig)
2336 return NULL;
2337
2338 /* coherent mode by default */
2339 dig->coherent_mode = true;
2340 dig->dig_encoder = -1;
2341
2342 if (encoder_enum == 2)
2343 dig->linkb = true;
2344 else
2345 dig->linkb = false;
2346
2347 return dig;
2348}
2349
2350void
2351radeon_add_atom_encoder(struct drm_device *dev,
2352 uint32_t encoder_enum,
2353 uint32_t supported_device,
2354 u16 caps)
2355{
2356 struct radeon_device *rdev = dev->dev_private;
2357 struct drm_encoder *encoder;
2358 struct radeon_encoder *radeon_encoder;
2359
2360 /* see if we already added it */
2361 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2362 radeon_encoder = to_radeon_encoder(encoder);
2363 if (radeon_encoder->encoder_enum == encoder_enum) {
2364 radeon_encoder->devices |= supported_device;
2365 return;
2366 }
2367
2368 }
2369
2370 /* add a new one */
2371 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2372 if (!radeon_encoder)
2373 return;
2374
2375 encoder = &radeon_encoder->base;
2376 switch (rdev->num_crtc) {
2377 case 1:
2378 encoder->possible_crtcs = 0x1;
2379 break;
2380 case 2:
2381 default:
2382 encoder->possible_crtcs = 0x3;
2383 break;
2384 case 4:
2385 encoder->possible_crtcs = 0xf;
2386 break;
2387 case 6:
2388 encoder->possible_crtcs = 0x3f;
2389 break;
2390 }
2391
2392 radeon_encoder->enc_priv = NULL;
2393
2394 radeon_encoder->encoder_enum = encoder_enum;
2395 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2396 radeon_encoder->devices = supported_device;
2397 radeon_encoder->rmx_type = RMX_OFF;
2398 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2399 radeon_encoder->is_ext_encoder = false;
2400 radeon_encoder->caps = caps;
2401
2402 switch (radeon_encoder->encoder_id) {
2403 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2404 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2405 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2406 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2407 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2408 radeon_encoder->rmx_type = RMX_FULL;
2409 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2410 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2411 } else {
2412 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2413 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2414 }
2415 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2416 break;
2417 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2418 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2419 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2420 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2421 break;
2422 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2423 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2424 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2425 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2426 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2427 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2428 break;
2429 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2431 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2432 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2433 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2434 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2435 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2436 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2437 radeon_encoder->rmx_type = RMX_FULL;
2438 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2439 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2440 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2441 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2442 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2443 } else {
2444 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2445 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2446 }
2447 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2448 break;
2449 case ENCODER_OBJECT_ID_SI170B:
2450 case ENCODER_OBJECT_ID_CH7303:
2451 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2452 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2453 case ENCODER_OBJECT_ID_TITFP513:
2454 case ENCODER_OBJECT_ID_VT1623:
2455 case ENCODER_OBJECT_ID_HDMI_SI1930:
2456 case ENCODER_OBJECT_ID_TRAVIS:
2457 case ENCODER_OBJECT_ID_NUTMEG:
2458 /* these are handled by the primary encoders */
2459 radeon_encoder->is_ext_encoder = true;
2460 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2461 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2462 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2463 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2464 else
2465 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2466 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2467 break;
2468 }
2469}
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index f8e18a904e37..e8860d984b17 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -491,7 +491,7 @@ extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
491 int action, uint8_t lane_num, 491 int action, uint8_t lane_num,
492 uint8_t lane_set); 492 uint8_t lane_set);
493extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 493extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
494extern struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder); 494extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
495extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 495extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
496 u8 write_byte, u8 *read_byte); 496 u8 write_byte, u8 *read_byte);
497 497
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 18:33:40 -0500