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-rw-r--r--drivers/gpu/drm/ast/ast_drv.c3
-rw-r--r--drivers/gpu/drm/ast/ast_mode.c2
-rw-r--r--drivers/gpu/drm/cirrus/cirrus_drv.c3
-rw-r--r--drivers/gpu/drm/drm_crtc.c2
-rw-r--r--drivers/gpu/drm/drm_edid.c3
-rw-r--r--drivers/gpu/drm/exynos/Kconfig2
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_dmabuf.c7
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.c5
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c5
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_g2d.c52
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_gem.c4
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_hdmi.c3
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_plane.c1
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_vidi.c4
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c11
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c6
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_device.c2
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_display.c3
-rw-r--r--drivers/gpu/drm/i810/i810_dma.c3
-rw-r--r--drivers/gpu/drm/i810/i810_drv.c3
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c1
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c2
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c3
-rw-r--r--drivers/gpu/drm/i915/intel_display.c18
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c11
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c8
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c31
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c3
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c15
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c4
-rw-r--r--drivers/gpu/drm/mgag200/mgag200_drv.c3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv50_gpio.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvd0_display.c4
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c199
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c29
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c140
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c30
-rw-r--r--drivers/gpu/drm/radeon/r600d.h8
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c8
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r6001
-rw-r--r--drivers/gpu/drm/savage/savage_drv.c3
-rw-r--r--drivers/gpu/drm/sis/sis_drv.c3
-rw-r--r--drivers/gpu/drm/tdfx/tdfx_drv.c3
-rw-r--r--drivers/gpu/drm/udl/udl_drv.c3
-rw-r--r--drivers/gpu/drm/via/via_drv.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/Kconfig8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h10
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c73
53 files changed, 515 insertions, 260 deletions
diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
index d0c4574ef49c..36164806b9d4 100644
--- a/drivers/gpu/drm/ast/ast_drv.c
+++ b/drivers/gpu/drm/ast/ast_drv.c
@@ -193,6 +193,9 @@ static const struct file_operations ast_fops = {
193 .mmap = ast_mmap, 193 .mmap = ast_mmap,
194 .poll = drm_poll, 194 .poll = drm_poll,
195 .fasync = drm_fasync, 195 .fasync = drm_fasync,
196#ifdef CONFIG_COMPAT
197 .compat_ioctl = drm_compat_ioctl,
198#endif
196 .read = drm_read, 199 .read = drm_read,
197}; 200};
198 201
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index 7282c081fb53..a712cafcfa1d 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -841,7 +841,7 @@ int ast_cursor_init(struct drm_device *dev)
841 841
842 ast->cursor_cache = obj; 842 ast->cursor_cache = obj;
843 ast->cursor_cache_gpu_addr = gpu_addr; 843 ast->cursor_cache_gpu_addr = gpu_addr;
844 DRM_ERROR("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr); 844 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
845 return 0; 845 return 0;
846fail: 846fail:
847 return ret; 847 return ret;
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c b/drivers/gpu/drm/cirrus/cirrus_drv.c
index 7053140c6596..b83a2d7ddd1a 100644
--- a/drivers/gpu/drm/cirrus/cirrus_drv.c
+++ b/drivers/gpu/drm/cirrus/cirrus_drv.c
@@ -74,6 +74,9 @@ static const struct file_operations cirrus_driver_fops = {
74 .unlocked_ioctl = drm_ioctl, 74 .unlocked_ioctl = drm_ioctl,
75 .mmap = cirrus_mmap, 75 .mmap = cirrus_mmap,
76 .poll = drm_poll, 76 .poll = drm_poll,
77#ifdef CONFIG_COMPAT
78 .compat_ioctl = drm_compat_ioctl,
79#endif
77 .fasync = drm_fasync, 80 .fasync = drm_fasync,
78}; 81};
79static struct drm_driver driver = { 82static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 08a7aa722d6b..6fbfc244748f 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1981,7 +1981,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev,
1981 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 1981 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1982 return -EINVAL; 1982 return -EINVAL;
1983 1983
1984 if (!req->flags) 1984 if (!req->flags || (~DRM_MODE_CURSOR_FLAGS & req->flags))
1985 return -EINVAL; 1985 return -EINVAL;
1986 1986
1987 mutex_lock(&dev->mode_config.mutex); 1987 mutex_lock(&dev->mode_config.mutex);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a8743c399e83..b7ee230572b7 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -87,6 +87,9 @@ static struct edid_quirk {
87 int product_id; 87 int product_id;
88 u32 quirks; 88 u32 quirks;
89} edid_quirk_list[] = { 89} edid_quirk_list[] = {
90 /* ASUS VW222S */
91 { "ACI", 0x22a2, EDID_QUIRK_FORCE_REDUCED_BLANKING },
92
90 /* Acer AL1706 */ 93 /* Acer AL1706 */
91 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
92 /* Acer F51 */ 95 /* Acer F51 */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 7f5096763b7d..59a26e577b57 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -36,6 +36,6 @@ config DRM_EXYNOS_VIDI
36 36
37config DRM_EXYNOS_G2D 37config DRM_EXYNOS_G2D
38 bool "Exynos DRM G2D" 38 bool "Exynos DRM G2D"
39 depends on DRM_EXYNOS 39 depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_G2D
40 help 40 help
41 Choose this option if you want to use Exynos G2D for DRM. 41 Choose this option if you want to use Exynos G2D for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
index 613bf8a5d9b2..ae13febe0eaa 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c
@@ -163,6 +163,12 @@ static void exynos_gem_dmabuf_kunmap(struct dma_buf *dma_buf,
163 /* TODO */ 163 /* TODO */
164} 164}
165 165
166static int exynos_gem_dmabuf_mmap(struct dma_buf *dma_buf,
167 struct vm_area_struct *vma)
168{
169 return -ENOTTY;
170}
171
166static struct dma_buf_ops exynos_dmabuf_ops = { 172static struct dma_buf_ops exynos_dmabuf_ops = {
167 .map_dma_buf = exynos_gem_map_dma_buf, 173 .map_dma_buf = exynos_gem_map_dma_buf,
168 .unmap_dma_buf = exynos_gem_unmap_dma_buf, 174 .unmap_dma_buf = exynos_gem_unmap_dma_buf,
@@ -170,6 +176,7 @@ static struct dma_buf_ops exynos_dmabuf_ops = {
170 .kmap_atomic = exynos_gem_dmabuf_kmap_atomic, 176 .kmap_atomic = exynos_gem_dmabuf_kmap_atomic,
171 .kunmap = exynos_gem_dmabuf_kunmap, 177 .kunmap = exynos_gem_dmabuf_kunmap,
172 .kunmap_atomic = exynos_gem_dmabuf_kunmap_atomic, 178 .kunmap_atomic = exynos_gem_dmabuf_kunmap_atomic,
179 .mmap = exynos_gem_dmabuf_mmap,
173 .release = exynos_dmabuf_release, 180 .release = exynos_dmabuf_release,
174}; 181};
175 182
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index ebacec6f1e48..d07071937453 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -160,7 +160,6 @@ static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
160 if (!file_priv) 160 if (!file_priv)
161 return -ENOMEM; 161 return -ENOMEM;
162 162
163 drm_prime_init_file_private(&file->prime);
164 file->driver_priv = file_priv; 163 file->driver_priv = file_priv;
165 164
166 return exynos_drm_subdrv_open(dev, file); 165 return exynos_drm_subdrv_open(dev, file);
@@ -184,7 +183,6 @@ static void exynos_drm_preclose(struct drm_device *dev,
184 e->base.destroy(&e->base); 183 e->base.destroy(&e->base);
185 } 184 }
186 } 185 }
187 drm_prime_destroy_file_private(&file->prime);
188 spin_unlock_irqrestore(&dev->event_lock, flags); 186 spin_unlock_irqrestore(&dev->event_lock, flags);
189 187
190 exynos_drm_subdrv_close(dev, file); 188 exynos_drm_subdrv_close(dev, file);
@@ -241,6 +239,9 @@ static const struct file_operations exynos_drm_driver_fops = {
241 .poll = drm_poll, 239 .poll = drm_poll,
242 .read = drm_read, 240 .read = drm_read,
243 .unlocked_ioctl = drm_ioctl, 241 .unlocked_ioctl = drm_ioctl,
242#ifdef CONFIG_COMPAT
243 .compat_ioctl = drm_compat_ioctl,
244#endif
244 .release = drm_release, 245 .release = drm_release,
245}; 246};
246 247
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index a68d2b313f03..b19cd93e7047 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -831,11 +831,6 @@ static int __devinit fimd_probe(struct platform_device *pdev)
831 } 831 }
832 832
833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
834 if (!res) {
835 dev_err(dev, "failed to find registers\n");
836 ret = -ENOENT;
837 goto err_clk;
838 }
839 834
840 ctx->regs = devm_request_and_ioremap(&pdev->dev, res); 835 ctx->regs = devm_request_and_ioremap(&pdev->dev, res);
841 if (!ctx->regs) { 836 if (!ctx->regs) {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index d2d88f22a037..1065e90d0919 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -129,7 +129,6 @@ struct g2d_runqueue_node {
129struct g2d_data { 129struct g2d_data {
130 struct device *dev; 130 struct device *dev;
131 struct clk *gate_clk; 131 struct clk *gate_clk;
132 struct resource *regs_res;
133 void __iomem *regs; 132 void __iomem *regs;
134 int irq; 133 int irq;
135 struct workqueue_struct *g2d_workq; 134 struct workqueue_struct *g2d_workq;
@@ -751,7 +750,7 @@ static int __devinit g2d_probe(struct platform_device *pdev)
751 struct exynos_drm_subdrv *subdrv; 750 struct exynos_drm_subdrv *subdrv;
752 int ret; 751 int ret;
753 752
754 g2d = kzalloc(sizeof(*g2d), GFP_KERNEL); 753 g2d = devm_kzalloc(&pdev->dev, sizeof(*g2d), GFP_KERNEL);
755 if (!g2d) { 754 if (!g2d) {
756 dev_err(dev, "failed to allocate driver data\n"); 755 dev_err(dev, "failed to allocate driver data\n");
757 return -ENOMEM; 756 return -ENOMEM;
@@ -759,10 +758,8 @@ static int __devinit g2d_probe(struct platform_device *pdev)
759 758
760 g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab", 759 g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab",
761 sizeof(struct g2d_runqueue_node), 0, 0, NULL); 760 sizeof(struct g2d_runqueue_node), 0, 0, NULL);
762 if (!g2d->runqueue_slab) { 761 if (!g2d->runqueue_slab)
763 ret = -ENOMEM; 762 return -ENOMEM;
764 goto err_free_mem;
765 }
766 763
767 g2d->dev = dev; 764 g2d->dev = dev;
768 765
@@ -794,38 +791,26 @@ static int __devinit g2d_probe(struct platform_device *pdev)
794 pm_runtime_enable(dev); 791 pm_runtime_enable(dev);
795 792
796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
797 if (!res) {
798 dev_err(dev, "failed to get I/O memory\n");
799 ret = -ENOENT;
800 goto err_put_clk;
801 }
802 794
803 g2d->regs_res = request_mem_region(res->start, resource_size(res), 795 g2d->regs = devm_request_and_ioremap(&pdev->dev, res);
804 dev_name(dev));
805 if (!g2d->regs_res) {
806 dev_err(dev, "failed to request I/O memory\n");
807 ret = -ENOENT;
808 goto err_put_clk;
809 }
810
811 g2d->regs = ioremap(res->start, resource_size(res));
812 if (!g2d->regs) { 796 if (!g2d->regs) {
813 dev_err(dev, "failed to remap I/O memory\n"); 797 dev_err(dev, "failed to remap I/O memory\n");
814 ret = -ENXIO; 798 ret = -ENXIO;
815 goto err_release_res; 799 goto err_put_clk;
816 } 800 }
817 801
818 g2d->irq = platform_get_irq(pdev, 0); 802 g2d->irq = platform_get_irq(pdev, 0);
819 if (g2d->irq < 0) { 803 if (g2d->irq < 0) {
820 dev_err(dev, "failed to get irq\n"); 804 dev_err(dev, "failed to get irq\n");
821 ret = g2d->irq; 805 ret = g2d->irq;
822 goto err_unmap_base; 806 goto err_put_clk;
823 } 807 }
824 808
825 ret = request_irq(g2d->irq, g2d_irq_handler, 0, "drm_g2d", g2d); 809 ret = devm_request_irq(&pdev->dev, g2d->irq, g2d_irq_handler, 0,
810 "drm_g2d", g2d);
826 if (ret < 0) { 811 if (ret < 0) {
827 dev_err(dev, "irq request failed\n"); 812 dev_err(dev, "irq request failed\n");
828 goto err_unmap_base; 813 goto err_put_clk;
829 } 814 }
830 815
831 platform_set_drvdata(pdev, g2d); 816 platform_set_drvdata(pdev, g2d);
@@ -838,7 +823,7 @@ static int __devinit g2d_probe(struct platform_device *pdev)
838 ret = exynos_drm_subdrv_register(subdrv); 823 ret = exynos_drm_subdrv_register(subdrv);
839 if (ret < 0) { 824 if (ret < 0) {
840 dev_err(dev, "failed to register drm g2d device\n"); 825 dev_err(dev, "failed to register drm g2d device\n");
841 goto err_free_irq; 826 goto err_put_clk;
842 } 827 }
843 828
844 dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n", 829 dev_info(dev, "The exynos g2d(ver %d.%d) successfully probed\n",
@@ -846,13 +831,6 @@ static int __devinit g2d_probe(struct platform_device *pdev)
846 831
847 return 0; 832 return 0;
848 833
849err_free_irq:
850 free_irq(g2d->irq, g2d);
851err_unmap_base:
852 iounmap(g2d->regs);
853err_release_res:
854 release_resource(g2d->regs_res);
855 kfree(g2d->regs_res);
856err_put_clk: 834err_put_clk:
857 pm_runtime_disable(dev); 835 pm_runtime_disable(dev);
858 clk_put(g2d->gate_clk); 836 clk_put(g2d->gate_clk);
@@ -862,8 +840,6 @@ err_destroy_workqueue:
862 destroy_workqueue(g2d->g2d_workq); 840 destroy_workqueue(g2d->g2d_workq);
863err_destroy_slab: 841err_destroy_slab:
864 kmem_cache_destroy(g2d->runqueue_slab); 842 kmem_cache_destroy(g2d->runqueue_slab);
865err_free_mem:
866 kfree(g2d);
867 return ret; 843 return ret;
868} 844}
869 845
@@ -873,24 +849,18 @@ static int __devexit g2d_remove(struct platform_device *pdev)
873 849
874 cancel_work_sync(&g2d->runqueue_work); 850 cancel_work_sync(&g2d->runqueue_work);
875 exynos_drm_subdrv_unregister(&g2d->subdrv); 851 exynos_drm_subdrv_unregister(&g2d->subdrv);
876 free_irq(g2d->irq, g2d);
877 852
878 while (g2d->runqueue_node) { 853 while (g2d->runqueue_node) {
879 g2d_free_runqueue_node(g2d, g2d->runqueue_node); 854 g2d_free_runqueue_node(g2d, g2d->runqueue_node);
880 g2d->runqueue_node = g2d_get_runqueue_node(g2d); 855 g2d->runqueue_node = g2d_get_runqueue_node(g2d);
881 } 856 }
882 857
883 iounmap(g2d->regs);
884 release_resource(g2d->regs_res);
885 kfree(g2d->regs_res);
886
887 pm_runtime_disable(&pdev->dev); 858 pm_runtime_disable(&pdev->dev);
888 clk_put(g2d->gate_clk); 859 clk_put(g2d->gate_clk);
889 860
890 g2d_fini_cmdlist(g2d); 861 g2d_fini_cmdlist(g2d);
891 destroy_workqueue(g2d->g2d_workq); 862 destroy_workqueue(g2d->g2d_workq);
892 kmem_cache_destroy(g2d->runqueue_slab); 863 kmem_cache_destroy(g2d->runqueue_slab);
893 kfree(g2d);
894 864
895 return 0; 865 return 0;
896} 866}
@@ -924,7 +894,7 @@ static int g2d_resume(struct device *dev)
924} 894}
925#endif 895#endif
926 896
927SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume); 897static SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume);
928 898
929struct platform_driver g2d_driver = { 899struct platform_driver g2d_driver = {
930 .probe = g2d_probe, 900 .probe = g2d_probe,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index f9efde40c097..a38051c95ec4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -122,7 +122,7 @@ fail:
122 __free_page(pages[i]); 122 __free_page(pages[i]);
123 123
124 drm_free_large(pages); 124 drm_free_large(pages);
125 return ERR_PTR(PTR_ERR(p)); 125 return ERR_CAST(p);
126} 126}
127 127
128static void exynos_gem_put_pages(struct drm_gem_object *obj, 128static void exynos_gem_put_pages(struct drm_gem_object *obj,
@@ -662,7 +662,7 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv,
662 */ 662 */
663 663
664 args->pitch = args->width * ((args->bpp + 7) / 8); 664 args->pitch = args->width * ((args->bpp + 7) / 8);
665 args->size = PAGE_ALIGN(args->pitch * args->height); 665 args->size = args->pitch * args->height;
666 666
667 exynos_gem_obj = exynos_drm_gem_create(dev, args->flags, args->size); 667 exynos_gem_obj = exynos_drm_gem_create(dev, args->flags, args->size);
668 if (IS_ERR(exynos_gem_obj)) 668 if (IS_ERR(exynos_gem_obj))
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
index 8ffcdf8b9e22..3fdf0b65f47e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
@@ -345,7 +345,7 @@ static int __devinit exynos_drm_hdmi_probe(struct platform_device *pdev)
345 345
346 DRM_DEBUG_KMS("%s\n", __FILE__); 346 DRM_DEBUG_KMS("%s\n", __FILE__);
347 347
348 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 348 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
349 if (!ctx) { 349 if (!ctx) {
350 DRM_LOG_KMS("failed to alloc common hdmi context.\n"); 350 DRM_LOG_KMS("failed to alloc common hdmi context.\n");
351 return -ENOMEM; 351 return -ENOMEM;
@@ -371,7 +371,6 @@ static int __devexit exynos_drm_hdmi_remove(struct platform_device *pdev)
371 DRM_DEBUG_KMS("%s\n", __FILE__); 371 DRM_DEBUG_KMS("%s\n", __FILE__);
372 372
373 exynos_drm_subdrv_unregister(&ctx->subdrv); 373 exynos_drm_subdrv_unregister(&ctx->subdrv);
374 kfree(ctx);
375 374
376 return 0; 375 return 0;
377} 376}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index b89829e5043a..e1f94b746bd7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -29,7 +29,6 @@ static const uint32_t formats[] = {
29 DRM_FORMAT_XRGB8888, 29 DRM_FORMAT_XRGB8888,
30 DRM_FORMAT_ARGB8888, 30 DRM_FORMAT_ARGB8888,
31 DRM_FORMAT_NV12, 31 DRM_FORMAT_NV12,
32 DRM_FORMAT_NV12M,
33 DRM_FORMAT_NV12MT, 32 DRM_FORMAT_NV12MT,
34}; 33};
35 34
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index bb1550c4dd57..537027a74fd5 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -633,7 +633,7 @@ static int __devinit vidi_probe(struct platform_device *pdev)
633 633
634 DRM_DEBUG_KMS("%s\n", __FILE__); 634 DRM_DEBUG_KMS("%s\n", __FILE__);
635 635
636 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 636 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
637 if (!ctx) 637 if (!ctx)
638 return -ENOMEM; 638 return -ENOMEM;
639 639
@@ -673,8 +673,6 @@ static int __devexit vidi_remove(struct platform_device *pdev)
673 ctx->raw_edid = NULL; 673 ctx->raw_edid = NULL;
674 } 674 }
675 675
676 kfree(ctx);
677
678 return 0; 676 return 0;
679} 677}
680 678
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 409e2ec1207c..a6aea6f3ea1a 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -2172,7 +2172,7 @@ static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
2172 2172
2173 DRM_DEBUG_KMS("HDMI resource init\n"); 2173 DRM_DEBUG_KMS("HDMI resource init\n");
2174 2174
2175 memset(res, 0, sizeof *res); 2175 memset(res, 0, sizeof(*res));
2176 2176
2177 /* get clocks, power */ 2177 /* get clocks, power */
2178 res->hdmi = clk_get(dev, "hdmi"); 2178 res->hdmi = clk_get(dev, "hdmi");
@@ -2204,7 +2204,7 @@ static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
2204 clk_set_parent(res->sclk_hdmi, res->sclk_pixel); 2204 clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
2205 2205
2206 res->regul_bulk = kzalloc(ARRAY_SIZE(supply) * 2206 res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
2207 sizeof res->regul_bulk[0], GFP_KERNEL); 2207 sizeof(res->regul_bulk[0]), GFP_KERNEL);
2208 if (!res->regul_bulk) { 2208 if (!res->regul_bulk) {
2209 DRM_ERROR("failed to get memory for regulators\n"); 2209 DRM_ERROR("failed to get memory for regulators\n");
2210 goto fail; 2210 goto fail;
@@ -2243,7 +2243,7 @@ static int hdmi_resources_cleanup(struct hdmi_context *hdata)
2243 clk_put(res->sclk_hdmi); 2243 clk_put(res->sclk_hdmi);
2244 if (!IS_ERR_OR_NULL(res->hdmi)) 2244 if (!IS_ERR_OR_NULL(res->hdmi))
2245 clk_put(res->hdmi); 2245 clk_put(res->hdmi);
2246 memset(res, 0, sizeof *res); 2246 memset(res, 0, sizeof(*res));
2247 2247
2248 return 0; 2248 return 0;
2249} 2249}
@@ -2312,11 +2312,6 @@ static int __devinit hdmi_probe(struct platform_device *pdev)
2312 } 2312 }
2313 2313
2314 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2314 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2315 if (!res) {
2316 DRM_ERROR("failed to find registers\n");
2317 ret = -ENOENT;
2318 goto err_resource;
2319 }
2320 2315
2321 hdata->regs = devm_request_and_ioremap(&pdev->dev, res); 2316 hdata->regs = devm_request_and_ioremap(&pdev->dev, res);
2322 if (!hdata->regs) { 2317 if (!hdata->regs) {
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 30fcc12f81dd..25b97d5e5fcb 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -236,11 +236,11 @@ static inline void vp_filter_set(struct mixer_resources *res,
236static void vp_default_filter(struct mixer_resources *res) 236static void vp_default_filter(struct mixer_resources *res)
237{ 237{
238 vp_filter_set(res, VP_POLY8_Y0_LL, 238 vp_filter_set(res, VP_POLY8_Y0_LL,
239 filter_y_horiz_tap8, sizeof filter_y_horiz_tap8); 239 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
240 vp_filter_set(res, VP_POLY4_Y0_LL, 240 vp_filter_set(res, VP_POLY4_Y0_LL,
241 filter_y_vert_tap4, sizeof filter_y_vert_tap4); 241 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
242 vp_filter_set(res, VP_POLY4_C0_LL, 242 vp_filter_set(res, VP_POLY4_C0_LL,
243 filter_cr_horiz_tap4, sizeof filter_cr_horiz_tap4); 243 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
244} 244}
245 245
246static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable) 246static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
diff --git a/drivers/gpu/drm/gma500/oaktrail_device.c b/drivers/gpu/drm/gma500/oaktrail_device.c
index 0f9b7db80f6b..cf49ba5a54bf 100644
--- a/drivers/gpu/drm/gma500/oaktrail_device.c
+++ b/drivers/gpu/drm/gma500/oaktrail_device.c
@@ -476,6 +476,7 @@ static const struct psb_offset oaktrail_regmap[2] = {
476 .pos = DSPAPOS, 476 .pos = DSPAPOS,
477 .surf = DSPASURF, 477 .surf = DSPASURF,
478 .addr = MRST_DSPABASE, 478 .addr = MRST_DSPABASE,
479 .base = MRST_DSPABASE,
479 .status = PIPEASTAT, 480 .status = PIPEASTAT,
480 .linoff = DSPALINOFF, 481 .linoff = DSPALINOFF,
481 .tileoff = DSPATILEOFF, 482 .tileoff = DSPATILEOFF,
@@ -499,6 +500,7 @@ static const struct psb_offset oaktrail_regmap[2] = {
499 .pos = DSPBPOS, 500 .pos = DSPBPOS,
500 .surf = DSPBSURF, 501 .surf = DSPBSURF,
501 .addr = DSPBBASE, 502 .addr = DSPBBASE,
503 .base = DSPBBASE,
502 .status = PIPEBSTAT, 504 .status = PIPEBSTAT,
503 .linoff = DSPBLINOFF, 505 .linoff = DSPBLINOFF,
504 .tileoff = DSPBTILEOFF, 506 .tileoff = DSPBTILEOFF,
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index 30dc22a7156c..8033526bb53b 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -1362,6 +1362,9 @@ void psb_intel_crtc_init(struct drm_device *dev, int pipe,
1362 (struct drm_connector **) (psb_intel_crtc + 1); 1362 (struct drm_connector **) (psb_intel_crtc + 1);
1363 psb_intel_crtc->mode_set.num_connectors = 0; 1363 psb_intel_crtc->mode_set.num_connectors = 0;
1364 psb_intel_cursor_init(dev, psb_intel_crtc); 1364 psb_intel_cursor_init(dev, psb_intel_crtc);
1365
1366 /* Set to true so that the pipe is forced off on initial config. */
1367 psb_intel_crtc->active = true;
1365} 1368}
1366 1369
1367int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 1370int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c
index 57d892eaaa6e..463ec6871fe9 100644
--- a/drivers/gpu/drm/i810/i810_dma.c
+++ b/drivers/gpu/drm/i810/i810_dma.c
@@ -115,6 +115,9 @@ static const struct file_operations i810_buffer_fops = {
115 .unlocked_ioctl = drm_ioctl, 115 .unlocked_ioctl = drm_ioctl,
116 .mmap = i810_mmap_buffers, 116 .mmap = i810_mmap_buffers,
117 .fasync = drm_fasync, 117 .fasync = drm_fasync,
118#ifdef CONFIG_COMPAT
119 .compat_ioctl = drm_compat_ioctl,
120#endif
118 .llseek = noop_llseek, 121 .llseek = noop_llseek,
119}; 122};
120 123
diff --git a/drivers/gpu/drm/i810/i810_drv.c b/drivers/gpu/drm/i810/i810_drv.c
index f9924ad04d09..48cfcca2b350 100644
--- a/drivers/gpu/drm/i810/i810_drv.c
+++ b/drivers/gpu/drm/i810/i810_drv.c
@@ -51,6 +51,9 @@ static const struct file_operations i810_driver_fops = {
51 .mmap = drm_mmap, 51 .mmap = drm_mmap,
52 .poll = drm_poll, 52 .poll = drm_poll,
53 .fasync = drm_fasync, 53 .fasync = drm_fasync,
54#ifdef CONFIG_COMPAT
55 .compat_ioctl = drm_compat_ioctl,
56#endif
54 .llseek = noop_llseek, 57 .llseek = noop_llseek,
55}; 58};
56 59
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9cf7dfe022b9..914c0dfabe60 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1587,6 +1587,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1587 spin_lock_init(&dev_priv->irq_lock); 1587 spin_lock_init(&dev_priv->irq_lock);
1588 spin_lock_init(&dev_priv->error_lock); 1588 spin_lock_init(&dev_priv->error_lock);
1589 spin_lock_init(&dev_priv->rps_lock); 1589 spin_lock_init(&dev_priv->rps_lock);
1590 spin_lock_init(&dev_priv->dpio_lock);
1590 1591
1591 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1592 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1592 dev_priv->num_pipe = 3; 1593 dev_priv->num_pipe = 3;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d9a5372ec56f..60815b861ec2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -72,7 +72,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
72 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 72 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
73 * entries. For aliasing ppgtt support we just steal them at the end for 73 * entries. For aliasing ppgtt support we just steal them at the end for
74 * now. */ 74 * now. */
75 first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES; 75 first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
76 76
77 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); 77 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
78 if (!ppgtt) 78 if (!ppgtt)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8a3828528b9d..5249640cce13 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2700,9 +2700,6 @@ void intel_irq_init(struct drm_device *dev)
2700 dev->driver->irq_handler = i8xx_irq_handler; 2700 dev->driver->irq_handler = i8xx_irq_handler;
2701 dev->driver->irq_uninstall = i8xx_irq_uninstall; 2701 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2702 } else if (INTEL_INFO(dev)->gen == 3) { 2702 } else if (INTEL_INFO(dev)->gen == 3) {
2703 /* IIR "flip pending" means done if this bit is set */
2704 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2705
2706 dev->driver->irq_preinstall = i915_irq_preinstall; 2703 dev->driver->irq_preinstall = i915_irq_preinstall;
2707 dev->driver->irq_postinstall = i915_irq_postinstall; 2704 dev->driver->irq_postinstall = i915_irq_postinstall;
2708 dev->driver->irq_uninstall = i915_irq_uninstall; 2705 dev->driver->irq_uninstall = i915_irq_uninstall;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a69a3d0d3acf..bc2ad348e5d8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1376,7 +1376,8 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe)); 1377 reg, pipe_name(pipe));
1378 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), 1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
1380 "IBX PCH dp port still using transcoder B\n"); 1381 "IBX PCH dp port still using transcoder B\n");
1381} 1382}
1382 1383
@@ -1384,11 +1385,12 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg) 1385 enum pipe pipe, int reg)
1385{ 1386{
1386 u32 val = I915_READ(reg); 1387 u32 val = I915_READ(reg);
1387 WARN(hdmi_pipe_enabled(dev_priv, val, pipe), 1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe)); 1390 reg, pipe_name(pipe));
1390 1391
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), 1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n"); 1394 "IBX PCH hdmi port still using transcoder B\n");
1393} 1395}
1394 1396
@@ -1404,13 +1406,13 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1404 1406
1405 reg = PCH_ADPA; 1407 reg = PCH_ADPA;
1406 val = I915_READ(reg); 1408 val = I915_READ(reg);
1407 WARN(adpa_pipe_enabled(dev_priv, val, pipe), 1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n", 1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1409 pipe_name(pipe)); 1411 pipe_name(pipe));
1410 1412
1411 reg = PCH_LVDS; 1413 reg = PCH_LVDS;
1412 val = I915_READ(reg); 1414 val = I915_READ(reg);
1413 WARN(lvds_pipe_enabled(dev_priv, val, pipe), 1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415 pipe_name(pipe)); 1417 pipe_name(pipe));
1416 1418
@@ -1872,7 +1874,7 @@ static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1872 enum pipe pipe, int reg) 1874 enum pipe pipe, int reg)
1873{ 1875{
1874 u32 val = I915_READ(reg); 1876 u32 val = I915_READ(reg);
1875 if (hdmi_pipe_enabled(dev_priv, val, pipe)) { 1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1876 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", 1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1877 reg, pipe); 1879 reg, pipe);
1878 I915_WRITE(reg, val & ~PORT_ENABLE); 1880 I915_WRITE(reg, val & ~PORT_ENABLE);
@@ -1894,12 +1896,12 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1894 1896
1895 reg = PCH_ADPA; 1897 reg = PCH_ADPA;
1896 val = I915_READ(reg); 1898 val = I915_READ(reg);
1897 if (adpa_pipe_enabled(dev_priv, val, pipe)) 1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1898 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); 1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1899 1901
1900 reg = PCH_LVDS; 1902 reg = PCH_LVDS;
1901 val = I915_READ(reg); 1903 val = I915_READ(reg);
1902 if (lvds_pipe_enabled(dev_priv, val, pipe)) { 1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1903 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); 1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1904 I915_WRITE(reg, val & ~LVDS_PORT_EN); 1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1905 POSTING_READ(reg); 1907 POSTING_READ(reg);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a6c426afaa7a..ace757af9133 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2533,14 +2533,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
2533 break; 2533 break;
2534 } 2534 }
2535 2535
2536 intel_dp_i2c_init(intel_dp, intel_connector, name);
2537
2538 /* Cache some DPCD data in the eDP case */ 2536 /* Cache some DPCD data in the eDP case */
2539 if (is_edp(intel_dp)) { 2537 if (is_edp(intel_dp)) {
2540 bool ret;
2541 struct edp_power_seq cur, vbt; 2538 struct edp_power_seq cur, vbt;
2542 u32 pp_on, pp_off, pp_div; 2539 u32 pp_on, pp_off, pp_div;
2543 struct edid *edid;
2544 2540
2545 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2541 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2546 pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2542 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
@@ -2591,6 +2587,13 @@ intel_dp_init(struct drm_device *dev, int output_reg)
2591 2587
2592 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 2588 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2593 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 2589 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2590 }
2591
2592 intel_dp_i2c_init(intel_dp, intel_connector, name);
2593
2594 if (is_edp(intel_dp)) {
2595 bool ret;
2596 struct edid *edid;
2594 2597
2595 ironlake_edp_panel_vdd_on(intel_dp); 2598 ironlake_edp_panel_vdd_on(intel_dp);
2596 ret = intel_dp_get_dpcd(intel_dp); 2599 ret = intel_dp_get_dpcd(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index e05c0d3e3440..e9a6f6aaed85 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -780,6 +780,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
780 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"), 780 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
781 }, 781 },
782 }, 782 },
783 {
784 .callback = intel_no_lvds_dmi_callback,
785 .ident = "Gigabyte GA-D525TUD",
786 .matches = {
787 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
788 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
789 },
790 },
783 791
784 { } /* terminating entry */ 792 { } /* terminating entry */
785}; 793};
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 3df4f5fa892a..e019b2369861 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -162,19 +162,12 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
162 return val; 162 return val;
163} 163}
164 164
165u32 intel_panel_get_max_backlight(struct drm_device *dev) 165static u32 _intel_panel_get_max_backlight(struct drm_device *dev)
166{ 166{
167 struct drm_i915_private *dev_priv = dev->dev_private; 167 struct drm_i915_private *dev_priv = dev->dev_private;
168 u32 max; 168 u32 max;
169 169
170 max = i915_read_blc_pwm_ctl(dev_priv); 170 max = i915_read_blc_pwm_ctl(dev_priv);
171 if (max == 0) {
172 /* XXX add code here to query mode clock or hardware clock
173 * and program max PWM appropriately.
174 */
175 pr_warn_once("fixme: max PWM is zero\n");
176 return 1;
177 }
178 171
179 if (HAS_PCH_SPLIT(dev)) { 172 if (HAS_PCH_SPLIT(dev)) {
180 max >>= 16; 173 max >>= 16;
@@ -188,6 +181,22 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
188 max *= 0xff; 181 max *= 0xff;
189 } 182 }
190 183
184 return max;
185}
186
187u32 intel_panel_get_max_backlight(struct drm_device *dev)
188{
189 u32 max;
190
191 max = _intel_panel_get_max_backlight(dev);
192 if (max == 0) {
193 /* XXX add code here to query mode clock or hardware clock
194 * and program max PWM appropriately.
195 */
196 pr_warn_once("fixme: max PWM is zero\n");
197 return 1;
198 }
199
191 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); 200 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
192 return max; 201 return max;
193} 202}
@@ -424,7 +433,11 @@ int intel_panel_setup_backlight(struct drm_device *dev)
424 433
425 memset(&props, 0, sizeof(props)); 434 memset(&props, 0, sizeof(props));
426 props.type = BACKLIGHT_RAW; 435 props.type = BACKLIGHT_RAW;
427 props.max_brightness = intel_panel_get_max_backlight(dev); 436 props.max_brightness = _intel_panel_get_max_backlight(dev);
437 if (props.max_brightness == 0) {
438 DRM_ERROR("Failed to get maximum backlight value\n");
439 return -ENODEV;
440 }
428 dev_priv->backlight = 441 dev_priv->backlight =
429 backlight_device_register("intel_backlight", 442 backlight_device_register("intel_backlight",
430 &connector->kdev, dev, 443 &connector->kdev, dev,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1881c8c83f0e..ba8a27b1757a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3672,6 +3672,9 @@ static void gen3_init_clock_gating(struct drm_device *dev)
3672 3672
3673 if (IS_PINEVIEW(dev)) 3673 if (IS_PINEVIEW(dev))
3674 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 3674 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
3675
3676 /* IIR "flip pending" means done if this bit is set */
3677 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
3675} 3678}
3676 3679
3677static void i85x_init_clock_gating(struct drm_device *dev) 3680static void i85x_init_clock_gating(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d81bb0bf2885..123afd357611 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2573,7 +2573,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2573 hotplug_mask = intel_sdvo->is_sdvob ? 2573 hotplug_mask = intel_sdvo->is_sdvob ?
2574 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915; 2574 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2575 } 2575 }
2576 dev_priv->hotplug_supported_mask |= hotplug_mask;
2577 2576
2578 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); 2577 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
2579 2578
@@ -2581,14 +2580,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2581 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 2580 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2582 goto err; 2581 goto err;
2583 2582
2584 /* Set up hotplug command - note paranoia about contents of reply.
2585 * We assume that the hardware is in a sane state, and only touch
2586 * the bits we think we understand.
2587 */
2588 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2589 &intel_sdvo->hotplug_active, 2);
2590 intel_sdvo->hotplug_active[0] &= ~0x3;
2591
2592 if (intel_sdvo_output_setup(intel_sdvo, 2583 if (intel_sdvo_output_setup(intel_sdvo,
2593 intel_sdvo->caps.output_flags) != true) { 2584 intel_sdvo->caps.output_flags) != true) {
2594 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 2585 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
@@ -2596,6 +2587,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2596 goto err; 2587 goto err;
2597 } 2588 }
2598 2589
2590 /* Only enable the hotplug irq if we need it, to work around noisy
2591 * hotplug lines.
2592 */
2593 if (intel_sdvo->hotplug_active[0])
2594 dev_priv->hotplug_supported_mask |= hotplug_mask;
2595
2599 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 2596 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2600 2597
2601 /* Set the input timing to the screen. Assume always input 0. */ 2598 /* Set the input timing to the screen. Assume always input 0. */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index cc8df4de2d92..7644f31a3778 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -60,11 +60,11 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
60 60
61 switch (fb->pixel_format) { 61 switch (fb->pixel_format) {
62 case DRM_FORMAT_XBGR8888: 62 case DRM_FORMAT_XBGR8888:
63 sprctl |= SPRITE_FORMAT_RGBX888; 63 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
64 pixel_size = 4; 64 pixel_size = 4;
65 break; 65 break;
66 case DRM_FORMAT_XRGB8888: 66 case DRM_FORMAT_XRGB8888:
67 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 67 sprctl |= SPRITE_FORMAT_RGBX888;
68 pixel_size = 4; 68 pixel_size = 4;
69 break; 69 break;
70 case DRM_FORMAT_YUYV: 70 case DRM_FORMAT_YUYV:
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c
index ea1024d79974..e5f145d2cb3b 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.c
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
@@ -84,6 +84,9 @@ static const struct file_operations mgag200_driver_fops = {
84 .mmap = mgag200_mmap, 84 .mmap = mgag200_mmap,
85 .poll = drm_poll, 85 .poll = drm_poll,
86 .fasync = drm_fasync, 86 .fasync = drm_fasync,
87#ifdef CONFIG_COMPAT
88 .compat_ioctl = drm_compat_ioctl,
89#endif
87 .read = drm_read, 90 .read = drm_read,
88}; 91};
89 92
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 69688ef5cf46..7e16dc5e6467 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -598,7 +598,7 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
598 args->size = args->pitch * args->height; 598 args->size = args->pitch * args->height;
599 args->size = roundup(args->size, PAGE_SIZE); 599 args->size = roundup(args->size, PAGE_SIZE);
600 600
601 ret = nouveau_gem_new(dev, args->size, 0, TTM_PL_FLAG_VRAM, 0, 0, &bo); 601 ret = nouveau_gem_new(dev, args->size, 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, &bo);
602 if (ret) 602 if (ret)
603 return ret; 603 return ret;
604 604
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 1866dbb49979..c61014442aa9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -736,9 +736,11 @@ nouveau_card_init(struct drm_device *dev)
736 } 736 }
737 break; 737 break;
738 case NV_C0: 738 case NV_C0:
739 nvc0_copy_create(dev, 1); 739 if (!(nv_rd32(dev, 0x022500) & 0x00000200))
740 nvc0_copy_create(dev, 1);
740 case NV_D0: 741 case NV_D0:
741 nvc0_copy_create(dev, 0); 742 if (!(nv_rd32(dev, 0x022500) & 0x00000100))
743 nvc0_copy_create(dev, 0);
742 break; 744 break;
743 default: 745 default:
744 break; 746 break;
diff --git a/drivers/gpu/drm/nouveau/nv50_gpio.c b/drivers/gpu/drm/nouveau/nv50_gpio.c
index f429e6a8ca7a..f03490534893 100644
--- a/drivers/gpu/drm/nouveau/nv50_gpio.c
+++ b/drivers/gpu/drm/nouveau/nv50_gpio.c
@@ -115,6 +115,9 @@ nv50_gpio_init(struct drm_device *dev)
115{ 115{
116 struct drm_nouveau_private *dev_priv = dev->dev_private; 116 struct drm_nouveau_private *dev_priv = dev->dev_private;
117 117
118 /* initialise gpios and routing to vbios defaults */
119 nouveau_gpio_reset(dev);
120
118 /* disable, and ack any pending gpio interrupts */ 121 /* disable, and ack any pending gpio interrupts */
119 nv_wr32(dev, 0xe050, 0x00000000); 122 nv_wr32(dev, 0xe050, 0x00000000);
120 nv_wr32(dev, 0xe054, 0xffffffff); 123 nv_wr32(dev, 0xe054, 0xffffffff);
diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c
index dac525b2994e..8a2fc89b7763 100644
--- a/drivers/gpu/drm/nouveau/nvd0_display.c
+++ b/drivers/gpu/drm/nouveau/nvd0_display.c
@@ -1510,10 +1510,10 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1510 case OUTPUT_DP: 1510 case OUTPUT_DP:
1511 if (nv_connector->base.display_info.bpc == 6) { 1511 if (nv_connector->base.display_info.bpc == 6) {
1512 nv_encoder->dp.datarate = mode->clock * 18 / 8; 1512 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1513 syncs |= 0x00000140; 1513 syncs |= 0x00000002 << 6;
1514 } else { 1514 } else {
1515 nv_encoder->dp.datarate = mode->clock * 24 / 8; 1515 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1516 syncs |= 0x00000180; 1516 syncs |= 0x00000005 << 6;
1517 } 1517 }
1518 1518
1519 if (nv_encoder->dcb->sorconf.link & 1) 1519 if (nv_encoder->dcb->sorconf.link & 1)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index f4d4505fe831..e721e3087b99 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -258,7 +258,6 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
258 radeon_crtc->enabled = true; 258 radeon_crtc->enabled = true;
259 /* adjust pm to dpms changes BEFORE enabling crtcs */ 259 /* adjust pm to dpms changes BEFORE enabling crtcs */
260 radeon_pm_compute_clocks(rdev); 260 radeon_pm_compute_clocks(rdev);
261 /* disable crtc pair power gating before programming */
262 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) 261 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
263 atombios_powergate_crtc(crtc, ATOM_DISABLE); 262 atombios_powergate_crtc(crtc, ATOM_DISABLE);
264 atombios_enable_crtc(crtc, ATOM_ENABLE); 263 atombios_enable_crtc(crtc, ATOM_ENABLE);
@@ -278,25 +277,8 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
278 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 277 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
279 atombios_enable_crtc(crtc, ATOM_DISABLE); 278 atombios_enable_crtc(crtc, ATOM_DISABLE);
280 radeon_crtc->enabled = false; 279 radeon_crtc->enabled = false;
281 /* power gating is per-pair */ 280 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
282 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) { 281 atombios_powergate_crtc(crtc, ATOM_ENABLE);
283 struct drm_crtc *other_crtc;
284 struct radeon_crtc *other_radeon_crtc;
285 list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
286 other_radeon_crtc = to_radeon_crtc(other_crtc);
287 if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||
288 ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||
289 ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||
290 ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||
291 ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||
292 ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {
293 /* if both crtcs in the pair are off, enable power gating */
294 if (other_radeon_crtc->enabled == false)
295 atombios_powergate_crtc(crtc, ATOM_ENABLE);
296 break;
297 }
298 }
299 }
300 /* adjust pm to dpms changes AFTER disabling crtcs */ 282 /* adjust pm to dpms changes AFTER disabling crtcs */
301 radeon_pm_compute_clocks(rdev); 283 radeon_pm_compute_clocks(rdev);
302 break; 284 break;
@@ -1497,14 +1479,98 @@ static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1497 } 1479 }
1498} 1480}
1499 1481
1482/**
1483 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1484 *
1485 * @crtc: drm crtc
1486 *
1487 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1488 */
1489static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1490{
1491 struct drm_device *dev = crtc->dev;
1492 struct drm_crtc *test_crtc;
1493 struct radeon_crtc *radeon_test_crtc;
1494 u32 pll_in_use = 0;
1495
1496 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1497 if (crtc == test_crtc)
1498 continue;
1499
1500 radeon_test_crtc = to_radeon_crtc(test_crtc);
1501 if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
1502 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1503 }
1504 return pll_in_use;
1505}
1506
1507/**
1508 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1509 *
1510 * @crtc: drm crtc
1511 *
1512 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1513 * also in DP mode. For DP, a single PPLL can be used for all DP
1514 * crtcs/encoders.
1515 */
1516static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1517{
1518 struct drm_device *dev = crtc->dev;
1519 struct drm_encoder *test_encoder;
1520 struct radeon_crtc *radeon_test_crtc;
1521
1522 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1523 if (test_encoder->crtc && (test_encoder->crtc != crtc)) {
1524 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1525 /* for DP use the same PLL for all */
1526 radeon_test_crtc = to_radeon_crtc(test_encoder->crtc);
1527 if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
1528 return radeon_test_crtc->pll_id;
1529 }
1530 }
1531 }
1532 return ATOM_PPLL_INVALID;
1533}
1534
1535/**
1536 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1537 *
1538 * @crtc: drm crtc
1539 *
1540 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1541 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1542 * monitors a dedicated PPLL must be used. If a particular board has
1543 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1544 * as there is no need to program the PLL itself. If we are not able to
1545 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1546 * avoid messing up an existing monitor.
1547 *
1548 * Asic specific PLL information
1549 *
1550 * DCE 6.1
1551 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1552 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1553 *
1554 * DCE 6.0
1555 * - PPLL0 is available to all UNIPHY (DP only)
1556 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1557 *
1558 * DCE 5.0
1559 * - DCPLL is available to all UNIPHY (DP only)
1560 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1561 *
1562 * DCE 3.0/4.0/4.1
1563 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1564 *
1565 */
1500static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1566static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1501{ 1567{
1502 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1568 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1503 struct drm_device *dev = crtc->dev; 1569 struct drm_device *dev = crtc->dev;
1504 struct radeon_device *rdev = dev->dev_private; 1570 struct radeon_device *rdev = dev->dev_private;
1505 struct drm_encoder *test_encoder; 1571 struct drm_encoder *test_encoder;
1506 struct drm_crtc *test_crtc; 1572 u32 pll_in_use;
1507 uint32_t pll_in_use = 0; 1573 int pll;
1508 1574
1509 if (ASIC_IS_DCE61(rdev)) { 1575 if (ASIC_IS_DCE61(rdev)) {
1510 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1576 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
@@ -1516,32 +1582,40 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1516 1582
1517 if ((test_radeon_encoder->encoder_id == 1583 if ((test_radeon_encoder->encoder_id ==
1518 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1584 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1519 (dig->linkb == false)) /* UNIPHY A uses PPLL2 */ 1585 (dig->linkb == false))
1586 /* UNIPHY A uses PPLL2 */
1520 return ATOM_PPLL2; 1587 return ATOM_PPLL2;
1588 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1589 /* UNIPHY B/C/D/E/F */
1590 if (rdev->clock.dp_extclk)
1591 /* skip PPLL programming if using ext clock */
1592 return ATOM_PPLL_INVALID;
1593 else {
1594 /* use the same PPLL for all DP monitors */
1595 pll = radeon_get_shared_dp_ppll(crtc);
1596 if (pll != ATOM_PPLL_INVALID)
1597 return pll;
1598 }
1599 }
1600 break;
1521 } 1601 }
1522 } 1602 }
1523 /* UNIPHY B/C/D/E/F */ 1603 /* UNIPHY B/C/D/E/F */
1524 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1604 pll_in_use = radeon_get_pll_use_mask(crtc);
1525 struct radeon_crtc *radeon_test_crtc; 1605 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1526
1527 if (crtc == test_crtc)
1528 continue;
1529
1530 radeon_test_crtc = to_radeon_crtc(test_crtc);
1531 if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
1532 (radeon_test_crtc->pll_id == ATOM_PPLL1))
1533 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1534 }
1535 if (!(pll_in_use & 4))
1536 return ATOM_PPLL0; 1606 return ATOM_PPLL0;
1537 return ATOM_PPLL1; 1607 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1608 return ATOM_PPLL1;
1609 DRM_ERROR("unable to allocate a PPLL\n");
1610 return ATOM_PPLL_INVALID;
1538 } else if (ASIC_IS_DCE4(rdev)) { 1611 } else if (ASIC_IS_DCE4(rdev)) {
1539 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1612 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1540 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1613 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1541 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1614 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1542 * depending on the asic: 1615 * depending on the asic:
1543 * DCE4: PPLL or ext clock 1616 * DCE4: PPLL or ext clock
1544 * DCE5: DCPLL or ext clock 1617 * DCE5: PPLL, DCPLL, or ext clock
1618 * DCE6: PPLL, PPLL0, or ext clock
1545 * 1619 *
1546 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1620 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1547 * PPLL/DCPLL programming and only program the DP DTO for the 1621 * PPLL/DCPLL programming and only program the DP DTO for the
@@ -1549,31 +1623,34 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1549 */ 1623 */
1550 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1624 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1551 if (rdev->clock.dp_extclk) 1625 if (rdev->clock.dp_extclk)
1626 /* skip PPLL programming if using ext clock */
1552 return ATOM_PPLL_INVALID; 1627 return ATOM_PPLL_INVALID;
1553 else if (ASIC_IS_DCE6(rdev)) 1628 else if (ASIC_IS_DCE6(rdev))
1629 /* use PPLL0 for all DP */
1554 return ATOM_PPLL0; 1630 return ATOM_PPLL0;
1555 else if (ASIC_IS_DCE5(rdev)) 1631 else if (ASIC_IS_DCE5(rdev))
1632 /* use DCPLL for all DP */
1556 return ATOM_DCPLL; 1633 return ATOM_DCPLL;
1634 else {
1635 /* use the same PPLL for all DP monitors */
1636 pll = radeon_get_shared_dp_ppll(crtc);
1637 if (pll != ATOM_PPLL_INVALID)
1638 return pll;
1639 }
1557 } 1640 }
1641 break;
1558 } 1642 }
1559 } 1643 }
1560 1644 /* all other cases */
1561 /* otherwise, pick one of the plls */ 1645 pll_in_use = radeon_get_pll_use_mask(crtc);
1562 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1646 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1563 struct radeon_crtc *radeon_test_crtc; 1647 return ATOM_PPLL2;
1564 1648 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1565 if (crtc == test_crtc)
1566 continue;
1567
1568 radeon_test_crtc = to_radeon_crtc(test_crtc);
1569 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1570 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1571 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1572 }
1573 if (!(pll_in_use & 1))
1574 return ATOM_PPLL1; 1649 return ATOM_PPLL1;
1575 return ATOM_PPLL2; 1650 DRM_ERROR("unable to allocate a PPLL\n");
1651 return ATOM_PPLL_INVALID;
1576 } else 1652 } else
1653 /* use PPLL1 or PPLL2 */
1577 return radeon_crtc->crtc_id; 1654 return radeon_crtc->crtc_id;
1578 1655
1579} 1656}
@@ -1682,9 +1759,22 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1682 struct drm_device *dev = crtc->dev; 1759 struct drm_device *dev = crtc->dev;
1683 struct radeon_device *rdev = dev->dev_private; 1760 struct radeon_device *rdev = dev->dev_private;
1684 struct radeon_atom_ss ss; 1761 struct radeon_atom_ss ss;
1762 int i;
1685 1763
1686 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1764 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1687 1765
1766 for (i = 0; i < rdev->num_crtc; i++) {
1767 if (rdev->mode_info.crtcs[i] &&
1768 rdev->mode_info.crtcs[i]->enabled &&
1769 i != radeon_crtc->crtc_id &&
1770 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1771 /* one other crtc is using this pll don't turn
1772 * off the pll
1773 */
1774 goto done;
1775 }
1776 }
1777
1688 switch (radeon_crtc->pll_id) { 1778 switch (radeon_crtc->pll_id) {
1689 case ATOM_PPLL1: 1779 case ATOM_PPLL1:
1690 case ATOM_PPLL2: 1780 case ATOM_PPLL2:
@@ -1701,7 +1791,8 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1701 default: 1791 default:
1702 break; 1792 break;
1703 } 1793 }
1704 radeon_crtc->pll_id = -1; 1794done:
1795 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1705} 1796}
1706 1797
1707static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1798static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
@@ -1750,6 +1841,6 @@ void radeon_atombios_init_crtc(struct drm_device *dev,
1750 else 1841 else
1751 radeon_crtc->crtc_offset = 0; 1842 radeon_crtc->crtc_offset = 0;
1752 } 1843 }
1753 radeon_crtc->pll_id = -1; 1844 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1754 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1845 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1755} 1846}
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 7712cf5ab33b..3623b98ed3fe 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -577,30 +577,25 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
577 struct radeon_device *rdev = dev->dev_private; 577 struct radeon_device *rdev = dev->dev_private;
578 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 578 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
579 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 579 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
580 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
581 u8 tmp;
580 582
581 if (!ASIC_IS_DCE4(rdev)) 583 if (!ASIC_IS_DCE4(rdev))
582 return panel_mode; 584 return panel_mode;
583 585
584 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 586 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
585 ENCODER_OBJECT_ID_NUTMEG) 587 /* DP bridge chips */
586 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 588 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
587 else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 589 if (tmp & 1)
588 ENCODER_OBJECT_ID_TRAVIS) { 590 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
589 u8 id[6]; 591 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
590 int i; 592 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
591 for (i = 0; i < 6; i++)
592 id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);
593 if (id[0] == 0x73 &&
594 id[1] == 0x69 &&
595 id[2] == 0x76 &&
596 id[3] == 0x61 &&
597 id[4] == 0x72 &&
598 id[5] == 0x54)
599 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 593 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
600 else 594 else
601 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 595 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
602 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 596 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
603 u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 597 /* eDP */
598 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
604 if (tmp & 1) 599 if (tmp & 1)
605 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 600 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
606 } 601 }
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index f9bc27fe269a..6e8803a1170c 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1379,6 +1379,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1379 struct drm_device *dev = encoder->dev; 1379 struct drm_device *dev = encoder->dev;
1380 struct radeon_device *rdev = dev->dev_private; 1380 struct radeon_device *rdev = dev->dev_private;
1381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1382 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1383 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1382 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1384 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1383 struct radeon_connector *radeon_connector = NULL; 1385 struct radeon_connector *radeon_connector = NULL;
1384 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1386 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
@@ -1390,19 +1392,37 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1390 1392
1391 switch (mode) { 1393 switch (mode) {
1392 case DRM_MODE_DPMS_ON: 1394 case DRM_MODE_DPMS_ON:
1393 /* some early dce3.2 boards have a bug in their transmitter control table */ 1395 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1394 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) || 1396 if (!connector)
1395 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1397 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1396 if (ASIC_IS_DCE6(rdev)) { 1398 else
1397 /* It seems we need to call ATOM_ENCODER_CMD_SETUP again 1399 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1398 * before reenabling encoder on DPMS ON, otherwise we never 1400
1399 * get picture 1401 /* setup and enable the encoder */
1400 */ 1402 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1401 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1403 atombios_dig_encoder_setup(encoder,
1404 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1405 dig->panel_mode);
1406 if (ext_encoder) {
1407 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1408 atombios_external_encoder_setup(encoder, ext_encoder,
1409 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1402 } 1410 }
1403 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1411 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1404 } else { 1412 } else if (ASIC_IS_DCE4(rdev)) {
1413 /* setup and enable the encoder */
1414 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1415 /* enable the transmitter */
1416 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1405 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1417 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1418 } else {
1419 /* setup and enable the encoder and transmitter */
1420 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1421 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1422 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1423 /* some early dce3.2 boards have a bug in their transmitter control table */
1424 if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1425 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1406 } 1426 }
1407 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1427 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1428 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
@@ -1420,10 +1440,19 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1420 case DRM_MODE_DPMS_STANDBY: 1440 case DRM_MODE_DPMS_STANDBY:
1421 case DRM_MODE_DPMS_SUSPEND: 1441 case DRM_MODE_DPMS_SUSPEND:
1422 case DRM_MODE_DPMS_OFF: 1442 case DRM_MODE_DPMS_OFF:
1423 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) 1443 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1444 /* disable the transmitter */
1424 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1445 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1425 else 1446 } else if (ASIC_IS_DCE4(rdev)) {
1447 /* disable the transmitter */
1448 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1449 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1450 } else {
1451 /* disable the encoder and transmitter */
1426 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1452 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1453 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1454 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1455 }
1427 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1456 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1428 if (ASIC_IS_DCE4(rdev)) 1457 if (ASIC_IS_DCE4(rdev))
1429 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1458 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
@@ -1740,13 +1769,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1740 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1769 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1741 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1770 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1742 struct drm_encoder *test_encoder; 1771 struct drm_encoder *test_encoder;
1743 struct radeon_encoder_atom_dig *dig; 1772 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1744 uint32_t dig_enc_in_use = 0; 1773 uint32_t dig_enc_in_use = 0;
1745 1774
1746 /* DCE4/5 */ 1775 if (ASIC_IS_DCE6(rdev)) {
1747 if (ASIC_IS_DCE4(rdev)) { 1776 /* DCE6 */
1748 dig = radeon_encoder->enc_priv; 1777 switch (radeon_encoder->encoder_id) {
1749 if (ASIC_IS_DCE41(rdev)) { 1778 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1779 if (dig->linkb)
1780 return 1;
1781 else
1782 return 0;
1783 break;
1784 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1785 if (dig->linkb)
1786 return 3;
1787 else
1788 return 2;
1789 break;
1790 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1791 if (dig->linkb)
1792 return 5;
1793 else
1794 return 4;
1795 break;
1796 }
1797 } else if (ASIC_IS_DCE4(rdev)) {
1798 /* DCE4/5 */
1799 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
1750 /* ontario follows DCE4 */ 1800 /* ontario follows DCE4 */
1751 if (rdev->family == CHIP_PALM) { 1801 if (rdev->family == CHIP_PALM) {
1752 if (dig->linkb) 1802 if (dig->linkb)
@@ -1848,10 +1898,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1848 struct drm_device *dev = encoder->dev; 1898 struct drm_device *dev = encoder->dev;
1849 struct radeon_device *rdev = dev->dev_private; 1899 struct radeon_device *rdev = dev->dev_private;
1850 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1900 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1851 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1852 1901
1853 radeon_encoder->pixel_clock = adjusted_mode->clock; 1902 radeon_encoder->pixel_clock = adjusted_mode->clock;
1854 1903
1904 /* need to call this here rather than in prepare() since we need some crtc info */
1905 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1906
1855 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 1907 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1856 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1908 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1857 atombios_yuv_setup(encoder, true); 1909 atombios_yuv_setup(encoder, true);
@@ -1870,38 +1922,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1870 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1922 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1871 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1923 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1872 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1924 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1873 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1925 /* handled in dpms */
1874 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1875 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1876
1877 if (!connector)
1878 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1879 else
1880 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1881
1882 /* setup and enable the encoder */
1883 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1884 atombios_dig_encoder_setup(encoder,
1885 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1886 dig->panel_mode);
1887 } else if (ASIC_IS_DCE4(rdev)) {
1888 /* disable the transmitter */
1889 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1890 /* setup and enable the encoder */
1891 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1892
1893 /* enable the transmitter */
1894 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1895 } else {
1896 /* disable the encoder and transmitter */
1897 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1898 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1899
1900 /* setup and enable the encoder and transmitter */
1901 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1902 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1903 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1904 }
1905 break; 1926 break;
1906 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1927 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1907 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1928 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -1922,14 +1943,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1922 break; 1943 break;
1923 } 1944 }
1924 1945
1925 if (ext_encoder) {
1926 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1927 atombios_external_encoder_setup(encoder, ext_encoder,
1928 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1929 else
1930 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1931 }
1932
1933 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1946 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1934 1947
1935 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1948 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
@@ -2116,7 +2129,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2116 } 2129 }
2117 2130
2118 radeon_atom_output_lock(encoder, true); 2131 radeon_atom_output_lock(encoder, true);
2119 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2120 2132
2121 if (connector) { 2133 if (connector) {
2122 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2134 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -2137,6 +2149,7 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2137 2149
2138static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2150static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2139{ 2151{
2152 /* need to call this here as we need the crtc set up */
2140 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2153 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2141 radeon_atom_output_lock(encoder, false); 2154 radeon_atom_output_lock(encoder, false);
2142} 2155}
@@ -2177,14 +2190,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2177 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2190 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2179 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2192 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2180 if (ASIC_IS_DCE4(rdev)) 2193 /* handled in dpms */
2181 /* disable the transmitter */
2182 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2183 else {
2184 /* disable the encoder and transmitter */
2185 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2186 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2187 }
2188 break; 2194 break;
2189 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2195 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2190 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2196 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index ab74e6b149e7..f37676d7f217 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -63,6 +63,7 @@ struct r600_cs_track {
63 u32 cb_color_size_idx[8]; /* unused */ 63 u32 cb_color_size_idx[8]; /* unused */
64 u32 cb_target_mask; 64 u32 cb_target_mask;
65 u32 cb_shader_mask; /* unused */ 65 u32 cb_shader_mask; /* unused */
66 bool is_resolve;
66 u32 cb_color_size[8]; 67 u32 cb_color_size[8];
67 u32 vgt_strmout_en; 68 u32 vgt_strmout_en;
68 u32 vgt_strmout_buffer_en; 69 u32 vgt_strmout_buffer_en;
@@ -315,7 +316,15 @@ static void r600_cs_track_init(struct r600_cs_track *track)
315 track->cb_color_bo[i] = NULL; 316 track->cb_color_bo[i] = NULL;
316 track->cb_color_bo_offset[i] = 0xFFFFFFFF; 317 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
317 track->cb_color_bo_mc[i] = 0xFFFFFFFF; 318 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
318 } 319 track->cb_color_frag_bo[i] = NULL;
320 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
321 track->cb_color_tile_bo[i] = NULL;
322 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
323 track->cb_color_mask[i] = 0xFFFFFFFF;
324 }
325 track->is_resolve = false;
326 track->nsamples = 16;
327 track->log_nsamples = 4;
319 track->cb_target_mask = 0xFFFFFFFF; 328 track->cb_target_mask = 0xFFFFFFFF;
320 track->cb_shader_mask = 0xFFFFFFFF; 329 track->cb_shader_mask = 0xFFFFFFFF;
321 track->cb_dirty = true; 330 track->cb_dirty = true;
@@ -352,6 +361,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
352 volatile u32 *ib = p->ib.ptr; 361 volatile u32 *ib = p->ib.ptr;
353 unsigned array_mode; 362 unsigned array_mode;
354 u32 format; 363 u32 format;
364 /* When resolve is used, the second colorbuffer has always 1 sample. */
365 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
355 366
356 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; 367 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
357 format = G_0280A0_FORMAT(track->cb_color_info[i]); 368 format = G_0280A0_FORMAT(track->cb_color_info[i]);
@@ -375,7 +386,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
375 array_check.group_size = track->group_size; 386 array_check.group_size = track->group_size;
376 array_check.nbanks = track->nbanks; 387 array_check.nbanks = track->nbanks;
377 array_check.npipes = track->npipes; 388 array_check.npipes = track->npipes;
378 array_check.nsamples = track->nsamples; 389 array_check.nsamples = nsamples;
379 array_check.blocksize = r600_fmt_get_blocksize(format); 390 array_check.blocksize = r600_fmt_get_blocksize(format);
380 if (r600_get_array_mode_alignment(&array_check, 391 if (r600_get_array_mode_alignment(&array_check,
381 &pitch_align, &height_align, &depth_align, &base_align)) { 392 &pitch_align, &height_align, &depth_align, &base_align)) {
@@ -421,7 +432,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
421 432
422 /* check offset */ 433 /* check offset */
423 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * 434 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
424 r600_fmt_get_blocksize(format) * track->nsamples; 435 r600_fmt_get_blocksize(format) * nsamples;
425 switch (array_mode) { 436 switch (array_mode) {
426 default: 437 default:
427 case V_0280A0_ARRAY_LINEAR_GENERAL: 438 case V_0280A0_ARRAY_LINEAR_GENERAL:
@@ -792,6 +803,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
792 */ 803 */
793 if (track->cb_dirty) { 804 if (track->cb_dirty) {
794 tmp = track->cb_target_mask; 805 tmp = track->cb_target_mask;
806
807 /* We must check both colorbuffers for RESOLVE. */
808 if (track->is_resolve) {
809 tmp |= 0xff;
810 }
811
795 for (i = 0; i < 8; i++) { 812 for (i = 0; i < 8; i++) {
796 if ((tmp >> (i * 4)) & 0xF) { 813 if ((tmp >> (i * 4)) & 0xF) {
797 /* at least one component is enabled */ 814 /* at least one component is enabled */
@@ -1281,6 +1298,11 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1281 track->nsamples = 1 << tmp; 1298 track->nsamples = 1 << tmp;
1282 track->cb_dirty = true; 1299 track->cb_dirty = true;
1283 break; 1300 break;
1301 case R_028808_CB_COLOR_CONTROL:
1302 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1303 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1304 track->cb_dirty = true;
1305 break;
1284 case R_0280A0_CB_COLOR0_INFO: 1306 case R_0280A0_CB_COLOR0_INFO:
1285 case R_0280A4_CB_COLOR1_INFO: 1307 case R_0280A4_CB_COLOR1_INFO:
1286 case R_0280A8_CB_COLOR2_INFO: 1308 case R_0280A8_CB_COLOR2_INFO:
@@ -1416,7 +1438,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1416 case R_028118_CB_COLOR6_MASK: 1438 case R_028118_CB_COLOR6_MASK:
1417 case R_02811C_CB_COLOR7_MASK: 1439 case R_02811C_CB_COLOR7_MASK:
1418 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; 1440 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1419 track->cb_color_mask[tmp] = ib[idx]; 1441 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1420 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { 1442 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1421 track->cb_dirty = true; 1443 track->cb_dirty = true;
1422 } 1444 }
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index bdb69a63062f..fa6f37099ba9 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -66,6 +66,14 @@
66#define CC_RB_BACKEND_DISABLE 0x98F4 66#define CC_RB_BACKEND_DISABLE 0x98F4
67#define BACKEND_DISABLE(x) ((x) << 16) 67#define BACKEND_DISABLE(x) ((x) << 16)
68 68
69#define R_028808_CB_COLOR_CONTROL 0x28808
70#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
71#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
72#define C_028808_SPECIAL_OP 0xFFFFFF8F
73#define V_028808_SPECIAL_NORMAL 0x00
74#define V_028808_SPECIAL_DISABLE 0x01
75#define V_028808_SPECIAL_RESOLVE_BOX 0x07
76
69#define CB_COLOR0_BASE 0x28040 77#define CB_COLOR0_BASE 0x28040
70#define CB_COLOR1_BASE 0x28044 78#define CB_COLOR1_BASE 0x28044
71#define CB_COLOR2_BASE 0x28048 79#define CB_COLOR2_BASE 0x28048
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index d2e243867ac6..7a3daebd732d 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1051,7 +1051,7 @@ int radeon_device_init(struct radeon_device *rdev,
1051 if (rdev->flags & RADEON_IS_AGP) 1051 if (rdev->flags & RADEON_IS_AGP)
1052 rdev->need_dma32 = true; 1052 rdev->need_dma32 = true;
1053 if ((rdev->flags & RADEON_IS_PCI) && 1053 if ((rdev->flags & RADEON_IS_PCI) &&
1054 (rdev->family < CHIP_RS400)) 1054 (rdev->family <= CHIP_RS740))
1055 rdev->need_dma32 = true; 1055 rdev->need_dma32 = true;
1056 1056
1057 dma_bits = rdev->need_dma32 ? 32 : 40; 1057 dma_bits = rdev->need_dma32 ? 32 : 40;
@@ -1346,12 +1346,15 @@ retry:
1346 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1346 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1347 radeon_ring_restore(rdev, &rdev->ring[i], 1347 radeon_ring_restore(rdev, &rdev->ring[i],
1348 ring_sizes[i], ring_data[i]); 1348 ring_sizes[i], ring_data[i]);
1349 ring_sizes[i] = 0;
1350 ring_data[i] = NULL;
1349 } 1351 }
1350 1352
1351 r = radeon_ib_ring_tests(rdev); 1353 r = radeon_ib_ring_tests(rdev);
1352 if (r) { 1354 if (r) {
1353 dev_err(rdev->dev, "ib ring test failed (%d).\n", r); 1355 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1354 if (saved) { 1356 if (saved) {
1357 saved = false;
1355 radeon_suspend(rdev); 1358 radeon_suspend(rdev);
1356 goto retry; 1359 goto retry;
1357 } 1360 }
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 27d22d709c90..8c593ea82c41 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -63,9 +63,10 @@
63 * 2.19.0 - r600-eg: MSAA textures 63 * 2.19.0 - r600-eg: MSAA textures
64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
65 * 2.21.0 - r600-r700: FMASK and CMASK 65 * 2.21.0 - r600-r700: FMASK and CMASK
66 * 2.22.0 - r600 only: RESOLVE_BOX allowed
66 */ 67 */
67#define KMS_DRIVER_MAJOR 2 68#define KMS_DRIVER_MAJOR 2
68#define KMS_DRIVER_MINOR 21 69#define KMS_DRIVER_MINOR 22
69#define KMS_DRIVER_PATCHLEVEL 0 70#define KMS_DRIVER_PATCHLEVEL 0
70int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 71int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
71int radeon_driver_unload_kms(struct drm_device *dev); 72int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 7b737b9339ad..2a59375dbe52 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -131,7 +131,7 @@ int radeon_fence_emit(struct radeon_device *rdev,
131 */ 131 */
132void radeon_fence_process(struct radeon_device *rdev, int ring) 132void radeon_fence_process(struct radeon_device *rdev, int ring)
133{ 133{
134 uint64_t seq, last_seq; 134 uint64_t seq, last_seq, last_emitted;
135 unsigned count_loop = 0; 135 unsigned count_loop = 0;
136 bool wake = false; 136 bool wake = false;
137 137
@@ -158,13 +158,15 @@ void radeon_fence_process(struct radeon_device *rdev, int ring)
158 */ 158 */
159 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq); 159 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
160 do { 160 do {
161 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
161 seq = radeon_fence_read(rdev, ring); 162 seq = radeon_fence_read(rdev, ring);
162 seq |= last_seq & 0xffffffff00000000LL; 163 seq |= last_seq & 0xffffffff00000000LL;
163 if (seq < last_seq) { 164 if (seq < last_seq) {
164 seq += 0x100000000LL; 165 seq &= 0xffffffff;
166 seq |= last_emitted & 0xffffffff00000000LL;
165 } 167 }
166 168
167 if (seq == last_seq) { 169 if (seq <= last_seq || seq > last_emitted) {
168 break; 170 break;
169 } 171 }
170 /* If we loop over we don't want to return without 172 /* If we loop over we don't want to return without
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index f93e45d869f4..20bfbda7b3f1 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -744,7 +744,6 @@ r600 0x9400
7440x00028C38 CB_CLRCMP_DST 7440x00028C38 CB_CLRCMP_DST
7450x00028C3C CB_CLRCMP_MSK 7450x00028C3C CB_CLRCMP_MSK
7460x00028C34 CB_CLRCMP_SRC 7460x00028C34 CB_CLRCMP_SRC
7470x00028808 CB_COLOR_CONTROL
7480x0002842C CB_FOG_BLUE 7470x0002842C CB_FOG_BLUE
7490x00028428 CB_FOG_GREEN 7480x00028428 CB_FOG_GREEN
7500x00028424 CB_FOG_RED 7490x00028424 CB_FOG_RED
diff --git a/drivers/gpu/drm/savage/savage_drv.c b/drivers/gpu/drm/savage/savage_drv.c
index d31d4cca9a4c..c5a164337bd5 100644
--- a/drivers/gpu/drm/savage/savage_drv.c
+++ b/drivers/gpu/drm/savage/savage_drv.c
@@ -43,6 +43,9 @@ static const struct file_operations savage_driver_fops = {
43 .mmap = drm_mmap, 43 .mmap = drm_mmap,
44 .poll = drm_poll, 44 .poll = drm_poll,
45 .fasync = drm_fasync, 45 .fasync = drm_fasync,
46#ifdef CONFIG_COMPAT
47 .compat_ioctl = drm_compat_ioctl,
48#endif
46 .llseek = noop_llseek, 49 .llseek = noop_llseek,
47}; 50};
48 51
diff --git a/drivers/gpu/drm/sis/sis_drv.c b/drivers/gpu/drm/sis/sis_drv.c
index 7f119870147c..867dc03000e6 100644
--- a/drivers/gpu/drm/sis/sis_drv.c
+++ b/drivers/gpu/drm/sis/sis_drv.c
@@ -74,6 +74,9 @@ static const struct file_operations sis_driver_fops = {
74 .mmap = drm_mmap, 74 .mmap = drm_mmap,
75 .poll = drm_poll, 75 .poll = drm_poll,
76 .fasync = drm_fasync, 76 .fasync = drm_fasync,
77#ifdef CONFIG_COMPAT
78 .compat_ioctl = drm_compat_ioctl,
79#endif
77 .llseek = noop_llseek, 80 .llseek = noop_llseek,
78}; 81};
79 82
diff --git a/drivers/gpu/drm/tdfx/tdfx_drv.c b/drivers/gpu/drm/tdfx/tdfx_drv.c
index 90f6b13acfac..a7f4d6bd1330 100644
--- a/drivers/gpu/drm/tdfx/tdfx_drv.c
+++ b/drivers/gpu/drm/tdfx/tdfx_drv.c
@@ -49,6 +49,9 @@ static const struct file_operations tdfx_driver_fops = {
49 .mmap = drm_mmap, 49 .mmap = drm_mmap,
50 .poll = drm_poll, 50 .poll = drm_poll,
51 .fasync = drm_fasync, 51 .fasync = drm_fasync,
52#ifdef CONFIG_COMPAT
53 .compat_ioctl = drm_compat_ioctl,
54#endif
52 .llseek = noop_llseek, 55 .llseek = noop_llseek,
53}; 56};
54 57
diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c
index 6e52069894b3..9f84128505bb 100644
--- a/drivers/gpu/drm/udl/udl_drv.c
+++ b/drivers/gpu/drm/udl/udl_drv.c
@@ -66,6 +66,9 @@ static const struct file_operations udl_driver_fops = {
66 .unlocked_ioctl = drm_ioctl, 66 .unlocked_ioctl = drm_ioctl,
67 .release = drm_release, 67 .release = drm_release,
68 .fasync = drm_fasync, 68 .fasync = drm_fasync,
69#ifdef CONFIG_COMPAT
70 .compat_ioctl = drm_compat_ioctl,
71#endif
69 .llseek = noop_llseek, 72 .llseek = noop_llseek,
70}; 73};
71 74
diff --git a/drivers/gpu/drm/via/via_drv.c b/drivers/gpu/drm/via/via_drv.c
index e927b4c052f5..af1b914b17e3 100644
--- a/drivers/gpu/drm/via/via_drv.c
+++ b/drivers/gpu/drm/via/via_drv.c
@@ -65,6 +65,9 @@ static const struct file_operations via_driver_fops = {
65 .mmap = drm_mmap, 65 .mmap = drm_mmap,
66 .poll = drm_poll, 66 .poll = drm_poll,
67 .fasync = drm_fasync, 67 .fasync = drm_fasync,
68#ifdef CONFIG_COMPAT
69 .compat_ioctl = drm_compat_ioctl,
70#endif
68 .llseek = noop_llseek, 71 .llseek = noop_llseek,
69}; 72};
70 73
diff --git a/drivers/gpu/drm/vmwgfx/Kconfig b/drivers/gpu/drm/vmwgfx/Kconfig
index 794ff67c5701..b71bcd0bfbbf 100644
--- a/drivers/gpu/drm/vmwgfx/Kconfig
+++ b/drivers/gpu/drm/vmwgfx/Kconfig
@@ -12,3 +12,11 @@ config DRM_VMWGFX
12 This is a KMS enabled DRM driver for the VMware SVGA2 12 This is a KMS enabled DRM driver for the VMware SVGA2
13 virtual hardware. 13 virtual hardware.
14 The compiled module will be called "vmwgfx.ko". 14 The compiled module will be called "vmwgfx.ko".
15
16config DRM_VMWGFX_FBCON
17 depends on DRM_VMWGFX
18 bool "Enable framebuffer console under vmwgfx by default"
19 help
20 Choose this option if you are shipping a new vmwgfx
21 userspace driver that supports using the kernel driver.
22
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 4d9edead01ac..ba2c35dbf10e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -182,8 +182,9 @@ static struct pci_device_id vmw_pci_id_list[] = {
182 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 182 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
183 {0, 0, 0} 183 {0, 0, 0}
184}; 184};
185MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
185 186
186static int enable_fbdev; 187static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
187 188
188static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 189static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
189static void vmw_master_init(struct vmw_master *); 190static void vmw_master_init(struct vmw_master *);
@@ -1154,6 +1155,11 @@ static struct drm_driver driver = {
1154 .open = vmw_driver_open, 1155 .open = vmw_driver_open,
1155 .preclose = vmw_preclose, 1156 .preclose = vmw_preclose,
1156 .postclose = vmw_postclose, 1157 .postclose = vmw_postclose,
1158
1159 .dumb_create = vmw_dumb_create,
1160 .dumb_map_offset = vmw_dumb_map_offset,
1161 .dumb_destroy = vmw_dumb_destroy,
1162
1157 .fops = &vmwgfx_driver_fops, 1163 .fops = &vmwgfx_driver_fops,
1158 .name = VMWGFX_DRIVER_NAME, 1164 .name = VMWGFX_DRIVER_NAME,
1159 .desc = VMWGFX_DRIVER_DESC, 1165 .desc = VMWGFX_DRIVER_DESC,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index d0f2c079ee27..29c984ff7f23 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -645,6 +645,16 @@ int vmw_kms_readback(struct vmw_private *dev_priv,
645int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data, 645int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
646 struct drm_file *file_priv); 646 struct drm_file *file_priv);
647 647
648int vmw_dumb_create(struct drm_file *file_priv,
649 struct drm_device *dev,
650 struct drm_mode_create_dumb *args);
651
652int vmw_dumb_map_offset(struct drm_file *file_priv,
653 struct drm_device *dev, uint32_t handle,
654 uint64_t *offset);
655int vmw_dumb_destroy(struct drm_file *file_priv,
656 struct drm_device *dev,
657 uint32_t handle);
648/** 658/**
649 * Overlay control - vmwgfx_overlay.c 659 * Overlay control - vmwgfx_overlay.c
650 */ 660 */
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index 22bf9a21ec71..2c6ffe0e2c07 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -1917,3 +1917,76 @@ err_ref:
1917 vmw_resource_unreference(&res); 1917 vmw_resource_unreference(&res);
1918 return ret; 1918 return ret;
1919} 1919}
1920
1921
1922int vmw_dumb_create(struct drm_file *file_priv,
1923 struct drm_device *dev,
1924 struct drm_mode_create_dumb *args)
1925{
1926 struct vmw_private *dev_priv = vmw_priv(dev);
1927 struct vmw_master *vmaster = vmw_master(file_priv->master);
1928 struct vmw_user_dma_buffer *vmw_user_bo;
1929 struct ttm_buffer_object *tmp;
1930 int ret;
1931
1932 args->pitch = args->width * ((args->bpp + 7) / 8);
1933 args->size = args->pitch * args->height;
1934
1935 vmw_user_bo = kzalloc(sizeof(*vmw_user_bo), GFP_KERNEL);
1936 if (vmw_user_bo == NULL)
1937 return -ENOMEM;
1938
1939 ret = ttm_read_lock(&vmaster->lock, true);
1940 if (ret != 0) {
1941 kfree(vmw_user_bo);
1942 return ret;
1943 }
1944
1945 ret = vmw_dmabuf_init(dev_priv, &vmw_user_bo->dma, args->size,
1946 &vmw_vram_sys_placement, true,
1947 &vmw_user_dmabuf_destroy);
1948 if (ret != 0)
1949 goto out_no_dmabuf;
1950
1951 tmp = ttm_bo_reference(&vmw_user_bo->dma.base);
1952 ret = ttm_base_object_init(vmw_fpriv(file_priv)->tfile,
1953 &vmw_user_bo->base,
1954 false,
1955 ttm_buffer_type,
1956 &vmw_user_dmabuf_release, NULL);
1957 if (unlikely(ret != 0))
1958 goto out_no_base_object;
1959
1960 args->handle = vmw_user_bo->base.hash.key;
1961
1962out_no_base_object:
1963 ttm_bo_unref(&tmp);
1964out_no_dmabuf:
1965 ttm_read_unlock(&vmaster->lock);
1966 return ret;
1967}
1968
1969int vmw_dumb_map_offset(struct drm_file *file_priv,
1970 struct drm_device *dev, uint32_t handle,
1971 uint64_t *offset)
1972{
1973 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
1974 struct vmw_dma_buffer *out_buf;
1975 int ret;
1976
1977 ret = vmw_user_dmabuf_lookup(tfile, handle, &out_buf);
1978 if (ret != 0)
1979 return -EINVAL;
1980
1981 *offset = out_buf->base.addr_space_offset;
1982 vmw_dmabuf_unreference(&out_buf);
1983 return 0;
1984}
1985
1986int vmw_dumb_destroy(struct drm_file *file_priv,
1987 struct drm_device *dev,
1988 uint32_t handle)
1989{
1990 return ttm_ref_object_base_unref(vmw_fpriv(file_priv)->tfile,
1991 handle, TTM_REF_USAGE);
1992}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 23:36:30 -0500