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-rw-r--r--drivers/gpu/drm/drm_edid.c2
-rw-r--r--drivers/gpu/drm/drm_irq.c1
-rw-r--r--drivers/gpu/drm/drm_memory.c2
-rw-r--r--drivers/gpu/drm/drm_stub.c4
-rw-r--r--drivers/gpu/drm/drm_sysfs.c21
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c2
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c14
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c11
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h14
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c283
-rw-r--r--drivers/gpu/drm/i915/i915_gem_debug.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c32
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c16
-rw-r--r--drivers/gpu/drm/i915/i915_opregion.c54
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h13
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c68
-rw-r--r--drivers/gpu/drm/i915/intel_display.c107
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c256
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h18
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c92
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c2
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c86
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c81
-rw-r--r--drivers/gpu/drm/i915/intel_modes.c22
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c6
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c731
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c96
-rw-r--r--drivers/gpu/drm/nouveau/Makefile2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c127
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c67
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_debugfs.c5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h40
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_encoder.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c55
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c124
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_sgdma.c18
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c14
-rw-r--r--drivers/gpu/drm/nouveau/nv40_fifo.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c21
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c22
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.h1
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fbcon.c13
-rw-r--r--drivers/gpu/drm/nouveau/nv50_gpio.c76
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c7
-rw-r--r--drivers/gpu/drm/nouveau/nv50_grctx.c19
-rw-r--r--drivers/gpu/drm/nouveau/nv50_instmem.c16
-rw-r--r--drivers/gpu/drm/nouveau/nv50_sor.c25
-rw-r--r--drivers/gpu/drm/radeon/atom.c17
-rw-r--r--drivers/gpu/drm/radeon/atombios.h2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c4
-rw-r--r--drivers/gpu/drm/radeon/r100.c23
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h3
-rw-r--r--drivers/gpu/drm/radeon/r300.c23
-rw-r--r--drivers/gpu/drm/radeon/r300_cmdbuf.c2
-rw-r--r--drivers/gpu/drm/radeon/r420.c6
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c20
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c53
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c96
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h3
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c70
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h2
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r3002
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r4202
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rs6002
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv5153
-rw-r--r--drivers/gpu/drm/radeon/rs600.c2
-rw-r--r--drivers/gpu/drm/via/via_video.c2
80 files changed, 1866 insertions, 1266 deletions
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 2cc6e87d849d..18f41d7061f0 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -85,6 +85,8 @@ static struct edid_quirk {
85 85
86 /* Envision Peripherals, Inc. EN-7100e */ 86 /* Envision Peripherals, Inc. EN-7100e */
87 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 87 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
88 /* Envision EN2028 */
89 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
88 90
89 /* Funai Electronics PM36B */ 91 /* Funai Electronics PM36B */
90 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 92 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 3bd872761567..a263b7070fc6 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -476,6 +476,7 @@ void drm_vblank_off(struct drm_device *dev, int crtc)
476 unsigned long irqflags; 476 unsigned long irqflags;
477 477
478 spin_lock_irqsave(&dev->vbl_lock, irqflags); 478 spin_lock_irqsave(&dev->vbl_lock, irqflags);
479 dev->driver->disable_vblank(dev, crtc);
479 DRM_WAKEUP(&dev->vbl_queue[crtc]); 480 DRM_WAKEUP(&dev->vbl_queue[crtc]);
480 dev->vblank_enabled[crtc] = 0; 481 dev->vblank_enabled[crtc] = 0;
481 dev->last_vblank[crtc] = dev->driver->get_vblank_counter(dev, crtc); 482 dev->last_vblank[crtc] = dev->driver->get_vblank_counter(dev, crtc);
diff --git a/drivers/gpu/drm/drm_memory.c b/drivers/gpu/drm/drm_memory.c
index e4865f99989c..7732268eced2 100644
--- a/drivers/gpu/drm/drm_memory.c
+++ b/drivers/gpu/drm/drm_memory.c
@@ -77,7 +77,7 @@ static void *agp_remap(unsigned long offset, unsigned long size,
77 && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= 77 && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >=
78 (offset + size)) 78 (offset + size))
79 break; 79 break;
80 if (!agpmem) 80 if (&agpmem->head == &dev->agp->memory)
81 return NULL; 81 return NULL;
82 82
83 /* 83 /*
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index b743411d8144..a0c365f2e521 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -516,8 +516,6 @@ void drm_put_dev(struct drm_device *dev)
516 } 516 }
517 driver = dev->driver; 517 driver = dev->driver;
518 518
519 drm_vblank_cleanup(dev);
520
521 drm_lastclose(dev); 519 drm_lastclose(dev);
522 520
523 if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && 521 if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) &&
@@ -537,6 +535,8 @@ void drm_put_dev(struct drm_device *dev)
537 dev->agp = NULL; 535 dev->agp = NULL;
538 } 536 }
539 537
538 drm_vblank_cleanup(dev);
539
540 list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) 540 list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head)
541 drm_rmmap(dev, r_list->map); 541 drm_rmmap(dev, r_list->map);
542 drm_ht_remove(&dev->map_hash); 542 drm_ht_remove(&dev->map_hash);
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 1a1825b29f5f..25bbd30ed7af 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -354,7 +354,10 @@ static struct bin_attribute edid_attr = {
354int drm_sysfs_connector_add(struct drm_connector *connector) 354int drm_sysfs_connector_add(struct drm_connector *connector)
355{ 355{
356 struct drm_device *dev = connector->dev; 356 struct drm_device *dev = connector->dev;
357 int ret = 0, i, j; 357 int attr_cnt = 0;
358 int opt_cnt = 0;
359 int i;
360 int ret = 0;
358 361
359 /* We shouldn't get called more than once for the same connector */ 362 /* We shouldn't get called more than once for the same connector */
360 BUG_ON(device_is_registered(&connector->kdev)); 363 BUG_ON(device_is_registered(&connector->kdev));
@@ -377,8 +380,8 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
377 380
378 /* Standard attributes */ 381 /* Standard attributes */
379 382
380 for (i = 0; i < ARRAY_SIZE(connector_attrs); i++) { 383 for (attr_cnt = 0; attr_cnt < ARRAY_SIZE(connector_attrs); attr_cnt++) {
381 ret = device_create_file(&connector->kdev, &connector_attrs[i]); 384 ret = device_create_file(&connector->kdev, &connector_attrs[attr_cnt]);
382 if (ret) 385 if (ret)
383 goto err_out_files; 386 goto err_out_files;
384 } 387 }
@@ -394,8 +397,8 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
394 case DRM_MODE_CONNECTOR_SVIDEO: 397 case DRM_MODE_CONNECTOR_SVIDEO:
395 case DRM_MODE_CONNECTOR_Component: 398 case DRM_MODE_CONNECTOR_Component:
396 case DRM_MODE_CONNECTOR_TV: 399 case DRM_MODE_CONNECTOR_TV:
397 for (i = 0; i < ARRAY_SIZE(connector_attrs_opt1); i++) { 400 for (opt_cnt = 0; opt_cnt < ARRAY_SIZE(connector_attrs_opt1); opt_cnt++) {
398 ret = device_create_file(&connector->kdev, &connector_attrs_opt1[i]); 401 ret = device_create_file(&connector->kdev, &connector_attrs_opt1[opt_cnt]);
399 if (ret) 402 if (ret)
400 goto err_out_files; 403 goto err_out_files;
401 } 404 }
@@ -414,10 +417,10 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
414 return 0; 417 return 0;
415 418
416err_out_files: 419err_out_files:
417 if (i > 0) 420 for (i = 0; i < opt_cnt; i++)
418 for (j = 0; j < i; j++) 421 device_remove_file(&connector->kdev, &connector_attrs_opt1[i]);
419 device_remove_file(&connector->kdev, 422 for (i = 0; i < attr_cnt; i++)
420 &connector_attrs[i]); 423 device_remove_file(&connector->kdev, &connector_attrs[i]);
421 device_unregister(&connector->kdev); 424 device_unregister(&connector->kdev);
422 425
423out: 426out:
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b574503dddd0..a0b8447b06e7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -226,7 +226,7 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
226 } else { 226 } else {
227 struct drm_i915_gem_object *obj_priv; 227 struct drm_i915_gem_object *obj_priv;
228 228
229 obj_priv = obj->driver_private; 229 obj_priv = to_intel_bo(obj);
230 seq_printf(m, "Fenced object[%2d] = %p: %s " 230 seq_printf(m, "Fenced object[%2d] = %p: %s "
231 "%08x %08zx %08x %s %08x %08x %d", 231 "%08x %08zx %08x %s %08x %08x %d",
232 i, obj, get_pin_flag(obj_priv), 232 i, obj, get_pin_flag(obj_priv),
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2dc93939507d..c3cfafcbfe7d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1357,6 +1357,8 @@ static void i915_setup_compression(struct drm_device *dev, int size)
1357 1357
1358 dev_priv->cfb_size = size; 1358 dev_priv->cfb_size = size;
1359 1359
1360 dev_priv->compressed_fb = compressed_fb;
1361
1360 if (IS_GM45(dev)) { 1362 if (IS_GM45(dev)) {
1361 g4x_disable_fbc(dev); 1363 g4x_disable_fbc(dev);
1362 I915_WRITE(DPFC_CB_BASE, compressed_fb->start); 1364 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
@@ -1364,12 +1366,22 @@ static void i915_setup_compression(struct drm_device *dev, int size)
1364 i8xx_disable_fbc(dev); 1366 i8xx_disable_fbc(dev);
1365 I915_WRITE(FBC_CFB_BASE, cfb_base); 1367 I915_WRITE(FBC_CFB_BASE, cfb_base);
1366 I915_WRITE(FBC_LL_BASE, ll_base); 1368 I915_WRITE(FBC_LL_BASE, ll_base);
1369 dev_priv->compressed_llb = compressed_llb;
1367 } 1370 }
1368 1371
1369 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base, 1372 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1370 ll_base, size >> 20); 1373 ll_base, size >> 20);
1371} 1374}
1372 1375
1376static void i915_cleanup_compression(struct drm_device *dev)
1377{
1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379
1380 drm_mm_put_block(dev_priv->compressed_fb);
1381 if (!IS_GM45(dev))
1382 drm_mm_put_block(dev_priv->compressed_llb);
1383}
1384
1373/* true = enable decode, false = disable decoder */ 1385/* true = enable decode, false = disable decoder */
1374static unsigned int i915_vga_set_decode(void *cookie, bool state) 1386static unsigned int i915_vga_set_decode(void *cookie, bool state)
1375{ 1387{
@@ -1787,6 +1799,8 @@ int i915_driver_unload(struct drm_device *dev)
1787 mutex_lock(&dev->struct_mutex); 1799 mutex_lock(&dev->struct_mutex);
1788 i915_gem_cleanup_ringbuffer(dev); 1800 i915_gem_cleanup_ringbuffer(dev);
1789 mutex_unlock(&dev->struct_mutex); 1801 mutex_unlock(&dev->struct_mutex);
1802 if (I915_HAS_FBC(dev) && i915_powersave)
1803 i915_cleanup_compression(dev);
1790 drm_mm_takedown(&dev_priv->vram); 1804 drm_mm_takedown(&dev_priv->vram);
1791 i915_gem_lastclose(dev); 1805 i915_gem_lastclose(dev);
1792 1806
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4b26919abdb2..cc03537bb883 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -69,7 +69,8 @@ const static struct intel_device_info intel_845g_info = {
69}; 69};
70 70
71const static struct intel_device_info intel_i85x_info = { 71const static struct intel_device_info intel_i85x_info = {
72 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, 72 .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
73 .cursor_needs_physical = 1,
73}; 74};
74 75
75const static struct intel_device_info intel_i865g_info = { 76const static struct intel_device_info intel_i865g_info = {
@@ -80,14 +81,14 @@ const static struct intel_device_info intel_i915g_info = {
80 .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1, 81 .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
81}; 82};
82const static struct intel_device_info intel_i915gm_info = { 83const static struct intel_device_info intel_i915gm_info = {
83 .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1, 84 .is_i9xx = 1, .is_mobile = 1,
84 .cursor_needs_physical = 1, 85 .cursor_needs_physical = 1,
85}; 86};
86const static struct intel_device_info intel_i945g_info = { 87const static struct intel_device_info intel_i945g_info = {
87 .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1, 88 .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
88}; 89};
89const static struct intel_device_info intel_i945gm_info = { 90const static struct intel_device_info intel_i945gm_info = {
90 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1, 91 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
91 .has_hotplug = 1, .cursor_needs_physical = 1, 92 .has_hotplug = 1, .cursor_needs_physical = 1,
92}; 93};
93 94
@@ -151,7 +152,7 @@ const static struct pci_device_id pciidlist[] = {
151 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), 152 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
152 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), 153 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
153 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), 154 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
154 INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info), 155 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
155 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), 156 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
156 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), 157 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
157 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), 158 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
@@ -361,7 +362,7 @@ int i965_reset(struct drm_device *dev, u8 flags)
361 !dev_priv->mm.suspended) { 362 !dev_priv->mm.suspended) {
362 drm_i915_ring_buffer_t *ring = &dev_priv->ring; 363 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
363 struct drm_gem_object *obj = ring->ring_obj; 364 struct drm_gem_object *obj = ring->ring_obj;
364 struct drm_i915_gem_object *obj_priv = obj->driver_private; 365 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
365 dev_priv->mm.suspended = 0; 366 dev_priv->mm.suspended = 0;
366 367
367 /* Stop the ring if it's running. */ 368 /* Stop the ring if it's running. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index aba8260fbc5e..6e4790065d9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -195,6 +195,7 @@ struct intel_overlay;
195struct intel_device_info { 195struct intel_device_info {
196 u8 is_mobile : 1; 196 u8 is_mobile : 1;
197 u8 is_i8xx : 1; 197 u8 is_i8xx : 1;
198 u8 is_i85x : 1;
198 u8 is_i915g : 1; 199 u8 is_i915g : 1;
199 u8 is_i9xx : 1; 200 u8 is_i9xx : 1;
200 u8 is_i945gm : 1; 201 u8 is_i945gm : 1;
@@ -235,11 +236,14 @@ typedef struct drm_i915_private {
235 236
236 drm_dma_handle_t *status_page_dmah; 237 drm_dma_handle_t *status_page_dmah;
237 void *hw_status_page; 238 void *hw_status_page;
239 void *seqno_page;
238 dma_addr_t dma_status_page; 240 dma_addr_t dma_status_page;
239 uint32_t counter; 241 uint32_t counter;
240 unsigned int status_gfx_addr; 242 unsigned int status_gfx_addr;
243 unsigned int seqno_gfx_addr;
241 drm_local_map_t hws_map; 244 drm_local_map_t hws_map;
242 struct drm_gem_object *hws_obj; 245 struct drm_gem_object *hws_obj;
246 struct drm_gem_object *seqno_obj;
243 struct drm_gem_object *pwrctx; 247 struct drm_gem_object *pwrctx;
244 248
245 struct resource mch_res; 249 struct resource mch_res;
@@ -611,6 +615,8 @@ typedef struct drm_i915_private {
611 /* Reclocking support */ 615 /* Reclocking support */
612 bool render_reclock_avail; 616 bool render_reclock_avail;
613 bool lvds_downclock_avail; 617 bool lvds_downclock_avail;
618 /* indicate whether the LVDS EDID is OK */
619 bool lvds_edid_good;
614 /* indicates the reduced downclock for LVDS*/ 620 /* indicates the reduced downclock for LVDS*/
615 int lvds_downclock; 621 int lvds_downclock;
616 struct work_struct idle_work; 622 struct work_struct idle_work;
@@ -628,6 +634,9 @@ typedef struct drm_i915_private {
628 u8 max_delay; 634 u8 max_delay;
629 635
630 enum no_fbc_reason no_fbc_reason; 636 enum no_fbc_reason no_fbc_reason;
637
638 struct drm_mm_node *compressed_fb;
639 struct drm_mm_node *compressed_llb;
631} drm_i915_private_t; 640} drm_i915_private_t;
632 641
633/** driver private structure attached to each drm_gem_object */ 642/** driver private structure attached to each drm_gem_object */
@@ -731,6 +740,8 @@ struct drm_i915_gem_object {
731 atomic_t pending_flip; 740 atomic_t pending_flip;
732}; 741};
733 742
743#define to_intel_bo(x) ((struct drm_i915_gem_object *) (x)->driver_private)
744
734/** 745/**
735 * Request queue structure. 746 * Request queue structure.
736 * 747 *
@@ -1066,7 +1077,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1066 1077
1067#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1078#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1068#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1079#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1069#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 1080#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1070#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1081#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1071#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx) 1082#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1072#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1083#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
@@ -1131,6 +1142,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1131 1142
1132#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ 1143#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1133 IS_GEN6(dev)) 1144 IS_GEN6(dev))
1145#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1134 1146
1135#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1147#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1136 1148
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 368d726853d1..ef3d91dda71a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -163,7 +163,7 @@ fast_shmem_read(struct page **pages,
163static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) 163static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
164{ 164{
165 drm_i915_private_t *dev_priv = obj->dev->dev_private; 165 drm_i915_private_t *dev_priv = obj->dev->dev_private;
166 struct drm_i915_gem_object *obj_priv = obj->driver_private; 166 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
167 167
168 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 168 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
169 obj_priv->tiling_mode != I915_TILING_NONE; 169 obj_priv->tiling_mode != I915_TILING_NONE;
@@ -264,7 +264,7 @@ i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
264 struct drm_i915_gem_pread *args, 264 struct drm_i915_gem_pread *args,
265 struct drm_file *file_priv) 265 struct drm_file *file_priv)
266{ 266{
267 struct drm_i915_gem_object *obj_priv = obj->driver_private; 267 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
268 ssize_t remain; 268 ssize_t remain;
269 loff_t offset, page_base; 269 loff_t offset, page_base;
270 char __user *user_data; 270 char __user *user_data;
@@ -285,7 +285,7 @@ i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
285 if (ret != 0) 285 if (ret != 0)
286 goto fail_put_pages; 286 goto fail_put_pages;
287 287
288 obj_priv = obj->driver_private; 288 obj_priv = to_intel_bo(obj);
289 offset = args->offset; 289 offset = args->offset;
290 290
291 while (remain > 0) { 291 while (remain > 0) {
@@ -354,7 +354,7 @@ i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
354 struct drm_i915_gem_pread *args, 354 struct drm_i915_gem_pread *args,
355 struct drm_file *file_priv) 355 struct drm_file *file_priv)
356{ 356{
357 struct drm_i915_gem_object *obj_priv = obj->driver_private; 357 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
358 struct mm_struct *mm = current->mm; 358 struct mm_struct *mm = current->mm;
359 struct page **user_pages; 359 struct page **user_pages;
360 ssize_t remain; 360 ssize_t remain;
@@ -403,7 +403,7 @@ i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
403 if (ret != 0) 403 if (ret != 0)
404 goto fail_put_pages; 404 goto fail_put_pages;
405 405
406 obj_priv = obj->driver_private; 406 obj_priv = to_intel_bo(obj);
407 offset = args->offset; 407 offset = args->offset;
408 408
409 while (remain > 0) { 409 while (remain > 0) {
@@ -479,7 +479,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
479 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 479 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480 if (obj == NULL) 480 if (obj == NULL)
481 return -EBADF; 481 return -EBADF;
482 obj_priv = obj->driver_private; 482 obj_priv = to_intel_bo(obj);
483 483
484 /* Bounds check source. 484 /* Bounds check source.
485 * 485 *
@@ -581,7 +581,7 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
581 struct drm_i915_gem_pwrite *args, 581 struct drm_i915_gem_pwrite *args,
582 struct drm_file *file_priv) 582 struct drm_file *file_priv)
583{ 583{
584 struct drm_i915_gem_object *obj_priv = obj->driver_private; 584 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
585 drm_i915_private_t *dev_priv = dev->dev_private; 585 drm_i915_private_t *dev_priv = dev->dev_private;
586 ssize_t remain; 586 ssize_t remain;
587 loff_t offset, page_base; 587 loff_t offset, page_base;
@@ -605,7 +605,7 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
605 if (ret) 605 if (ret)
606 goto fail; 606 goto fail;
607 607
608 obj_priv = obj->driver_private; 608 obj_priv = to_intel_bo(obj);
609 offset = obj_priv->gtt_offset + args->offset; 609 offset = obj_priv->gtt_offset + args->offset;
610 610
611 while (remain > 0) { 611 while (remain > 0) {
@@ -655,7 +655,7 @@ i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
655 struct drm_i915_gem_pwrite *args, 655 struct drm_i915_gem_pwrite *args,
656 struct drm_file *file_priv) 656 struct drm_file *file_priv)
657{ 657{
658 struct drm_i915_gem_object *obj_priv = obj->driver_private; 658 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
659 drm_i915_private_t *dev_priv = dev->dev_private; 659 drm_i915_private_t *dev_priv = dev->dev_private;
660 ssize_t remain; 660 ssize_t remain;
661 loff_t gtt_page_base, offset; 661 loff_t gtt_page_base, offset;
@@ -699,7 +699,7 @@ i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
699 if (ret) 699 if (ret)
700 goto out_unpin_object; 700 goto out_unpin_object;
701 701
702 obj_priv = obj->driver_private; 702 obj_priv = to_intel_bo(obj);
703 offset = obj_priv->gtt_offset + args->offset; 703 offset = obj_priv->gtt_offset + args->offset;
704 704
705 while (remain > 0) { 705 while (remain > 0) {
@@ -761,7 +761,7 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
761 struct drm_i915_gem_pwrite *args, 761 struct drm_i915_gem_pwrite *args,
762 struct drm_file *file_priv) 762 struct drm_file *file_priv)
763{ 763{
764 struct drm_i915_gem_object *obj_priv = obj->driver_private; 764 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
765 ssize_t remain; 765 ssize_t remain;
766 loff_t offset, page_base; 766 loff_t offset, page_base;
767 char __user *user_data; 767 char __user *user_data;
@@ -781,7 +781,7 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
781 if (ret != 0) 781 if (ret != 0)
782 goto fail_put_pages; 782 goto fail_put_pages;
783 783
784 obj_priv = obj->driver_private; 784 obj_priv = to_intel_bo(obj);
785 offset = args->offset; 785 offset = args->offset;
786 obj_priv->dirty = 1; 786 obj_priv->dirty = 1;
787 787
@@ -829,7 +829,7 @@ i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
829 struct drm_i915_gem_pwrite *args, 829 struct drm_i915_gem_pwrite *args,
830 struct drm_file *file_priv) 830 struct drm_file *file_priv)
831{ 831{
832 struct drm_i915_gem_object *obj_priv = obj->driver_private; 832 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
833 struct mm_struct *mm = current->mm; 833 struct mm_struct *mm = current->mm;
834 struct page **user_pages; 834 struct page **user_pages;
835 ssize_t remain; 835 ssize_t remain;
@@ -877,7 +877,7 @@ i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
877 if (ret != 0) 877 if (ret != 0)
878 goto fail_put_pages; 878 goto fail_put_pages;
879 879
880 obj_priv = obj->driver_private; 880 obj_priv = to_intel_bo(obj);
881 offset = args->offset; 881 offset = args->offset;
882 obj_priv->dirty = 1; 882 obj_priv->dirty = 1;
883 883
@@ -952,7 +952,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
952 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 952 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
953 if (obj == NULL) 953 if (obj == NULL)
954 return -EBADF; 954 return -EBADF;
955 obj_priv = obj->driver_private; 955 obj_priv = to_intel_bo(obj);
956 956
957 /* Bounds check destination. 957 /* Bounds check destination.
958 * 958 *
@@ -1034,7 +1034,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1034 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1034 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1035 if (obj == NULL) 1035 if (obj == NULL)
1036 return -EBADF; 1036 return -EBADF;
1037 obj_priv = obj->driver_private; 1037 obj_priv = to_intel_bo(obj);
1038 1038
1039 mutex_lock(&dev->struct_mutex); 1039 mutex_lock(&dev->struct_mutex);
1040 1040
@@ -1096,7 +1096,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n", 1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1097 __func__, args->handle, obj, obj->size); 1097 __func__, args->handle, obj, obj->size);
1098#endif 1098#endif
1099 obj_priv = obj->driver_private; 1099 obj_priv = to_intel_bo(obj);
1100 1100
1101 /* Pinned buffers may be scanout, so flush the cache */ 1101 /* Pinned buffers may be scanout, so flush the cache */
1102 if (obj_priv->pin_count) 1102 if (obj_priv->pin_count)
@@ -1167,7 +1167,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1167 struct drm_gem_object *obj = vma->vm_private_data; 1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev; 1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private; 1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1171 pgoff_t page_offset; 1171 pgoff_t page_offset;
1172 unsigned long pfn; 1172 unsigned long pfn;
1173 int ret = 0; 1173 int ret = 0;
@@ -1234,7 +1234,7 @@ i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1234{ 1234{
1235 struct drm_device *dev = obj->dev; 1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private; 1236 struct drm_gem_mm *mm = dev->mm_private;
1237 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1238 struct drm_map_list *list; 1238 struct drm_map_list *list;
1239 struct drm_local_map *map; 1239 struct drm_local_map *map;
1240 int ret = 0; 1240 int ret = 0;
@@ -1305,7 +1305,7 @@ void
1305i915_gem_release_mmap(struct drm_gem_object *obj) 1305i915_gem_release_mmap(struct drm_gem_object *obj)
1306{ 1306{
1307 struct drm_device *dev = obj->dev; 1307 struct drm_device *dev = obj->dev;
1308 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1309 1309
1310 if (dev->dev_mapping) 1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping, 1311 unmap_mapping_range(dev->dev_mapping,
@@ -1316,7 +1316,7 @@ static void
1316i915_gem_free_mmap_offset(struct drm_gem_object *obj) 1316i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1317{ 1317{
1318 struct drm_device *dev = obj->dev; 1318 struct drm_device *dev = obj->dev;
1319 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1320 struct drm_gem_mm *mm = dev->mm_private; 1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list; 1321 struct drm_map_list *list;
1322 1322
@@ -1347,7 +1347,7 @@ static uint32_t
1347i915_gem_get_gtt_alignment(struct drm_gem_object *obj) 1347i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1348{ 1348{
1349 struct drm_device *dev = obj->dev; 1349 struct drm_device *dev = obj->dev;
1350 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1351 int start, i; 1351 int start, i;
1352 1352
1353 /* 1353 /*
@@ -1406,7 +1406,7 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1406 1406
1407 mutex_lock(&dev->struct_mutex); 1407 mutex_lock(&dev->struct_mutex);
1408 1408
1409 obj_priv = obj->driver_private; 1409 obj_priv = to_intel_bo(obj);
1410 1410
1411 if (obj_priv->madv != I915_MADV_WILLNEED) { 1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n"); 1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
@@ -1450,7 +1450,7 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1450void 1450void
1451i915_gem_object_put_pages(struct drm_gem_object *obj) 1451i915_gem_object_put_pages(struct drm_gem_object *obj)
1452{ 1452{
1453 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1454 int page_count = obj->size / PAGE_SIZE; 1454 int page_count = obj->size / PAGE_SIZE;
1455 int i; 1455 int i;
1456 1456
@@ -1486,7 +1486,7 @@ i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1486{ 1486{
1487 struct drm_device *dev = obj->dev; 1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private; 1488 drm_i915_private_t *dev_priv = dev->dev_private;
1489 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1490 1490
1491 /* Add a reference if we're newly entering the active list. */ 1491 /* Add a reference if we're newly entering the active list. */
1492 if (!obj_priv->active) { 1492 if (!obj_priv->active) {
@@ -1506,7 +1506,7 @@ i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1506{ 1506{
1507 struct drm_device *dev = obj->dev; 1507 struct drm_device *dev = obj->dev;
1508 drm_i915_private_t *dev_priv = dev->dev_private; 1508 drm_i915_private_t *dev_priv = dev->dev_private;
1509 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1510 1510
1511 BUG_ON(!obj_priv->active); 1511 BUG_ON(!obj_priv->active);
1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); 1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
@@ -1517,7 +1517,7 @@ i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1517static void 1517static void
1518i915_gem_object_truncate(struct drm_gem_object *obj) 1518i915_gem_object_truncate(struct drm_gem_object *obj)
1519{ 1519{
1520 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1520 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1521 struct inode *inode; 1521 struct inode *inode;
1522 1522
1523 inode = obj->filp->f_path.dentry->d_inode; 1523 inode = obj->filp->f_path.dentry->d_inode;
@@ -1538,7 +1538,7 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1538{ 1538{
1539 struct drm_device *dev = obj->dev; 1539 struct drm_device *dev = obj->dev;
1540 drm_i915_private_t *dev_priv = dev->dev_private; 1540 drm_i915_private_t *dev_priv = dev->dev_private;
1541 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1541 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1542 1542
1543 i915_verify_inactive(dev, __FILE__, __LINE__); 1543 i915_verify_inactive(dev, __FILE__, __LINE__);
1544 if (obj_priv->pin_count != 0) 1544 if (obj_priv->pin_count != 0)
@@ -1588,6 +1588,13 @@ i915_gem_process_flushing_list(struct drm_device *dev,
1588 } 1588 }
1589} 1589}
1590 1590
1591#define PIPE_CONTROL_FLUSH(addr) \
1592 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
1593 PIPE_CONTROL_DEPTH_STALL); \
1594 OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
1595 OUT_RING(0); \
1596 OUT_RING(0); \
1597
1591/** 1598/**
1592 * Creates a new sequence number, emitting a write of it to the status page 1599 * Creates a new sequence number, emitting a write of it to the status page
1593 * plus an interrupt, which will trigger i915_user_interrupt_handler. 1600 * plus an interrupt, which will trigger i915_user_interrupt_handler.
@@ -1622,13 +1629,47 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1622 if (dev_priv->mm.next_gem_seqno == 0) 1629 if (dev_priv->mm.next_gem_seqno == 0)
1623 dev_priv->mm.next_gem_seqno++; 1630 dev_priv->mm.next_gem_seqno++;
1624 1631
1625 BEGIN_LP_RING(4); 1632 if (HAS_PIPE_CONTROL(dev)) {
1626 OUT_RING(MI_STORE_DWORD_INDEX); 1633 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
1627 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1628 OUT_RING(seqno);
1629 1634
1630 OUT_RING(MI_USER_INTERRUPT); 1635 /*
1631 ADVANCE_LP_RING(); 1636 * Workaround qword write incoherence by flushing the
1637 * PIPE_NOTIFY buffers out to memory before requesting
1638 * an interrupt.
1639 */
1640 BEGIN_LP_RING(32);
1641 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
1642 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
1643 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
1644 OUT_RING(seqno);
1645 OUT_RING(0);
1646 PIPE_CONTROL_FLUSH(scratch_addr);
1647 scratch_addr += 128; /* write to separate cachelines */
1648 PIPE_CONTROL_FLUSH(scratch_addr);
1649 scratch_addr += 128;
1650 PIPE_CONTROL_FLUSH(scratch_addr);
1651 scratch_addr += 128;
1652 PIPE_CONTROL_FLUSH(scratch_addr);
1653 scratch_addr += 128;
1654 PIPE_CONTROL_FLUSH(scratch_addr);
1655 scratch_addr += 128;
1656 PIPE_CONTROL_FLUSH(scratch_addr);
1657 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
1658 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
1659 PIPE_CONTROL_NOTIFY);
1660 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
1661 OUT_RING(seqno);
1662 OUT_RING(0);
1663 ADVANCE_LP_RING();
1664 } else {
1665 BEGIN_LP_RING(4);
1666 OUT_RING(MI_STORE_DWORD_INDEX);
1667 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1668 OUT_RING(seqno);
1669
1670 OUT_RING(MI_USER_INTERRUPT);
1671 ADVANCE_LP_RING();
1672 }
1632 1673
1633 DRM_DEBUG_DRIVER("%d\n", seqno); 1674 DRM_DEBUG_DRIVER("%d\n", seqno);
1634 1675
@@ -1752,7 +1793,10 @@ i915_get_gem_seqno(struct drm_device *dev)
1752{ 1793{
1753 drm_i915_private_t *dev_priv = dev->dev_private; 1794 drm_i915_private_t *dev_priv = dev->dev_private;
1754 1795
1755 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); 1796 if (HAS_PIPE_CONTROL(dev))
1797 return ((volatile u32 *)(dev_priv->seqno_page))[0];
1798 else
1799 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1756} 1800}
1757 1801
1758/** 1802/**
@@ -1965,7 +2009,7 @@ static int
1965i915_gem_object_wait_rendering(struct drm_gem_object *obj) 2009i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1966{ 2010{
1967 struct drm_device *dev = obj->dev; 2011 struct drm_device *dev = obj->dev;
1968 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2012 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1969 int ret; 2013 int ret;
1970 2014
1971 /* This function only exists to support waiting for existing rendering, 2015 /* This function only exists to support waiting for existing rendering,
@@ -1997,7 +2041,7 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
1997{ 2041{
1998 struct drm_device *dev = obj->dev; 2042 struct drm_device *dev = obj->dev;
1999 drm_i915_private_t *dev_priv = dev->dev_private; 2043 drm_i915_private_t *dev_priv = dev->dev_private;
2000 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2044 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2001 int ret = 0; 2045 int ret = 0;
2002 2046
2003#if WATCH_BUF 2047#if WATCH_BUF
@@ -2173,7 +2217,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size)
2173#if WATCH_LRU 2217#if WATCH_LRU
2174 DRM_INFO("%s: evicting %p\n", __func__, obj); 2218 DRM_INFO("%s: evicting %p\n", __func__, obj);
2175#endif 2219#endif
2176 obj_priv = obj->driver_private; 2220 obj_priv = to_intel_bo(obj);
2177 BUG_ON(obj_priv->pin_count != 0); 2221 BUG_ON(obj_priv->pin_count != 0);
2178 BUG_ON(obj_priv->active); 2222 BUG_ON(obj_priv->active);
2179 2223
@@ -2244,7 +2288,7 @@ int
2244i915_gem_object_get_pages(struct drm_gem_object *obj, 2288i915_gem_object_get_pages(struct drm_gem_object *obj,
2245 gfp_t gfpmask) 2289 gfp_t gfpmask)
2246{ 2290{
2247 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2291 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2248 int page_count, i; 2292 int page_count, i;
2249 struct address_space *mapping; 2293 struct address_space *mapping;
2250 struct inode *inode; 2294 struct inode *inode;
@@ -2297,7 +2341,7 @@ static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2297 struct drm_gem_object *obj = reg->obj; 2341 struct drm_gem_object *obj = reg->obj;
2298 struct drm_device *dev = obj->dev; 2342 struct drm_device *dev = obj->dev;
2299 drm_i915_private_t *dev_priv = dev->dev_private; 2343 drm_i915_private_t *dev_priv = dev->dev_private;
2300 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2344 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2301 int regnum = obj_priv->fence_reg; 2345 int regnum = obj_priv->fence_reg;
2302 uint64_t val; 2346 uint64_t val;
2303 2347
@@ -2319,7 +2363,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2319 struct drm_gem_object *obj = reg->obj; 2363 struct drm_gem_object *obj = reg->obj;
2320 struct drm_device *dev = obj->dev; 2364 struct drm_device *dev = obj->dev;
2321 drm_i915_private_t *dev_priv = dev->dev_private; 2365 drm_i915_private_t *dev_priv = dev->dev_private;
2322 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2366 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2323 int regnum = obj_priv->fence_reg; 2367 int regnum = obj_priv->fence_reg;
2324 uint64_t val; 2368 uint64_t val;
2325 2369
@@ -2339,7 +2383,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2339 struct drm_gem_object *obj = reg->obj; 2383 struct drm_gem_object *obj = reg->obj;
2340 struct drm_device *dev = obj->dev; 2384 struct drm_device *dev = obj->dev;
2341 drm_i915_private_t *dev_priv = dev->dev_private; 2385 drm_i915_private_t *dev_priv = dev->dev_private;
2342 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2386 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2343 int regnum = obj_priv->fence_reg; 2387 int regnum = obj_priv->fence_reg;
2344 int tile_width; 2388 int tile_width;
2345 uint32_t fence_reg, val; 2389 uint32_t fence_reg, val;
@@ -2362,6 +2406,12 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2362 pitch_val = obj_priv->stride / tile_width; 2406 pitch_val = obj_priv->stride / tile_width;
2363 pitch_val = ffs(pitch_val) - 1; 2407 pitch_val = ffs(pitch_val) - 1;
2364 2408
2409 if (obj_priv->tiling_mode == I915_TILING_Y &&
2410 HAS_128_BYTE_Y_TILING(dev))
2411 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2412 else
2413 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2414
2365 val = obj_priv->gtt_offset; 2415 val = obj_priv->gtt_offset;
2366 if (obj_priv->tiling_mode == I915_TILING_Y) 2416 if (obj_priv->tiling_mode == I915_TILING_Y)
2367 val |= 1 << I830_FENCE_TILING_Y_SHIFT; 2417 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
@@ -2381,7 +2431,7 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2381 struct drm_gem_object *obj = reg->obj; 2431 struct drm_gem_object *obj = reg->obj;
2382 struct drm_device *dev = obj->dev; 2432 struct drm_device *dev = obj->dev;
2383 drm_i915_private_t *dev_priv = dev->dev_private; 2433 drm_i915_private_t *dev_priv = dev->dev_private;
2384 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2434 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2385 int regnum = obj_priv->fence_reg; 2435 int regnum = obj_priv->fence_reg;
2386 uint32_t val; 2436 uint32_t val;
2387 uint32_t pitch_val; 2437 uint32_t pitch_val;
@@ -2425,7 +2475,7 @@ static int i915_find_fence_reg(struct drm_device *dev)
2425 if (!reg->obj) 2475 if (!reg->obj)
2426 return i; 2476 return i;
2427 2477
2428 obj_priv = reg->obj->driver_private; 2478 obj_priv = to_intel_bo(reg->obj);
2429 if (!obj_priv->pin_count) 2479 if (!obj_priv->pin_count)
2430 avail++; 2480 avail++;
2431 } 2481 }
@@ -2480,7 +2530,7 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2480{ 2530{
2481 struct drm_device *dev = obj->dev; 2531 struct drm_device *dev = obj->dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private; 2532 struct drm_i915_private *dev_priv = dev->dev_private;
2483 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2533 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2484 struct drm_i915_fence_reg *reg = NULL; 2534 struct drm_i915_fence_reg *reg = NULL;
2485 int ret; 2535 int ret;
2486 2536
@@ -2547,7 +2597,7 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2547{ 2597{
2548 struct drm_device *dev = obj->dev; 2598 struct drm_device *dev = obj->dev;
2549 drm_i915_private_t *dev_priv = dev->dev_private; 2599 drm_i915_private_t *dev_priv = dev->dev_private;
2550 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2600 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2551 2601
2552 if (IS_GEN6(dev)) { 2602 if (IS_GEN6(dev)) {
2553 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + 2603 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
@@ -2583,7 +2633,7 @@ int
2583i915_gem_object_put_fence_reg(struct drm_gem_object *obj) 2633i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2584{ 2634{
2585 struct drm_device *dev = obj->dev; 2635 struct drm_device *dev = obj->dev;
2586 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2636 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2587 2637
2588 if (obj_priv->fence_reg == I915_FENCE_REG_NONE) 2638 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2589 return 0; 2639 return 0;
@@ -2621,7 +2671,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2621{ 2671{
2622 struct drm_device *dev = obj->dev; 2672 struct drm_device *dev = obj->dev;
2623 drm_i915_private_t *dev_priv = dev->dev_private; 2673 drm_i915_private_t *dev_priv = dev->dev_private;
2624 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2674 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2625 struct drm_mm_node *free_space; 2675 struct drm_mm_node *free_space;
2626 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; 2676 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2627 int ret; 2677 int ret;
@@ -2728,7 +2778,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2728void 2778void
2729i915_gem_clflush_object(struct drm_gem_object *obj) 2779i915_gem_clflush_object(struct drm_gem_object *obj)
2730{ 2780{
2731 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2781 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2732 2782
2733 /* If we don't have a page list set up, then we're not pinned 2783 /* If we don't have a page list set up, then we're not pinned
2734 * to GPU, and we can ignore the cache flush because it'll happen 2784 * to GPU, and we can ignore the cache flush because it'll happen
@@ -2829,7 +2879,7 @@ i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2829int 2879int
2830i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) 2880i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2831{ 2881{
2832 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2882 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2833 uint32_t old_write_domain, old_read_domains; 2883 uint32_t old_write_domain, old_read_domains;
2834 int ret; 2884 int ret;
2835 2885
@@ -2879,7 +2929,7 @@ int
2879i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) 2929i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2880{ 2930{
2881 struct drm_device *dev = obj->dev; 2931 struct drm_device *dev = obj->dev;
2882 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2932 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2883 uint32_t old_write_domain, old_read_domains; 2933 uint32_t old_write_domain, old_read_domains;
2884 int ret; 2934 int ret;
2885 2935
@@ -3092,7 +3142,7 @@ static void
3092i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) 3142i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3093{ 3143{
3094 struct drm_device *dev = obj->dev; 3144 struct drm_device *dev = obj->dev;
3095 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3145 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3096 uint32_t invalidate_domains = 0; 3146 uint32_t invalidate_domains = 0;
3097 uint32_t flush_domains = 0; 3147 uint32_t flush_domains = 0;
3098 uint32_t old_read_domains; 3148 uint32_t old_read_domains;
@@ -3177,7 +3227,7 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3177static void 3227static void
3178i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) 3228i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3179{ 3229{
3180 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3230 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3181 3231
3182 if (!obj_priv->page_cpu_valid) 3232 if (!obj_priv->page_cpu_valid)
3183 return; 3233 return;
@@ -3217,7 +3267,7 @@ static int
3217i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, 3267i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3218 uint64_t offset, uint64_t size) 3268 uint64_t offset, uint64_t size)
3219{ 3269{
3220 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3270 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3221 uint32_t old_read_domains; 3271 uint32_t old_read_domains;
3222 int i, ret; 3272 int i, ret;
3223 3273
@@ -3286,7 +3336,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3286{ 3336{
3287 struct drm_device *dev = obj->dev; 3337 struct drm_device *dev = obj->dev;
3288 drm_i915_private_t *dev_priv = dev->dev_private; 3338 drm_i915_private_t *dev_priv = dev->dev_private;
3289 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3339 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3290 int i, ret; 3340 int i, ret;
3291 void __iomem *reloc_page; 3341 void __iomem *reloc_page;
3292 bool need_fence; 3342 bool need_fence;
@@ -3337,7 +3387,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3337 i915_gem_object_unpin(obj); 3387 i915_gem_object_unpin(obj);
3338 return -EBADF; 3388 return -EBADF;
3339 } 3389 }
3340 target_obj_priv = target_obj->driver_private; 3390 target_obj_priv = to_intel_bo(target_obj);
3341 3391
3342#if WATCH_RELOC 3392#if WATCH_RELOC
3343 DRM_INFO("%s: obj %p offset %08x target %d " 3393 DRM_INFO("%s: obj %p offset %08x target %d "
@@ -3689,7 +3739,7 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
3689 prepare_to_wait(&dev_priv->pending_flip_queue, 3739 prepare_to_wait(&dev_priv->pending_flip_queue,
3690 &wait, TASK_INTERRUPTIBLE); 3740 &wait, TASK_INTERRUPTIBLE);
3691 for (i = 0; i < count; i++) { 3741 for (i = 0; i < count; i++) {
3692 obj_priv = object_list[i]->driver_private; 3742 obj_priv = to_intel_bo(object_list[i]);
3693 if (atomic_read(&obj_priv->pending_flip) > 0) 3743 if (atomic_read(&obj_priv->pending_flip) > 0)
3694 break; 3744 break;
3695 } 3745 }
@@ -3798,7 +3848,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3798 goto err; 3848 goto err;
3799 } 3849 }
3800 3850
3801 obj_priv = object_list[i]->driver_private; 3851 obj_priv = to_intel_bo(object_list[i]);
3802 if (obj_priv->in_execbuffer) { 3852 if (obj_priv->in_execbuffer) {
3803 DRM_ERROR("Object %p appears more than once in object list\n", 3853 DRM_ERROR("Object %p appears more than once in object list\n",
3804 object_list[i]); 3854 object_list[i]);
@@ -3924,7 +3974,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3924 3974
3925 for (i = 0; i < args->buffer_count; i++) { 3975 for (i = 0; i < args->buffer_count; i++) {
3926 struct drm_gem_object *obj = object_list[i]; 3976 struct drm_gem_object *obj = object_list[i];
3927 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3977 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3928 uint32_t old_write_domain = obj->write_domain; 3978 uint32_t old_write_domain = obj->write_domain;
3929 3979
3930 obj->write_domain = obj->pending_write_domain; 3980 obj->write_domain = obj->pending_write_domain;
@@ -3999,7 +4049,7 @@ err:
3999 4049
4000 for (i = 0; i < args->buffer_count; i++) { 4050 for (i = 0; i < args->buffer_count; i++) {
4001 if (object_list[i]) { 4051 if (object_list[i]) {
4002 obj_priv = object_list[i]->driver_private; 4052 obj_priv = to_intel_bo(object_list[i]);
4003 obj_priv->in_execbuffer = false; 4053 obj_priv->in_execbuffer = false;
4004 } 4054 }
4005 drm_gem_object_unreference(object_list[i]); 4055 drm_gem_object_unreference(object_list[i]);
@@ -4177,7 +4227,7 @@ int
4177i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) 4227i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4178{ 4228{
4179 struct drm_device *dev = obj->dev; 4229 struct drm_device *dev = obj->dev;
4180 struct drm_i915_gem_object *obj_priv = obj->driver_private; 4230 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4181 int ret; 4231 int ret;
4182 4232
4183 i915_verify_inactive(dev, __FILE__, __LINE__); 4233 i915_verify_inactive(dev, __FILE__, __LINE__);
@@ -4210,7 +4260,7 @@ i915_gem_object_unpin(struct drm_gem_object *obj)
4210{ 4260{
4211 struct drm_device *dev = obj->dev; 4261 struct drm_device *dev = obj->dev;
4212 drm_i915_private_t *dev_priv = dev->dev_private; 4262 drm_i915_private_t *dev_priv = dev->dev_private;
4213 struct drm_i915_gem_object *obj_priv = obj->driver_private; 4263 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4214 4264
4215 i915_verify_inactive(dev, __FILE__, __LINE__); 4265 i915_verify_inactive(dev, __FILE__, __LINE__);
4216 obj_priv->pin_count--; 4266 obj_priv->pin_count--;
@@ -4250,7 +4300,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4250 mutex_unlock(&dev->struct_mutex); 4300 mutex_unlock(&dev->struct_mutex);
4251 return -EBADF; 4301 return -EBADF;
4252 } 4302 }
4253 obj_priv = obj->driver_private; 4303 obj_priv = to_intel_bo(obj);
4254 4304
4255 if (obj_priv->madv != I915_MADV_WILLNEED) { 4305 if (obj_priv->madv != I915_MADV_WILLNEED) {
4256 DRM_ERROR("Attempting to pin a purgeable buffer\n"); 4306 DRM_ERROR("Attempting to pin a purgeable buffer\n");
@@ -4307,7 +4357,7 @@ i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4307 return -EBADF; 4357 return -EBADF;
4308 } 4358 }
4309 4359
4310 obj_priv = obj->driver_private; 4360 obj_priv = to_intel_bo(obj);
4311 if (obj_priv->pin_filp != file_priv) { 4361 if (obj_priv->pin_filp != file_priv) {
4312 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", 4362 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4313 args->handle); 4363 args->handle);
@@ -4349,7 +4399,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4349 */ 4399 */
4350 i915_gem_retire_requests(dev); 4400 i915_gem_retire_requests(dev);
4351 4401
4352 obj_priv = obj->driver_private; 4402 obj_priv = to_intel_bo(obj);
4353 /* Don't count being on the flushing list against the object being 4403 /* Don't count being on the flushing list against the object being
4354 * done. Otherwise, a buffer left on the flushing list but not getting 4404 * done. Otherwise, a buffer left on the flushing list but not getting
4355 * flushed (because nobody's flushing that domain) won't ever return 4405 * flushed (because nobody's flushing that domain) won't ever return
@@ -4395,7 +4445,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4395 } 4445 }
4396 4446
4397 mutex_lock(&dev->struct_mutex); 4447 mutex_lock(&dev->struct_mutex);
4398 obj_priv = obj->driver_private; 4448 obj_priv = to_intel_bo(obj);
4399 4449
4400 if (obj_priv->pin_count) { 4450 if (obj_priv->pin_count) {
4401 drm_gem_object_unreference(obj); 4451 drm_gem_object_unreference(obj);
@@ -4456,7 +4506,7 @@ int i915_gem_init_object(struct drm_gem_object *obj)
4456void i915_gem_free_object(struct drm_gem_object *obj) 4506void i915_gem_free_object(struct drm_gem_object *obj)
4457{ 4507{
4458 struct drm_device *dev = obj->dev; 4508 struct drm_device *dev = obj->dev;
4459 struct drm_i915_gem_object *obj_priv = obj->driver_private; 4509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4460 4510
4461 trace_i915_gem_object_destroy(obj); 4511 trace_i915_gem_object_destroy(obj);
4462 4512
@@ -4546,6 +4596,49 @@ i915_gem_idle(struct drm_device *dev)
4546 return 0; 4596 return 0;
4547} 4597}
4548 4598
4599/*
4600 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4601 * over cache flushing.
4602 */
4603static int
4604i915_gem_init_pipe_control(struct drm_device *dev)
4605{
4606 drm_i915_private_t *dev_priv = dev->dev_private;
4607 struct drm_gem_object *obj;
4608 struct drm_i915_gem_object *obj_priv;
4609 int ret;
4610
4611 obj = drm_gem_object_alloc(dev, 4096);
4612 if (obj == NULL) {
4613 DRM_ERROR("Failed to allocate seqno page\n");
4614 ret = -ENOMEM;
4615 goto err;
4616 }
4617 obj_priv = to_intel_bo(obj);
4618 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4619
4620 ret = i915_gem_object_pin(obj, 4096);
4621 if (ret)
4622 goto err_unref;
4623
4624 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4625 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4626 if (dev_priv->seqno_page == NULL)
4627 goto err_unpin;
4628
4629 dev_priv->seqno_obj = obj;
4630 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4631
4632 return 0;
4633
4634err_unpin:
4635 i915_gem_object_unpin(obj);
4636err_unref:
4637 drm_gem_object_unreference(obj);
4638err:
4639 return ret;
4640}
4641
4549static int 4642static int
4550i915_gem_init_hws(struct drm_device *dev) 4643i915_gem_init_hws(struct drm_device *dev)
4551{ 4644{
@@ -4563,15 +4656,16 @@ i915_gem_init_hws(struct drm_device *dev)
4563 obj = drm_gem_object_alloc(dev, 4096); 4656 obj = drm_gem_object_alloc(dev, 4096);
4564 if (obj == NULL) { 4657 if (obj == NULL) {
4565 DRM_ERROR("Failed to allocate status page\n"); 4658 DRM_ERROR("Failed to allocate status page\n");
4566 return -ENOMEM; 4659 ret = -ENOMEM;
4660 goto err;
4567 } 4661 }
4568 obj_priv = obj->driver_private; 4662 obj_priv = to_intel_bo(obj);
4569 obj_priv->agp_type = AGP_USER_CACHED_MEMORY; 4663 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4570 4664
4571 ret = i915_gem_object_pin(obj, 4096); 4665 ret = i915_gem_object_pin(obj, 4096);
4572 if (ret != 0) { 4666 if (ret != 0) {
4573 drm_gem_object_unreference(obj); 4667 drm_gem_object_unreference(obj);
4574 return ret; 4668 goto err_unref;
4575 } 4669 }
4576 4670
4577 dev_priv->status_gfx_addr = obj_priv->gtt_offset; 4671 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
@@ -4580,10 +4674,16 @@ i915_gem_init_hws(struct drm_device *dev)
4580 if (dev_priv->hw_status_page == NULL) { 4674 if (dev_priv->hw_status_page == NULL) {
4581 DRM_ERROR("Failed to map status page.\n"); 4675 DRM_ERROR("Failed to map status page.\n");
4582 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); 4676 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4583 i915_gem_object_unpin(obj); 4677 ret = -EINVAL;
4584 drm_gem_object_unreference(obj); 4678 goto err_unpin;
4585 return -EINVAL;
4586 } 4679 }
4680
4681 if (HAS_PIPE_CONTROL(dev)) {
4682 ret = i915_gem_init_pipe_control(dev);
4683 if (ret)
4684 goto err_unpin;
4685 }
4686
4587 dev_priv->hws_obj = obj; 4687 dev_priv->hws_obj = obj;
4588 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 4688 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4589 if (IS_GEN6(dev)) { 4689 if (IS_GEN6(dev)) {
@@ -4596,6 +4696,30 @@ i915_gem_init_hws(struct drm_device *dev)
4596 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); 4696 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4597 4697
4598 return 0; 4698 return 0;
4699
4700err_unpin:
4701 i915_gem_object_unpin(obj);
4702err_unref:
4703 drm_gem_object_unreference(obj);
4704err:
4705 return 0;
4706}
4707
4708static void
4709i915_gem_cleanup_pipe_control(struct drm_device *dev)
4710{
4711 drm_i915_private_t *dev_priv = dev->dev_private;
4712 struct drm_gem_object *obj;
4713 struct drm_i915_gem_object *obj_priv;
4714
4715 obj = dev_priv->seqno_obj;
4716 obj_priv = to_intel_bo(obj);
4717 kunmap(obj_priv->pages[0]);
4718 i915_gem_object_unpin(obj);
4719 drm_gem_object_unreference(obj);
4720 dev_priv->seqno_obj = NULL;
4721
4722 dev_priv->seqno_page = NULL;
4599} 4723}
4600 4724
4601static void 4725static void
@@ -4609,7 +4733,7 @@ i915_gem_cleanup_hws(struct drm_device *dev)
4609 return; 4733 return;
4610 4734
4611 obj = dev_priv->hws_obj; 4735 obj = dev_priv->hws_obj;
4612 obj_priv = obj->driver_private; 4736 obj_priv = to_intel_bo(obj);
4613 4737
4614 kunmap(obj_priv->pages[0]); 4738 kunmap(obj_priv->pages[0]);
4615 i915_gem_object_unpin(obj); 4739 i915_gem_object_unpin(obj);
@@ -4619,6 +4743,9 @@ i915_gem_cleanup_hws(struct drm_device *dev)
4619 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); 4743 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4620 dev_priv->hw_status_page = NULL; 4744 dev_priv->hw_status_page = NULL;
4621 4745
4746 if (HAS_PIPE_CONTROL(dev))
4747 i915_gem_cleanup_pipe_control(dev);
4748
4622 /* Write high address into HWS_PGA when disabling. */ 4749 /* Write high address into HWS_PGA when disabling. */
4623 I915_WRITE(HWS_PGA, 0x1ffff000); 4750 I915_WRITE(HWS_PGA, 0x1ffff000);
4624} 4751}
@@ -4643,7 +4770,7 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
4643 i915_gem_cleanup_hws(dev); 4770 i915_gem_cleanup_hws(dev);
4644 return -ENOMEM; 4771 return -ENOMEM;
4645 } 4772 }
4646 obj_priv = obj->driver_private; 4773 obj_priv = to_intel_bo(obj);
4647 4774
4648 ret = i915_gem_object_pin(obj, 4096); 4775 ret = i915_gem_object_pin(obj, 4096);
4649 if (ret != 0) { 4776 if (ret != 0) {
@@ -4936,7 +5063,7 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
4936 int ret; 5063 int ret;
4937 int page_count; 5064 int page_count;
4938 5065
4939 obj_priv = obj->driver_private; 5066 obj_priv = to_intel_bo(obj);
4940 if (!obj_priv->phys_obj) 5067 if (!obj_priv->phys_obj)
4941 return; 5068 return;
4942 5069
@@ -4975,7 +5102,7 @@ i915_gem_attach_phys_object(struct drm_device *dev,
4975 if (id > I915_MAX_PHYS_OBJECT) 5102 if (id > I915_MAX_PHYS_OBJECT)
4976 return -EINVAL; 5103 return -EINVAL;
4977 5104
4978 obj_priv = obj->driver_private; 5105 obj_priv = to_intel_bo(obj);
4979 5106
4980 if (obj_priv->phys_obj) { 5107 if (obj_priv->phys_obj) {
4981 if (obj_priv->phys_obj->id == id) 5108 if (obj_priv->phys_obj->id == id)
@@ -5026,7 +5153,7 @@ i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5026 struct drm_i915_gem_pwrite *args, 5153 struct drm_i915_gem_pwrite *args,
5027 struct drm_file *file_priv) 5154 struct drm_file *file_priv)
5028{ 5155{
5029 struct drm_i915_gem_object *obj_priv = obj->driver_private; 5156 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5030 void *obj_addr; 5157 void *obj_addr;
5031 int ret; 5158 int ret;
5032 char __user *user_data; 5159 char __user *user_data;
diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c
index e602614bd3f8..35507cf53fa3 100644
--- a/drivers/gpu/drm/i915/i915_gem_debug.c
+++ b/drivers/gpu/drm/i915/i915_gem_debug.c
@@ -72,7 +72,7 @@ void
72i915_gem_dump_object(struct drm_gem_object *obj, int len, 72i915_gem_dump_object(struct drm_gem_object *obj, int len,
73 const char *where, uint32_t mark) 73 const char *where, uint32_t mark)
74{ 74{
75 struct drm_i915_gem_object *obj_priv = obj->driver_private; 75 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
76 int page; 76 int page;
77 77
78 DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset); 78 DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
@@ -137,7 +137,7 @@ void
137i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle) 137i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
138{ 138{
139 struct drm_device *dev = obj->dev; 139 struct drm_device *dev = obj->dev;
140 struct drm_i915_gem_object *obj_priv = obj->driver_private; 140 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
141 int page; 141 int page;
142 uint32_t *gtt_mapping; 142 uint32_t *gtt_mapping;
143 uint32_t *backing_map = NULL; 143 uint32_t *backing_map = NULL;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index c01c878e51ba..4bdccefcf2cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -202,21 +202,17 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
202 * reg, so dont bother to check the size */ 202 * reg, so dont bother to check the size */
203 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) 203 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
204 return false; 204 return false;
205 } else if (IS_I9XX(dev)) { 205 } else if (IS_GEN3(dev) || IS_GEN2(dev)) {
206 uint32_t pitch_val = ffs(stride / tile_width) - 1; 206 if (stride > 8192)
207
208 /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB)
209 * instead of 4 (2KB) on 945s.
210 */
211 if (pitch_val > I915_FENCE_MAX_PITCH_VAL ||
212 size > (I830_FENCE_MAX_SIZE_VAL << 20))
213 return false; 207 return false;
214 } else {
215 uint32_t pitch_val = ffs(stride / tile_width) - 1;
216 208
217 if (pitch_val > I830_FENCE_MAX_PITCH_VAL || 209 if (IS_GEN3(dev)) {
218 size > (I830_FENCE_MAX_SIZE_VAL << 19)) 210 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
219 return false; 211 return false;
212 } else {
213 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
214 return false;
215 }
220 } 216 }
221 217
222 /* 965+ just needs multiples of tile width */ 218 /* 965+ just needs multiples of tile width */
@@ -240,7 +236,7 @@ bool
240i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode) 236i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode)
241{ 237{
242 struct drm_device *dev = obj->dev; 238 struct drm_device *dev = obj->dev;
243 struct drm_i915_gem_object *obj_priv = obj->driver_private; 239 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
244 240
245 if (obj_priv->gtt_space == NULL) 241 if (obj_priv->gtt_space == NULL)
246 return true; 242 return true;
@@ -280,7 +276,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
280 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 276 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
281 if (obj == NULL) 277 if (obj == NULL)
282 return -EINVAL; 278 return -EINVAL;
283 obj_priv = obj->driver_private; 279 obj_priv = to_intel_bo(obj);
284 280
285 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { 281 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
286 drm_gem_object_unreference_unlocked(obj); 282 drm_gem_object_unreference_unlocked(obj);
@@ -364,7 +360,7 @@ i915_gem_get_tiling(struct drm_device *dev, void *data,
364 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 360 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
365 if (obj == NULL) 361 if (obj == NULL)
366 return -EINVAL; 362 return -EINVAL;
367 obj_priv = obj->driver_private; 363 obj_priv = to_intel_bo(obj);
368 364
369 mutex_lock(&dev->struct_mutex); 365 mutex_lock(&dev->struct_mutex);
370 366
@@ -427,7 +423,7 @@ i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj)
427{ 423{
428 struct drm_device *dev = obj->dev; 424 struct drm_device *dev = obj->dev;
429 drm_i915_private_t *dev_priv = dev->dev_private; 425 drm_i915_private_t *dev_priv = dev->dev_private;
430 struct drm_i915_gem_object *obj_priv = obj->driver_private; 426 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
431 int page_count = obj->size >> PAGE_SHIFT; 427 int page_count = obj->size >> PAGE_SHIFT;
432 int i; 428 int i;
433 429
@@ -456,7 +452,7 @@ i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj)
456{ 452{
457 struct drm_device *dev = obj->dev; 453 struct drm_device *dev = obj->dev;
458 drm_i915_private_t *dev_priv = dev->dev_private; 454 drm_i915_private_t *dev_priv = dev->dev_private;
459 struct drm_i915_gem_object *obj_priv = obj->driver_private; 455 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
460 int page_count = obj->size >> PAGE_SHIFT; 456 int page_count = obj->size >> PAGE_SHIFT;
461 int i; 457 int i;
462 458
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 49c458bc6502..2b8b969d0c15 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -260,10 +260,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
260 260
261 if (mode_config->num_connector) { 261 if (mode_config->num_connector) {
262 list_for_each_entry(connector, &mode_config->connector_list, head) { 262 list_for_each_entry(connector, &mode_config->connector_list, head) {
263 struct intel_output *intel_output = to_intel_output(connector); 263 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
264 264
265 if (intel_output->hot_plug) 265 if (intel_encoder->hot_plug)
266 (*intel_output->hot_plug) (intel_output); 266 (*intel_encoder->hot_plug) (intel_encoder);
267 } 267 }
268 } 268 }
269 /* Just fire off a uevent and let userspace tell us what to do */ 269 /* Just fire off a uevent and let userspace tell us what to do */
@@ -349,7 +349,7 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
349 READ_BREADCRUMB(dev_priv); 349 READ_BREADCRUMB(dev_priv);
350 } 350 }
351 351
352 if (gt_iir & GT_USER_INTERRUPT) { 352 if (gt_iir & GT_PIPE_NOTIFY) {
353 u32 seqno = i915_get_gem_seqno(dev); 353 u32 seqno = i915_get_gem_seqno(dev);
354 dev_priv->mm.irq_gem_seqno = seqno; 354 dev_priv->mm.irq_gem_seqno = seqno;
355 trace_i915_gem_request_complete(dev, seqno); 355 trace_i915_gem_request_complete(dev, seqno);
@@ -444,7 +444,7 @@ i915_error_object_create(struct drm_device *dev,
444 if (src == NULL) 444 if (src == NULL)
445 return NULL; 445 return NULL;
446 446
447 src_priv = src->driver_private; 447 src_priv = to_intel_bo(src);
448 if (src_priv->pages == NULL) 448 if (src_priv->pages == NULL)
449 return NULL; 449 return NULL;
450 450
@@ -1005,7 +1005,7 @@ void i915_user_irq_get(struct drm_device *dev)
1005 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 1005 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1006 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { 1006 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
1007 if (HAS_PCH_SPLIT(dev)) 1007 if (HAS_PCH_SPLIT(dev))
1008 ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); 1008 ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
1009 else 1009 else
1010 i915_enable_irq(dev_priv, I915_USER_INTERRUPT); 1010 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1011 } 1011 }
@@ -1021,7 +1021,7 @@ void i915_user_irq_put(struct drm_device *dev)
1021 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); 1021 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
1022 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { 1022 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
1023 if (HAS_PCH_SPLIT(dev)) 1023 if (HAS_PCH_SPLIT(dev))
1024 ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); 1024 ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
1025 else 1025 else
1026 i915_disable_irq(dev_priv, I915_USER_INTERRUPT); 1026 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1027 } 1027 }
@@ -1305,7 +1305,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1305 /* enable kind of interrupts always enabled */ 1305 /* enable kind of interrupts always enabled */
1306 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1306 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1307 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1307 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1308 u32 render_mask = GT_USER_INTERRUPT; 1308 u32 render_mask = GT_PIPE_NOTIFY;
1309 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | 1309 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1310 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; 1310 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1311 1311
diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c
index 7cc8410239cb..8fcc75c1aa28 100644
--- a/drivers/gpu/drm/i915/i915_opregion.c
+++ b/drivers/gpu/drm/i915/i915_opregion.c
@@ -382,8 +382,57 @@ static void intel_didl_outputs(struct drm_device *dev)
382 struct drm_i915_private *dev_priv = dev->dev_private; 382 struct drm_i915_private *dev_priv = dev->dev_private;
383 struct intel_opregion *opregion = &dev_priv->opregion; 383 struct intel_opregion *opregion = &dev_priv->opregion;
384 struct drm_connector *connector; 384 struct drm_connector *connector;
385 acpi_handle handle;
386 struct acpi_device *acpi_dev, *acpi_cdev, *acpi_video_bus = NULL;
387 unsigned long long device_id;
388 acpi_status status;
385 int i = 0; 389 int i = 0;
386 390
391 handle = DEVICE_ACPI_HANDLE(&dev->pdev->dev);
392 if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &acpi_dev)))
393 return;
394
395 if (acpi_is_video_device(acpi_dev))
396 acpi_video_bus = acpi_dev;
397 else {
398 list_for_each_entry(acpi_cdev, &acpi_dev->children, node) {
399 if (acpi_is_video_device(acpi_cdev)) {
400 acpi_video_bus = acpi_cdev;
401 break;
402 }
403 }
404 }
405
406 if (!acpi_video_bus) {
407 printk(KERN_WARNING "No ACPI video bus found\n");
408 return;
409 }
410
411 list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
412 if (i >= 8) {
413 dev_printk (KERN_ERR, &dev->pdev->dev,
414 "More than 8 outputs detected\n");
415 return;
416 }
417 status =
418 acpi_evaluate_integer(acpi_cdev->handle, "_ADR",
419 NULL, &device_id);
420 if (ACPI_SUCCESS(status)) {
421 if (!device_id)
422 goto blind_set;
423 opregion->acpi->didl[i] = (u32)(device_id & 0x0f0f);
424 i++;
425 }
426 }
427
428end:
429 /* If fewer than 8 outputs, the list must be null terminated */
430 if (i < 8)
431 opregion->acpi->didl[i] = 0;
432 return;
433
434blind_set:
435 i = 0;
387 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 436 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
388 int output_type = ACPI_OTHER_OUTPUT; 437 int output_type = ACPI_OTHER_OUTPUT;
389 if (i >= 8) { 438 if (i >= 8) {
@@ -416,10 +465,7 @@ static void intel_didl_outputs(struct drm_device *dev)
416 opregion->acpi->didl[i] |= (1<<31) | output_type | i; 465 opregion->acpi->didl[i] |= (1<<31) | output_type | i;
417 i++; 466 i++;
418 } 467 }
419 468 goto end;
420 /* If fewer than 8 outputs, the list must be null terminated */
421 if (i < 8)
422 opregion->acpi->didl[i] = 0;
423} 469}
424 470
425int intel_opregion_init(struct drm_device *dev, int resume) 471int intel_opregion_init(struct drm_device *dev, int resume)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbbf59f56dfa..4cbc5210fd30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -230,6 +230,16 @@
230#define ASYNC_FLIP (1<<22) 230#define ASYNC_FLIP (1<<22)
231#define DISPLAY_PLANE_A (0<<20) 231#define DISPLAY_PLANE_A (0<<20)
232#define DISPLAY_PLANE_B (1<<20) 232#define DISPLAY_PLANE_B (1<<20)
233#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
234#define PIPE_CONTROL_QW_WRITE (1<<14)
235#define PIPE_CONTROL_DEPTH_STALL (1<<13)
236#define PIPE_CONTROL_WC_FLUSH (1<<12)
237#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
238#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
239#define PIPE_CONTROL_ISP_DIS (1<<9)
240#define PIPE_CONTROL_NOTIFY (1<<8)
241#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
242#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
233 243
234/* 244/*
235 * Fence registers 245 * Fence registers
@@ -241,7 +251,7 @@
241#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 251#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
242#define I830_FENCE_PITCH_SHIFT 4 252#define I830_FENCE_PITCH_SHIFT 4
243#define I830_FENCE_REG_VALID (1<<0) 253#define I830_FENCE_REG_VALID (1<<0)
244#define I915_FENCE_MAX_PITCH_VAL 0x10 254#define I915_FENCE_MAX_PITCH_VAL 4
245#define I830_FENCE_MAX_PITCH_VAL 6 255#define I830_FENCE_MAX_PITCH_VAL 6
246#define I830_FENCE_MAX_SIZE_VAL (1<<8) 256#define I830_FENCE_MAX_SIZE_VAL (1<<8)
247 257
@@ -2285,6 +2295,7 @@
2285#define DEIER 0x4400c 2295#define DEIER 0x4400c
2286 2296
2287/* GT interrupt */ 2297/* GT interrupt */
2298#define GT_PIPE_NOTIFY (1 << 4)
2288#define GT_SYNC_STATUS (1 << 2) 2299#define GT_SYNC_STATUS (1 << 2)
2289#define GT_USER_INTERRUPT (1 << 0) 2300#define GT_USER_INTERRUPT (1 << 0)
2290 2301
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 38110ce742a5..759c2ef72eff 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -247,19 +247,19 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
247 247
248static bool intel_crt_detect_ddc(struct drm_connector *connector) 248static bool intel_crt_detect_ddc(struct drm_connector *connector)
249{ 249{
250 struct intel_output *intel_output = to_intel_output(connector); 250 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
251 251
252 /* CRT should always be at 0, but check anyway */ 252 /* CRT should always be at 0, but check anyway */
253 if (intel_output->type != INTEL_OUTPUT_ANALOG) 253 if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
254 return false; 254 return false;
255 255
256 return intel_ddc_probe(intel_output); 256 return intel_ddc_probe(intel_encoder);
257} 257}
258 258
259static enum drm_connector_status 259static enum drm_connector_status
260intel_crt_load_detect(struct drm_crtc *crtc, struct intel_output *intel_output) 260intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder)
261{ 261{
262 struct drm_encoder *encoder = &intel_output->enc; 262 struct drm_encoder *encoder = &intel_encoder->enc;
263 struct drm_device *dev = encoder->dev; 263 struct drm_device *dev = encoder->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private; 264 struct drm_i915_private *dev_priv = dev->dev_private;
265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -387,8 +387,8 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_output *intel_output)
387static enum drm_connector_status intel_crt_detect(struct drm_connector *connector) 387static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
388{ 388{
389 struct drm_device *dev = connector->dev; 389 struct drm_device *dev = connector->dev;
390 struct intel_output *intel_output = to_intel_output(connector); 390 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
391 struct drm_encoder *encoder = &intel_output->enc; 391 struct drm_encoder *encoder = &intel_encoder->enc;
392 struct drm_crtc *crtc; 392 struct drm_crtc *crtc;
393 int dpms_mode; 393 int dpms_mode;
394 enum drm_connector_status status; 394 enum drm_connector_status status;
@@ -405,13 +405,13 @@ static enum drm_connector_status intel_crt_detect(struct drm_connector *connecto
405 405
406 /* for pre-945g platforms use load detect */ 406 /* for pre-945g platforms use load detect */
407 if (encoder->crtc && encoder->crtc->enabled) { 407 if (encoder->crtc && encoder->crtc->enabled) {
408 status = intel_crt_load_detect(encoder->crtc, intel_output); 408 status = intel_crt_load_detect(encoder->crtc, intel_encoder);
409 } else { 409 } else {
410 crtc = intel_get_load_detect_pipe(intel_output, 410 crtc = intel_get_load_detect_pipe(intel_encoder,
411 NULL, &dpms_mode); 411 NULL, &dpms_mode);
412 if (crtc) { 412 if (crtc) {
413 status = intel_crt_load_detect(crtc, intel_output); 413 status = intel_crt_load_detect(crtc, intel_encoder);
414 intel_release_load_detect_pipe(intel_output, dpms_mode); 414 intel_release_load_detect_pipe(intel_encoder, dpms_mode);
415 } else 415 } else
416 status = connector_status_unknown; 416 status = connector_status_unknown;
417 } 417 }
@@ -421,9 +421,9 @@ static enum drm_connector_status intel_crt_detect(struct drm_connector *connecto
421 421
422static void intel_crt_destroy(struct drm_connector *connector) 422static void intel_crt_destroy(struct drm_connector *connector)
423{ 423{
424 struct intel_output *intel_output = to_intel_output(connector); 424 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
425 425
426 intel_i2c_destroy(intel_output->ddc_bus); 426 intel_i2c_destroy(intel_encoder->ddc_bus);
427 drm_sysfs_connector_remove(connector); 427 drm_sysfs_connector_remove(connector);
428 drm_connector_cleanup(connector); 428 drm_connector_cleanup(connector);
429 kfree(connector); 429 kfree(connector);
@@ -432,28 +432,28 @@ static void intel_crt_destroy(struct drm_connector *connector)
432static int intel_crt_get_modes(struct drm_connector *connector) 432static int intel_crt_get_modes(struct drm_connector *connector)
433{ 433{
434 int ret; 434 int ret;
435 struct intel_output *intel_output = to_intel_output(connector); 435 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
436 struct i2c_adapter *ddcbus; 436 struct i2c_adapter *ddcbus;
437 struct drm_device *dev = connector->dev; 437 struct drm_device *dev = connector->dev;
438 438
439 439
440 ret = intel_ddc_get_modes(intel_output); 440 ret = intel_ddc_get_modes(intel_encoder);
441 if (ret || !IS_G4X(dev)) 441 if (ret || !IS_G4X(dev))
442 goto end; 442 goto end;
443 443
444 ddcbus = intel_output->ddc_bus; 444 ddcbus = intel_encoder->ddc_bus;
445 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 445 /* Try to probe digital port for output in DVI-I -> VGA mode. */
446 intel_output->ddc_bus = 446 intel_encoder->ddc_bus =
447 intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D"); 447 intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D");
448 448
449 if (!intel_output->ddc_bus) { 449 if (!intel_encoder->ddc_bus) {
450 intel_output->ddc_bus = ddcbus; 450 intel_encoder->ddc_bus = ddcbus;
451 dev_printk(KERN_ERR, &connector->dev->pdev->dev, 451 dev_printk(KERN_ERR, &connector->dev->pdev->dev,
452 "DDC bus registration failed for CRTDDC_D.\n"); 452 "DDC bus registration failed for CRTDDC_D.\n");
453 goto end; 453 goto end;
454 } 454 }
455 /* Try to get modes by GPIOD port */ 455 /* Try to get modes by GPIOD port */
456 ret = intel_ddc_get_modes(intel_output); 456 ret = intel_ddc_get_modes(intel_encoder);
457 intel_i2c_destroy(ddcbus); 457 intel_i2c_destroy(ddcbus);
458 458
459end: 459end:
@@ -506,23 +506,23 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
506void intel_crt_init(struct drm_device *dev) 506void intel_crt_init(struct drm_device *dev)
507{ 507{
508 struct drm_connector *connector; 508 struct drm_connector *connector;
509 struct intel_output *intel_output; 509 struct intel_encoder *intel_encoder;
510 struct drm_i915_private *dev_priv = dev->dev_private; 510 struct drm_i915_private *dev_priv = dev->dev_private;
511 u32 i2c_reg; 511 u32 i2c_reg;
512 512
513 intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); 513 intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
514 if (!intel_output) 514 if (!intel_encoder)
515 return; 515 return;
516 516
517 connector = &intel_output->base; 517 connector = &intel_encoder->base;
518 drm_connector_init(dev, &intel_output->base, 518 drm_connector_init(dev, &intel_encoder->base,
519 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 519 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
520 520
521 drm_encoder_init(dev, &intel_output->enc, &intel_crt_enc_funcs, 521 drm_encoder_init(dev, &intel_encoder->enc, &intel_crt_enc_funcs,
522 DRM_MODE_ENCODER_DAC); 522 DRM_MODE_ENCODER_DAC);
523 523
524 drm_mode_connector_attach_encoder(&intel_output->base, 524 drm_mode_connector_attach_encoder(&intel_encoder->base,
525 &intel_output->enc); 525 &intel_encoder->enc);
526 526
527 /* Set up the DDC bus. */ 527 /* Set up the DDC bus. */
528 if (HAS_PCH_SPLIT(dev)) 528 if (HAS_PCH_SPLIT(dev))
@@ -533,22 +533,22 @@ void intel_crt_init(struct drm_device *dev)
533 if (dev_priv->crt_ddc_bus != 0) 533 if (dev_priv->crt_ddc_bus != 0)
534 i2c_reg = dev_priv->crt_ddc_bus; 534 i2c_reg = dev_priv->crt_ddc_bus;
535 } 535 }
536 intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); 536 intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
537 if (!intel_output->ddc_bus) { 537 if (!intel_encoder->ddc_bus) {
538 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " 538 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
539 "failed.\n"); 539 "failed.\n");
540 return; 540 return;
541 } 541 }
542 542
543 intel_output->type = INTEL_OUTPUT_ANALOG; 543 intel_encoder->type = INTEL_OUTPUT_ANALOG;
544 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 544 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
545 (1 << INTEL_ANALOG_CLONE_BIT) | 545 (1 << INTEL_ANALOG_CLONE_BIT) |
546 (1 << INTEL_SDVO_LVDS_CLONE_BIT); 546 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
547 intel_output->crtc_mask = (1 << 0) | (1 << 1); 547 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
548 connector->interlace_allowed = 0; 548 connector->interlace_allowed = 0;
549 connector->doublescan_allowed = 0; 549 connector->doublescan_allowed = 0;
550 550
551 drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs); 551 drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs);
552 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 552 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
553 553
554 drm_sysfs_connector_add(connector); 554 drm_sysfs_connector_add(connector);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e7e753b2845f..c7502b6b1600 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -747,16 +747,16 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
747 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 747 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
748 if (l_entry->encoder && 748 if (l_entry->encoder &&
749 l_entry->encoder->crtc == crtc) { 749 l_entry->encoder->crtc == crtc) {
750 struct intel_output *intel_output = to_intel_output(l_entry); 750 struct intel_encoder *intel_encoder = to_intel_encoder(l_entry);
751 if (intel_output->type == type) 751 if (intel_encoder->type == type)
752 return true; 752 return true;
753 } 753 }
754 } 754 }
755 return false; 755 return false;
756} 756}
757 757
758struct drm_connector * 758static struct drm_connector *
759intel_pipe_get_output (struct drm_crtc *crtc) 759intel_pipe_get_connector (struct drm_crtc *crtc)
760{ 760{
761 struct drm_device *dev = crtc->dev; 761 struct drm_device *dev = crtc->dev;
762 struct drm_mode_config *mode_config = &dev->mode_config; 762 struct drm_mode_config *mode_config = &dev->mode_config;
@@ -1003,7 +1003,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1003 struct drm_i915_private *dev_priv = dev->dev_private; 1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 struct drm_framebuffer *fb = crtc->fb; 1004 struct drm_framebuffer *fb = crtc->fb;
1005 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1005 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1006 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private; 1006 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008 int plane, i; 1008 int plane, i;
1009 u32 fbc_ctl, fbc_ctl2; 1009 u32 fbc_ctl, fbc_ctl2;
@@ -1080,7 +1080,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1080 struct drm_i915_private *dev_priv = dev->dev_private; 1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 struct drm_framebuffer *fb = crtc->fb; 1081 struct drm_framebuffer *fb = crtc->fb;
1082 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1082 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1083 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private; 1083 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1085 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : 1085 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1086 DPFC_CTL_PLANEB); 1086 DPFC_CTL_PLANEB);
@@ -1176,7 +1176,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1176 return; 1176 return;
1177 1177
1178 intel_fb = to_intel_framebuffer(fb); 1178 intel_fb = to_intel_framebuffer(fb);
1179 obj_priv = intel_fb->obj->driver_private; 1179 obj_priv = to_intel_bo(intel_fb->obj);
1180 1180
1181 /* 1181 /*
1182 * If FBC is already on, we just have to verify that we can 1182 * If FBC is already on, we just have to verify that we can
@@ -1243,7 +1243,7 @@ out_disable:
1243static int 1243static int
1244intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj) 1244intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1245{ 1245{
1246 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1246 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1247 u32 alignment; 1247 u32 alignment;
1248 int ret; 1248 int ret;
1249 1249
@@ -1323,7 +1323,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1323 1323
1324 intel_fb = to_intel_framebuffer(crtc->fb); 1324 intel_fb = to_intel_framebuffer(crtc->fb);
1325 obj = intel_fb->obj; 1325 obj = intel_fb->obj;
1326 obj_priv = obj->driver_private; 1326 obj_priv = to_intel_bo(obj);
1327 1327
1328 mutex_lock(&dev->struct_mutex); 1328 mutex_lock(&dev->struct_mutex);
1329 ret = intel_pin_and_fence_fb_obj(dev, obj); 1329 ret = intel_pin_and_fence_fb_obj(dev, obj);
@@ -1401,7 +1401,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1401 1401
1402 if (old_fb) { 1402 if (old_fb) {
1403 intel_fb = to_intel_framebuffer(old_fb); 1403 intel_fb = to_intel_framebuffer(old_fb);
1404 obj_priv = intel_fb->obj->driver_private; 1404 obj_priv = to_intel_bo(intel_fb->obj);
1405 i915_gem_object_unpin(intel_fb->obj); 1405 i915_gem_object_unpin(intel_fb->obj);
1406 } 1406 }
1407 intel_increase_pllclock(crtc, true); 1407 intel_increase_pllclock(crtc, true);
@@ -2917,7 +2917,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2917 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE; 2917 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2918 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS; 2918 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2919 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 2919 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2920 int refclk, num_outputs = 0; 2920 int refclk, num_connectors = 0;
2921 intel_clock_t clock, reduced_clock; 2921 intel_clock_t clock, reduced_clock;
2922 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 2922 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2923 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 2923 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
@@ -2943,19 +2943,19 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2943 drm_vblank_pre_modeset(dev, pipe); 2943 drm_vblank_pre_modeset(dev, pipe);
2944 2944
2945 list_for_each_entry(connector, &mode_config->connector_list, head) { 2945 list_for_each_entry(connector, &mode_config->connector_list, head) {
2946 struct intel_output *intel_output = to_intel_output(connector); 2946 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2947 2947
2948 if (!connector->encoder || connector->encoder->crtc != crtc) 2948 if (!connector->encoder || connector->encoder->crtc != crtc)
2949 continue; 2949 continue;
2950 2950
2951 switch (intel_output->type) { 2951 switch (intel_encoder->type) {
2952 case INTEL_OUTPUT_LVDS: 2952 case INTEL_OUTPUT_LVDS:
2953 is_lvds = true; 2953 is_lvds = true;
2954 break; 2954 break;
2955 case INTEL_OUTPUT_SDVO: 2955 case INTEL_OUTPUT_SDVO:
2956 case INTEL_OUTPUT_HDMI: 2956 case INTEL_OUTPUT_HDMI:
2957 is_sdvo = true; 2957 is_sdvo = true;
2958 if (intel_output->needs_tv_clock) 2958 if (intel_encoder->needs_tv_clock)
2959 is_tv = true; 2959 is_tv = true;
2960 break; 2960 break;
2961 case INTEL_OUTPUT_DVO: 2961 case INTEL_OUTPUT_DVO:
@@ -2975,10 +2975,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2975 break; 2975 break;
2976 } 2976 }
2977 2977
2978 num_outputs++; 2978 num_connectors++;
2979 } 2979 }
2980 2980
2981 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { 2981 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
2982 refclk = dev_priv->lvds_ssc_freq * 1000; 2982 refclk = dev_priv->lvds_ssc_freq * 1000;
2983 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 2983 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2984 refclk / 1000); 2984 refclk / 1000);
@@ -3049,8 +3049,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3049 if (is_edp) { 3049 if (is_edp) {
3050 struct drm_connector *edp; 3050 struct drm_connector *edp;
3051 target_clock = mode->clock; 3051 target_clock = mode->clock;
3052 edp = intel_pipe_get_output(crtc); 3052 edp = intel_pipe_get_connector(crtc);
3053 intel_edp_link_config(to_intel_output(edp), 3053 intel_edp_link_config(to_intel_encoder(edp),
3054 &lane, &link_bw); 3054 &lane, &link_bw);
3055 } else { 3055 } else {
3056 /* DP over FDI requires target mode clock 3056 /* DP over FDI requires target mode clock
@@ -3231,7 +3231,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3231 /* XXX: just matching BIOS for now */ 3231 /* XXX: just matching BIOS for now */
3232 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 3232 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3233 dpll |= 3; 3233 dpll |= 3;
3234 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) 3234 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3235 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 3235 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3236 else 3236 else
3237 dpll |= PLL_REF_INPUT_DREFCLK; 3237 dpll |= PLL_REF_INPUT_DREFCLK;
@@ -3511,7 +3511,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3511 if (!bo) 3511 if (!bo)
3512 return -ENOENT; 3512 return -ENOENT;
3513 3513
3514 obj_priv = bo->driver_private; 3514 obj_priv = to_intel_bo(bo);
3515 3515
3516 if (bo->size < width * height * 4) { 3516 if (bo->size < width * height * 4) {
3517 DRM_ERROR("buffer is to small\n"); 3517 DRM_ERROR("buffer is to small\n");
@@ -3655,9 +3655,9 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3655 * detection. 3655 * detection.
3656 * 3656 *
3657 * It will be up to the load-detect code to adjust the pipe as appropriate for 3657 * It will be up to the load-detect code to adjust the pipe as appropriate for
3658 * its requirements. The pipe will be connected to no other outputs. 3658 * its requirements. The pipe will be connected to no other encoders.
3659 * 3659 *
3660 * Currently this code will only succeed if there is a pipe with no outputs 3660 * Currently this code will only succeed if there is a pipe with no encoders
3661 * configured for it. In the future, it could choose to temporarily disable 3661 * configured for it. In the future, it could choose to temporarily disable
3662 * some outputs to free up a pipe for its use. 3662 * some outputs to free up a pipe for its use.
3663 * 3663 *
@@ -3670,14 +3670,14 @@ static struct drm_display_mode load_detect_mode = {
3670 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 3670 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3671}; 3671};
3672 3672
3673struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, 3673struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3674 struct drm_display_mode *mode, 3674 struct drm_display_mode *mode,
3675 int *dpms_mode) 3675 int *dpms_mode)
3676{ 3676{
3677 struct intel_crtc *intel_crtc; 3677 struct intel_crtc *intel_crtc;
3678 struct drm_crtc *possible_crtc; 3678 struct drm_crtc *possible_crtc;
3679 struct drm_crtc *supported_crtc =NULL; 3679 struct drm_crtc *supported_crtc =NULL;
3680 struct drm_encoder *encoder = &intel_output->enc; 3680 struct drm_encoder *encoder = &intel_encoder->enc;
3681 struct drm_crtc *crtc = NULL; 3681 struct drm_crtc *crtc = NULL;
3682 struct drm_device *dev = encoder->dev; 3682 struct drm_device *dev = encoder->dev;
3683 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3683 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
@@ -3729,8 +3729,8 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3729 } 3729 }
3730 3730
3731 encoder->crtc = crtc; 3731 encoder->crtc = crtc;
3732 intel_output->base.encoder = encoder; 3732 intel_encoder->base.encoder = encoder;
3733 intel_output->load_detect_temp = true; 3733 intel_encoder->load_detect_temp = true;
3734 3734
3735 intel_crtc = to_intel_crtc(crtc); 3735 intel_crtc = to_intel_crtc(crtc);
3736 *dpms_mode = intel_crtc->dpms_mode; 3736 *dpms_mode = intel_crtc->dpms_mode;
@@ -3755,23 +3755,23 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3755 return crtc; 3755 return crtc;
3756} 3756}
3757 3757
3758void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) 3758void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpms_mode)
3759{ 3759{
3760 struct drm_encoder *encoder = &intel_output->enc; 3760 struct drm_encoder *encoder = &intel_encoder->enc;
3761 struct drm_device *dev = encoder->dev; 3761 struct drm_device *dev = encoder->dev;
3762 struct drm_crtc *crtc = encoder->crtc; 3762 struct drm_crtc *crtc = encoder->crtc;
3763 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3763 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3764 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 3764 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3765 3765
3766 if (intel_output->load_detect_temp) { 3766 if (intel_encoder->load_detect_temp) {
3767 encoder->crtc = NULL; 3767 encoder->crtc = NULL;
3768 intel_output->base.encoder = NULL; 3768 intel_encoder->base.encoder = NULL;
3769 intel_output->load_detect_temp = false; 3769 intel_encoder->load_detect_temp = false;
3770 crtc->enabled = drm_helper_crtc_in_use(crtc); 3770 crtc->enabled = drm_helper_crtc_in_use(crtc);
3771 drm_helper_disable_unused_functions(dev); 3771 drm_helper_disable_unused_functions(dev);
3772 } 3772 }
3773 3773
3774 /* Switch crtc and output back off if necessary */ 3774 /* Switch crtc and encoder back off if necessary */
3775 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { 3775 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3776 if (encoder->crtc == crtc) 3776 if (encoder->crtc == crtc)
3777 encoder_funcs->dpms(encoder, dpms_mode); 3777 encoder_funcs->dpms(encoder, dpms_mode);
@@ -4156,7 +4156,7 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
4156 work = intel_crtc->unpin_work; 4156 work = intel_crtc->unpin_work;
4157 if (work == NULL || !work->pending) { 4157 if (work == NULL || !work->pending) {
4158 if (work && !work->pending) { 4158 if (work && !work->pending) {
4159 obj_priv = work->pending_flip_obj->driver_private; 4159 obj_priv = to_intel_bo(work->pending_flip_obj);
4160 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n", 4160 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4161 obj_priv, 4161 obj_priv,
4162 atomic_read(&obj_priv->pending_flip)); 4162 atomic_read(&obj_priv->pending_flip));
@@ -4181,7 +4181,7 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
4181 4181
4182 spin_unlock_irqrestore(&dev->event_lock, flags); 4182 spin_unlock_irqrestore(&dev->event_lock, flags);
4183 4183
4184 obj_priv = work->pending_flip_obj->driver_private; 4184 obj_priv = to_intel_bo(work->pending_flip_obj);
4185 4185
4186 /* Initial scanout buffer will have a 0 pending flip count */ 4186 /* Initial scanout buffer will have a 0 pending flip count */
4187 if ((atomic_read(&obj_priv->pending_flip) == 0) || 4187 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
@@ -4252,7 +4252,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4252 ret = intel_pin_and_fence_fb_obj(dev, obj); 4252 ret = intel_pin_and_fence_fb_obj(dev, obj);
4253 if (ret != 0) { 4253 if (ret != 0) {
4254 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n", 4254 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4255 obj->driver_private); 4255 to_intel_bo(obj));
4256 kfree(work); 4256 kfree(work);
4257 intel_crtc->unpin_work = NULL; 4257 intel_crtc->unpin_work = NULL;
4258 mutex_unlock(&dev->struct_mutex); 4258 mutex_unlock(&dev->struct_mutex);
@@ -4266,7 +4266,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4266 crtc->fb = fb; 4266 crtc->fb = fb;
4267 i915_gem_object_flush_write_domain(obj); 4267 i915_gem_object_flush_write_domain(obj);
4268 drm_vblank_get(dev, intel_crtc->pipe); 4268 drm_vblank_get(dev, intel_crtc->pipe);
4269 obj_priv = obj->driver_private; 4269 obj_priv = to_intel_bo(obj);
4270 atomic_inc(&obj_priv->pending_flip); 4270 atomic_inc(&obj_priv->pending_flip);
4271 work->pending_flip_obj = obj; 4271 work->pending_flip_obj = obj;
4272 4272
@@ -4399,8 +4399,8 @@ static int intel_connector_clones(struct drm_device *dev, int type_mask)
4399 int entry = 0; 4399 int entry = 0;
4400 4400
4401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4402 struct intel_output *intel_output = to_intel_output(connector); 4402 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4403 if (type_mask & intel_output->clone_mask) 4403 if (type_mask & intel_encoder->clone_mask)
4404 index_mask |= (1 << entry); 4404 index_mask |= (1 << entry);
4405 entry++; 4405 entry++;
4406 } 4406 }
@@ -4495,12 +4495,12 @@ static void intel_setup_outputs(struct drm_device *dev)
4495 intel_tv_init(dev); 4495 intel_tv_init(dev);
4496 4496
4497 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4497 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4498 struct intel_output *intel_output = to_intel_output(connector); 4498 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4499 struct drm_encoder *encoder = &intel_output->enc; 4499 struct drm_encoder *encoder = &intel_encoder->enc;
4500 4500
4501 encoder->possible_crtcs = intel_output->crtc_mask; 4501 encoder->possible_crtcs = intel_encoder->crtc_mask;
4502 encoder->possible_clones = intel_connector_clones(dev, 4502 encoder->possible_clones = intel_connector_clones(dev,
4503 intel_output->clone_mask); 4503 intel_encoder->clone_mask);
4504 } 4504 }
4505} 4505}
4506 4506
@@ -4779,14 +4779,14 @@ void intel_init_clock_gating(struct drm_device *dev)
4779 struct drm_i915_gem_object *obj_priv = NULL; 4779 struct drm_i915_gem_object *obj_priv = NULL;
4780 4780
4781 if (dev_priv->pwrctx) { 4781 if (dev_priv->pwrctx) {
4782 obj_priv = dev_priv->pwrctx->driver_private; 4782 obj_priv = to_intel_bo(dev_priv->pwrctx);
4783 } else { 4783 } else {
4784 struct drm_gem_object *pwrctx; 4784 struct drm_gem_object *pwrctx;
4785 4785
4786 pwrctx = intel_alloc_power_context(dev); 4786 pwrctx = intel_alloc_power_context(dev);
4787 if (pwrctx) { 4787 if (pwrctx) {
4788 dev_priv->pwrctx = pwrctx; 4788 dev_priv->pwrctx = pwrctx;
4789 obj_priv = pwrctx->driver_private; 4789 obj_priv = to_intel_bo(pwrctx);
4790 } 4790 }
4791 } 4791 }
4792 4792
@@ -4815,7 +4815,7 @@ static void intel_init_display(struct drm_device *dev)
4815 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 4815 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4816 dev_priv->display.enable_fbc = g4x_enable_fbc; 4816 dev_priv->display.enable_fbc = g4x_enable_fbc;
4817 dev_priv->display.disable_fbc = g4x_disable_fbc; 4817 dev_priv->display.disable_fbc = g4x_disable_fbc;
4818 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) { 4818 } else if (IS_I965GM(dev)) {
4819 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; 4819 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4820 dev_priv->display.enable_fbc = i8xx_enable_fbc; 4820 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4821 dev_priv->display.disable_fbc = i8xx_disable_fbc; 4821 dev_priv->display.disable_fbc = i8xx_disable_fbc;
@@ -4853,17 +4853,18 @@ static void intel_init_display(struct drm_device *dev)
4853 dev_priv->display.update_wm = g4x_update_wm; 4853 dev_priv->display.update_wm = g4x_update_wm;
4854 else if (IS_I965G(dev)) 4854 else if (IS_I965G(dev))
4855 dev_priv->display.update_wm = i965_update_wm; 4855 dev_priv->display.update_wm = i965_update_wm;
4856 else if (IS_I9XX(dev) || IS_MOBILE(dev)) { 4856 else if (IS_I9XX(dev)) {
4857 dev_priv->display.update_wm = i9xx_update_wm; 4857 dev_priv->display.update_wm = i9xx_update_wm;
4858 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 4858 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4859 } else if (IS_I85X(dev)) {
4860 dev_priv->display.update_wm = i9xx_update_wm;
4861 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4859 } else { 4862 } else {
4860 if (IS_I85X(dev)) 4863 dev_priv->display.update_wm = i830_update_wm;
4861 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 4864 if (IS_845G(dev))
4862 else if (IS_845G(dev))
4863 dev_priv->display.get_fifo_size = i845_get_fifo_size; 4865 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4864 else 4866 else
4865 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4867 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4866 dev_priv->display.update_wm = i830_update_wm;
4867 } 4868 }
4868} 4869}
4869 4870
@@ -4957,7 +4958,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
4957 if (dev_priv->pwrctx) { 4958 if (dev_priv->pwrctx) {
4958 struct drm_i915_gem_object *obj_priv; 4959 struct drm_i915_gem_object *obj_priv;
4959 4960
4960 obj_priv = dev_priv->pwrctx->driver_private; 4961 obj_priv = to_intel_bo(dev_priv->pwrctx);
4961 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN); 4962 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4962 I915_READ(PWRCTXA); 4963 I915_READ(PWRCTXA);
4963 i915_gem_object_unpin(dev_priv->pwrctx); 4964 i915_gem_object_unpin(dev_priv->pwrctx);
@@ -4978,9 +4979,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
4978*/ 4979*/
4979struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 4980struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4980{ 4981{
4981 struct intel_output *intel_output = to_intel_output(connector); 4982 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4982 4983
4983 return &intel_output->enc; 4984 return &intel_encoder->enc;
4984} 4985}
4985 4986
4986/* 4987/*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8e283f75941d..77e40cfcf216 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -55,23 +55,23 @@ struct intel_dp_priv {
55 uint8_t link_bw; 55 uint8_t link_bw;
56 uint8_t lane_count; 56 uint8_t lane_count;
57 uint8_t dpcd[4]; 57 uint8_t dpcd[4];
58 struct intel_output *intel_output; 58 struct intel_encoder *intel_encoder;
59 struct i2c_adapter adapter; 59 struct i2c_adapter adapter;
60 struct i2c_algo_dp_aux_data algo; 60 struct i2c_algo_dp_aux_data algo;
61}; 61};
62 62
63static void 63static void
64intel_dp_link_train(struct intel_output *intel_output, uint32_t DP, 64intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]); 65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
66 66
67static void 67static void
68intel_dp_link_down(struct intel_output *intel_output, uint32_t DP); 68intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
69 69
70void 70void
71intel_edp_link_config (struct intel_output *intel_output, 71intel_edp_link_config (struct intel_encoder *intel_encoder,
72 int *lane_num, int *link_bw) 72 int *lane_num, int *link_bw)
73{ 73{
74 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 74 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
75 75
76 *lane_num = dp_priv->lane_count; 76 *lane_num = dp_priv->lane_count;
77 if (dp_priv->link_bw == DP_LINK_BW_1_62) 77 if (dp_priv->link_bw == DP_LINK_BW_1_62)
@@ -81,9 +81,9 @@ intel_edp_link_config (struct intel_output *intel_output,
81} 81}
82 82
83static int 83static int
84intel_dp_max_lane_count(struct intel_output *intel_output) 84intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
85{ 85{
86 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 86 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
87 int max_lane_count = 4; 87 int max_lane_count = 4;
88 88
89 if (dp_priv->dpcd[0] >= 0x11) { 89 if (dp_priv->dpcd[0] >= 0x11) {
@@ -99,9 +99,9 @@ intel_dp_max_lane_count(struct intel_output *intel_output)
99} 99}
100 100
101static int 101static int
102intel_dp_max_link_bw(struct intel_output *intel_output) 102intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
103{ 103{
104 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 104 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
105 int max_link_bw = dp_priv->dpcd[1]; 105 int max_link_bw = dp_priv->dpcd[1];
106 106
107 switch (max_link_bw) { 107 switch (max_link_bw) {
@@ -127,11 +127,11 @@ intel_dp_link_clock(uint8_t link_bw)
127/* I think this is a fiction */ 127/* I think this is a fiction */
128static int 128static int
129intel_dp_link_required(struct drm_device *dev, 129intel_dp_link_required(struct drm_device *dev,
130 struct intel_output *intel_output, int pixel_clock) 130 struct intel_encoder *intel_encoder, int pixel_clock)
131{ 131{
132 struct drm_i915_private *dev_priv = dev->dev_private; 132 struct drm_i915_private *dev_priv = dev->dev_private;
133 133
134 if (IS_eDP(intel_output)) 134 if (IS_eDP(intel_encoder))
135 return (pixel_clock * dev_priv->edp_bpp) / 8; 135 return (pixel_clock * dev_priv->edp_bpp) / 8;
136 else 136 else
137 return pixel_clock * 3; 137 return pixel_clock * 3;
@@ -141,11 +141,11 @@ static int
141intel_dp_mode_valid(struct drm_connector *connector, 141intel_dp_mode_valid(struct drm_connector *connector,
142 struct drm_display_mode *mode) 142 struct drm_display_mode *mode)
143{ 143{
144 struct intel_output *intel_output = to_intel_output(connector); 144 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
145 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output)); 145 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
146 int max_lanes = intel_dp_max_lane_count(intel_output); 146 int max_lanes = intel_dp_max_lane_count(intel_encoder);
147 147
148 if (intel_dp_link_required(connector->dev, intel_output, mode->clock) 148 if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
149 > max_link_clock * max_lanes) 149 > max_link_clock * max_lanes)
150 return MODE_CLOCK_HIGH; 150 return MODE_CLOCK_HIGH;
151 151
@@ -209,13 +209,13 @@ intel_hrawclk(struct drm_device *dev)
209} 209}
210 210
211static int 211static int
212intel_dp_aux_ch(struct intel_output *intel_output, 212intel_dp_aux_ch(struct intel_encoder *intel_encoder,
213 uint8_t *send, int send_bytes, 213 uint8_t *send, int send_bytes,
214 uint8_t *recv, int recv_size) 214 uint8_t *recv, int recv_size)
215{ 215{
216 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 216 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
217 uint32_t output_reg = dp_priv->output_reg; 217 uint32_t output_reg = dp_priv->output_reg;
218 struct drm_device *dev = intel_output->base.dev; 218 struct drm_device *dev = intel_encoder->base.dev;
219 struct drm_i915_private *dev_priv = dev->dev_private; 219 struct drm_i915_private *dev_priv = dev->dev_private;
220 uint32_t ch_ctl = output_reg + 0x10; 220 uint32_t ch_ctl = output_reg + 0x10;
221 uint32_t ch_data = ch_ctl + 4; 221 uint32_t ch_data = ch_ctl + 4;
@@ -230,7 +230,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
230 * and would like to run at 2MHz. So, take the 230 * and would like to run at 2MHz. So, take the
231 * hrawclk value and divide by 2 and use that 231 * hrawclk value and divide by 2 and use that
232 */ 232 */
233 if (IS_eDP(intel_output)) 233 if (IS_eDP(intel_encoder))
234 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 234 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
235 else if (HAS_PCH_SPLIT(dev)) 235 else if (HAS_PCH_SPLIT(dev))
236 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ 236 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
@@ -313,7 +313,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
313 313
314/* Write data to the aux channel in native mode */ 314/* Write data to the aux channel in native mode */
315static int 315static int
316intel_dp_aux_native_write(struct intel_output *intel_output, 316intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
317 uint16_t address, uint8_t *send, int send_bytes) 317 uint16_t address, uint8_t *send, int send_bytes)
318{ 318{
319 int ret; 319 int ret;
@@ -330,7 +330,7 @@ intel_dp_aux_native_write(struct intel_output *intel_output,
330 memcpy(&msg[4], send, send_bytes); 330 memcpy(&msg[4], send, send_bytes);
331 msg_bytes = send_bytes + 4; 331 msg_bytes = send_bytes + 4;
332 for (;;) { 332 for (;;) {
333 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1); 333 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
334 if (ret < 0) 334 if (ret < 0)
335 return ret; 335 return ret;
336 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 336 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
@@ -345,15 +345,15 @@ intel_dp_aux_native_write(struct intel_output *intel_output,
345 345
346/* Write a single byte to the aux channel in native mode */ 346/* Write a single byte to the aux channel in native mode */
347static int 347static int
348intel_dp_aux_native_write_1(struct intel_output *intel_output, 348intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
349 uint16_t address, uint8_t byte) 349 uint16_t address, uint8_t byte)
350{ 350{
351 return intel_dp_aux_native_write(intel_output, address, &byte, 1); 351 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
352} 352}
353 353
354/* read bytes from a native aux channel */ 354/* read bytes from a native aux channel */
355static int 355static int
356intel_dp_aux_native_read(struct intel_output *intel_output, 356intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
357 uint16_t address, uint8_t *recv, int recv_bytes) 357 uint16_t address, uint8_t *recv, int recv_bytes)
358{ 358{
359 uint8_t msg[4]; 359 uint8_t msg[4];
@@ -372,7 +372,7 @@ intel_dp_aux_native_read(struct intel_output *intel_output,
372 reply_bytes = recv_bytes + 1; 372 reply_bytes = recv_bytes + 1;
373 373
374 for (;;) { 374 for (;;) {
375 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, 375 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
376 reply, reply_bytes); 376 reply, reply_bytes);
377 if (ret == 0) 377 if (ret == 0)
378 return -EPROTO; 378 return -EPROTO;
@@ -398,7 +398,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
398 struct intel_dp_priv *dp_priv = container_of(adapter, 398 struct intel_dp_priv *dp_priv = container_of(adapter,
399 struct intel_dp_priv, 399 struct intel_dp_priv,
400 adapter); 400 adapter);
401 struct intel_output *intel_output = dp_priv->intel_output; 401 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
402 uint16_t address = algo_data->address; 402 uint16_t address = algo_data->address;
403 uint8_t msg[5]; 403 uint8_t msg[5];
404 uint8_t reply[2]; 404 uint8_t reply[2];
@@ -437,7 +437,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
437 } 437 }
438 438
439 for (;;) { 439 for (;;) {
440 ret = intel_dp_aux_ch(intel_output, 440 ret = intel_dp_aux_ch(intel_encoder,
441 msg, msg_bytes, 441 msg, msg_bytes,
442 reply, reply_bytes); 442 reply, reply_bytes);
443 if (ret < 0) { 443 if (ret < 0) {
@@ -465,9 +465,9 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
465} 465}
466 466
467static int 467static int
468intel_dp_i2c_init(struct intel_output *intel_output, const char *name) 468intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name)
469{ 469{
470 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 470 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
471 471
472 DRM_DEBUG_KMS("i2c_init %s\n", name); 472 DRM_DEBUG_KMS("i2c_init %s\n", name);
473 dp_priv->algo.running = false; 473 dp_priv->algo.running = false;
@@ -480,7 +480,7 @@ intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
480 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); 480 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
481 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; 481 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
482 dp_priv->adapter.algo_data = &dp_priv->algo; 482 dp_priv->adapter.algo_data = &dp_priv->algo;
483 dp_priv->adapter.dev.parent = &intel_output->base.kdev; 483 dp_priv->adapter.dev.parent = &intel_encoder->base.kdev;
484 484
485 return i2c_dp_aux_add_bus(&dp_priv->adapter); 485 return i2c_dp_aux_add_bus(&dp_priv->adapter);
486} 486}
@@ -489,18 +489,18 @@ static bool
489intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 489intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
490 struct drm_display_mode *adjusted_mode) 490 struct drm_display_mode *adjusted_mode)
491{ 491{
492 struct intel_output *intel_output = enc_to_intel_output(encoder); 492 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
493 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 493 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
494 int lane_count, clock; 494 int lane_count, clock;
495 int max_lane_count = intel_dp_max_lane_count(intel_output); 495 int max_lane_count = intel_dp_max_lane_count(intel_encoder);
496 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0; 496 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
497 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 497 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
498 498
499 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 499 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
500 for (clock = 0; clock <= max_clock; clock++) { 500 for (clock = 0; clock <= max_clock; clock++) {
501 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count; 501 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
502 502
503 if (intel_dp_link_required(encoder->dev, intel_output, mode->clock) 503 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
504 <= link_avail) { 504 <= link_avail) {
505 dp_priv->link_bw = bws[clock]; 505 dp_priv->link_bw = bws[clock];
506 dp_priv->lane_count = lane_count; 506 dp_priv->lane_count = lane_count;
@@ -562,16 +562,16 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
562 struct intel_dp_m_n m_n; 562 struct intel_dp_m_n m_n;
563 563
564 /* 564 /*
565 * Find the lane count in the intel_output private 565 * Find the lane count in the intel_encoder private
566 */ 566 */
567 list_for_each_entry(connector, &mode_config->connector_list, head) { 567 list_for_each_entry(connector, &mode_config->connector_list, head) {
568 struct intel_output *intel_output = to_intel_output(connector); 568 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
569 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 569 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
570 570
571 if (!connector->encoder || connector->encoder->crtc != crtc) 571 if (!connector->encoder || connector->encoder->crtc != crtc)
572 continue; 572 continue;
573 573
574 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) { 574 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
575 lane_count = dp_priv->lane_count; 575 lane_count = dp_priv->lane_count;
576 break; 576 break;
577 } 577 }
@@ -626,9 +626,9 @@ static void
626intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 626intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
627 struct drm_display_mode *adjusted_mode) 627 struct drm_display_mode *adjusted_mode)
628{ 628{
629 struct intel_output *intel_output = enc_to_intel_output(encoder); 629 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
630 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 630 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
631 struct drm_crtc *crtc = intel_output->enc.crtc; 631 struct drm_crtc *crtc = intel_encoder->enc.crtc;
632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
633 633
634 dp_priv->DP = (DP_LINK_TRAIN_OFF | 634 dp_priv->DP = (DP_LINK_TRAIN_OFF |
@@ -667,7 +667,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
667 if (intel_crtc->pipe == 1) 667 if (intel_crtc->pipe == 1)
668 dp_priv->DP |= DP_PIPEB_SELECT; 668 dp_priv->DP |= DP_PIPEB_SELECT;
669 669
670 if (IS_eDP(intel_output)) { 670 if (IS_eDP(intel_encoder)) {
671 /* don't miss out required setting for eDP */ 671 /* don't miss out required setting for eDP */
672 dp_priv->DP |= DP_PLL_ENABLE; 672 dp_priv->DP |= DP_PLL_ENABLE;
673 if (adjusted_mode->clock < 200000) 673 if (adjusted_mode->clock < 200000)
@@ -702,22 +702,22 @@ static void ironlake_edp_backlight_off (struct drm_device *dev)
702static void 702static void
703intel_dp_dpms(struct drm_encoder *encoder, int mode) 703intel_dp_dpms(struct drm_encoder *encoder, int mode)
704{ 704{
705 struct intel_output *intel_output = enc_to_intel_output(encoder); 705 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
706 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 706 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
707 struct drm_device *dev = intel_output->base.dev; 707 struct drm_device *dev = intel_encoder->base.dev;
708 struct drm_i915_private *dev_priv = dev->dev_private; 708 struct drm_i915_private *dev_priv = dev->dev_private;
709 uint32_t dp_reg = I915_READ(dp_priv->output_reg); 709 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
710 710
711 if (mode != DRM_MODE_DPMS_ON) { 711 if (mode != DRM_MODE_DPMS_ON) {
712 if (dp_reg & DP_PORT_EN) { 712 if (dp_reg & DP_PORT_EN) {
713 intel_dp_link_down(intel_output, dp_priv->DP); 713 intel_dp_link_down(intel_encoder, dp_priv->DP);
714 if (IS_eDP(intel_output)) 714 if (IS_eDP(intel_encoder))
715 ironlake_edp_backlight_off(dev); 715 ironlake_edp_backlight_off(dev);
716 } 716 }
717 } else { 717 } else {
718 if (!(dp_reg & DP_PORT_EN)) { 718 if (!(dp_reg & DP_PORT_EN)) {
719 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); 719 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
720 if (IS_eDP(intel_output)) 720 if (IS_eDP(intel_encoder))
721 ironlake_edp_backlight_on(dev); 721 ironlake_edp_backlight_on(dev);
722 } 722 }
723 } 723 }
@@ -729,12 +729,12 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
729 * link status information 729 * link status information
730 */ 730 */
731static bool 731static bool
732intel_dp_get_link_status(struct intel_output *intel_output, 732intel_dp_get_link_status(struct intel_encoder *intel_encoder,
733 uint8_t link_status[DP_LINK_STATUS_SIZE]) 733 uint8_t link_status[DP_LINK_STATUS_SIZE])
734{ 734{
735 int ret; 735 int ret;
736 736
737 ret = intel_dp_aux_native_read(intel_output, 737 ret = intel_dp_aux_native_read(intel_encoder,
738 DP_LANE0_1_STATUS, 738 DP_LANE0_1_STATUS,
739 link_status, DP_LINK_STATUS_SIZE); 739 link_status, DP_LINK_STATUS_SIZE);
740 if (ret != DP_LINK_STATUS_SIZE) 740 if (ret != DP_LINK_STATUS_SIZE)
@@ -752,13 +752,13 @@ intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
752static void 752static void
753intel_dp_save(struct drm_connector *connector) 753intel_dp_save(struct drm_connector *connector)
754{ 754{
755 struct intel_output *intel_output = to_intel_output(connector); 755 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
756 struct drm_device *dev = intel_output->base.dev; 756 struct drm_device *dev = intel_encoder->base.dev;
757 struct drm_i915_private *dev_priv = dev->dev_private; 757 struct drm_i915_private *dev_priv = dev->dev_private;
758 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 758 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
759 759
760 dp_priv->save_DP = I915_READ(dp_priv->output_reg); 760 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
761 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET, 761 intel_dp_aux_native_read(intel_encoder, DP_LINK_BW_SET,
762 dp_priv->save_link_configuration, 762 dp_priv->save_link_configuration,
763 sizeof (dp_priv->save_link_configuration)); 763 sizeof (dp_priv->save_link_configuration));
764} 764}
@@ -825,7 +825,7 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
825} 825}
826 826
827static void 827static void
828intel_get_adjust_train(struct intel_output *intel_output, 828intel_get_adjust_train(struct intel_encoder *intel_encoder,
829 uint8_t link_status[DP_LINK_STATUS_SIZE], 829 uint8_t link_status[DP_LINK_STATUS_SIZE],
830 int lane_count, 830 int lane_count,
831 uint8_t train_set[4]) 831 uint8_t train_set[4])
@@ -942,15 +942,15 @@ intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
942} 942}
943 943
944static bool 944static bool
945intel_dp_set_link_train(struct intel_output *intel_output, 945intel_dp_set_link_train(struct intel_encoder *intel_encoder,
946 uint32_t dp_reg_value, 946 uint32_t dp_reg_value,
947 uint8_t dp_train_pat, 947 uint8_t dp_train_pat,
948 uint8_t train_set[4], 948 uint8_t train_set[4],
949 bool first) 949 bool first)
950{ 950{
951 struct drm_device *dev = intel_output->base.dev; 951 struct drm_device *dev = intel_encoder->base.dev;
952 struct drm_i915_private *dev_priv = dev->dev_private; 952 struct drm_i915_private *dev_priv = dev->dev_private;
953 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 953 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
954 int ret; 954 int ret;
955 955
956 I915_WRITE(dp_priv->output_reg, dp_reg_value); 956 I915_WRITE(dp_priv->output_reg, dp_reg_value);
@@ -958,11 +958,11 @@ intel_dp_set_link_train(struct intel_output *intel_output,
958 if (first) 958 if (first)
959 intel_wait_for_vblank(dev); 959 intel_wait_for_vblank(dev);
960 960
961 intel_dp_aux_native_write_1(intel_output, 961 intel_dp_aux_native_write_1(intel_encoder,
962 DP_TRAINING_PATTERN_SET, 962 DP_TRAINING_PATTERN_SET,
963 dp_train_pat); 963 dp_train_pat);
964 964
965 ret = intel_dp_aux_native_write(intel_output, 965 ret = intel_dp_aux_native_write(intel_encoder,
966 DP_TRAINING_LANE0_SET, train_set, 4); 966 DP_TRAINING_LANE0_SET, train_set, 4);
967 if (ret != 4) 967 if (ret != 4)
968 return false; 968 return false;
@@ -971,12 +971,12 @@ intel_dp_set_link_train(struct intel_output *intel_output,
971} 971}
972 972
973static void 973static void
974intel_dp_link_train(struct intel_output *intel_output, uint32_t DP, 974intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
975 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]) 975 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
976{ 976{
977 struct drm_device *dev = intel_output->base.dev; 977 struct drm_device *dev = intel_encoder->base.dev;
978 struct drm_i915_private *dev_priv = dev->dev_private; 978 struct drm_i915_private *dev_priv = dev->dev_private;
979 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 979 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
980 uint8_t train_set[4]; 980 uint8_t train_set[4];
981 uint8_t link_status[DP_LINK_STATUS_SIZE]; 981 uint8_t link_status[DP_LINK_STATUS_SIZE];
982 int i; 982 int i;
@@ -987,7 +987,7 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
987 int tries; 987 int tries;
988 988
989 /* Write the link configuration data */ 989 /* Write the link configuration data */
990 intel_dp_aux_native_write(intel_output, 0x100, 990 intel_dp_aux_native_write(intel_encoder, 0x100,
991 link_configuration, DP_LINK_CONFIGURATION_SIZE); 991 link_configuration, DP_LINK_CONFIGURATION_SIZE);
992 992
993 DP |= DP_PORT_EN; 993 DP |= DP_PORT_EN;
@@ -1001,14 +1001,14 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
1001 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1001 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1002 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1002 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1003 1003
1004 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1, 1004 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_1,
1005 DP_TRAINING_PATTERN_1, train_set, first)) 1005 DP_TRAINING_PATTERN_1, train_set, first))
1006 break; 1006 break;
1007 first = false; 1007 first = false;
1008 /* Set training pattern 1 */ 1008 /* Set training pattern 1 */
1009 1009
1010 udelay(100); 1010 udelay(100);
1011 if (!intel_dp_get_link_status(intel_output, link_status)) 1011 if (!intel_dp_get_link_status(intel_encoder, link_status))
1012 break; 1012 break;
1013 1013
1014 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) { 1014 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
@@ -1033,7 +1033,7 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
1033 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1033 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1034 1034
1035 /* Compute new train_set as requested by target */ 1035 /* Compute new train_set as requested by target */
1036 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set); 1036 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1037 } 1037 }
1038 1038
1039 /* channel equalization */ 1039 /* channel equalization */
@@ -1045,13 +1045,13 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
1045 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1045 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1046 1046
1047 /* channel eq pattern */ 1047 /* channel eq pattern */
1048 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2, 1048 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_2,
1049 DP_TRAINING_PATTERN_2, train_set, 1049 DP_TRAINING_PATTERN_2, train_set,
1050 false)) 1050 false))
1051 break; 1051 break;
1052 1052
1053 udelay(400); 1053 udelay(400);
1054 if (!intel_dp_get_link_status(intel_output, link_status)) 1054 if (!intel_dp_get_link_status(intel_encoder, link_status))
1055 break; 1055 break;
1056 1056
1057 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) { 1057 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
@@ -1064,26 +1064,26 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
1064 break; 1064 break;
1065 1065
1066 /* Compute new train_set as requested by target */ 1066 /* Compute new train_set as requested by target */
1067 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set); 1067 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1068 ++tries; 1068 ++tries;
1069 } 1069 }
1070 1070
1071 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF); 1071 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1072 POSTING_READ(dp_priv->output_reg); 1072 POSTING_READ(dp_priv->output_reg);
1073 intel_dp_aux_native_write_1(intel_output, 1073 intel_dp_aux_native_write_1(intel_encoder,
1074 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1074 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1075} 1075}
1076 1076
1077static void 1077static void
1078intel_dp_link_down(struct intel_output *intel_output, uint32_t DP) 1078intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1079{ 1079{
1080 struct drm_device *dev = intel_output->base.dev; 1080 struct drm_device *dev = intel_encoder->base.dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private; 1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1082 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1083 1083
1084 DRM_DEBUG_KMS("\n"); 1084 DRM_DEBUG_KMS("\n");
1085 1085
1086 if (IS_eDP(intel_output)) { 1086 if (IS_eDP(intel_encoder)) {
1087 DP &= ~DP_PLL_ENABLE; 1087 DP &= ~DP_PLL_ENABLE;
1088 I915_WRITE(dp_priv->output_reg, DP); 1088 I915_WRITE(dp_priv->output_reg, DP);
1089 POSTING_READ(dp_priv->output_reg); 1089 POSTING_READ(dp_priv->output_reg);
@@ -1096,7 +1096,7 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1096 1096
1097 udelay(17000); 1097 udelay(17000);
1098 1098
1099 if (IS_eDP(intel_output)) 1099 if (IS_eDP(intel_encoder))
1100 DP |= DP_LINK_TRAIN_OFF; 1100 DP |= DP_LINK_TRAIN_OFF;
1101 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN); 1101 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1102 POSTING_READ(dp_priv->output_reg); 1102 POSTING_READ(dp_priv->output_reg);
@@ -1105,13 +1105,13 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1105static void 1105static void
1106intel_dp_restore(struct drm_connector *connector) 1106intel_dp_restore(struct drm_connector *connector)
1107{ 1107{
1108 struct intel_output *intel_output = to_intel_output(connector); 1108 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1109 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1109 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1110 1110
1111 if (dp_priv->save_DP & DP_PORT_EN) 1111 if (dp_priv->save_DP & DP_PORT_EN)
1112 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration); 1112 intel_dp_link_train(intel_encoder, dp_priv->save_DP, dp_priv->save_link_configuration);
1113 else 1113 else
1114 intel_dp_link_down(intel_output, dp_priv->save_DP); 1114 intel_dp_link_down(intel_encoder, dp_priv->save_DP);
1115} 1115}
1116 1116
1117/* 1117/*
@@ -1124,32 +1124,32 @@ intel_dp_restore(struct drm_connector *connector)
1124 */ 1124 */
1125 1125
1126static void 1126static void
1127intel_dp_check_link_status(struct intel_output *intel_output) 1127intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1128{ 1128{
1129 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1129 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1130 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1130 uint8_t link_status[DP_LINK_STATUS_SIZE];
1131 1131
1132 if (!intel_output->enc.crtc) 1132 if (!intel_encoder->enc.crtc)
1133 return; 1133 return;
1134 1134
1135 if (!intel_dp_get_link_status(intel_output, link_status)) { 1135 if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1136 intel_dp_link_down(intel_output, dp_priv->DP); 1136 intel_dp_link_down(intel_encoder, dp_priv->DP);
1137 return; 1137 return;
1138 } 1138 }
1139 1139
1140 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count)) 1140 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1141 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); 1141 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1142} 1142}
1143 1143
1144static enum drm_connector_status 1144static enum drm_connector_status
1145ironlake_dp_detect(struct drm_connector *connector) 1145ironlake_dp_detect(struct drm_connector *connector)
1146{ 1146{
1147 struct intel_output *intel_output = to_intel_output(connector); 1147 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1148 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1148 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1149 enum drm_connector_status status; 1149 enum drm_connector_status status;
1150 1150
1151 status = connector_status_disconnected; 1151 status = connector_status_disconnected;
1152 if (intel_dp_aux_native_read(intel_output, 1152 if (intel_dp_aux_native_read(intel_encoder,
1153 0x000, dp_priv->dpcd, 1153 0x000, dp_priv->dpcd,
1154 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1154 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1155 { 1155 {
@@ -1168,10 +1168,10 @@ ironlake_dp_detect(struct drm_connector *connector)
1168static enum drm_connector_status 1168static enum drm_connector_status
1169intel_dp_detect(struct drm_connector *connector) 1169intel_dp_detect(struct drm_connector *connector)
1170{ 1170{
1171 struct intel_output *intel_output = to_intel_output(connector); 1171 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1172 struct drm_device *dev = intel_output->base.dev; 1172 struct drm_device *dev = intel_encoder->base.dev;
1173 struct drm_i915_private *dev_priv = dev->dev_private; 1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1174 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1175 uint32_t temp, bit; 1175 uint32_t temp, bit;
1176 enum drm_connector_status status; 1176 enum drm_connector_status status;
1177 1177
@@ -1210,7 +1210,7 @@ intel_dp_detect(struct drm_connector *connector)
1210 return connector_status_disconnected; 1210 return connector_status_disconnected;
1211 1211
1212 status = connector_status_disconnected; 1212 status = connector_status_disconnected;
1213 if (intel_dp_aux_native_read(intel_output, 1213 if (intel_dp_aux_native_read(intel_encoder,
1214 0x000, dp_priv->dpcd, 1214 0x000, dp_priv->dpcd,
1215 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1215 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1216 { 1216 {
@@ -1222,20 +1222,20 @@ intel_dp_detect(struct drm_connector *connector)
1222 1222
1223static int intel_dp_get_modes(struct drm_connector *connector) 1223static int intel_dp_get_modes(struct drm_connector *connector)
1224{ 1224{
1225 struct intel_output *intel_output = to_intel_output(connector); 1225 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1226 struct drm_device *dev = intel_output->base.dev; 1226 struct drm_device *dev = intel_encoder->base.dev;
1227 struct drm_i915_private *dev_priv = dev->dev_private; 1227 struct drm_i915_private *dev_priv = dev->dev_private;
1228 int ret; 1228 int ret;
1229 1229
1230 /* We should parse the EDID data and find out if it has an audio sink 1230 /* We should parse the EDID data and find out if it has an audio sink
1231 */ 1231 */
1232 1232
1233 ret = intel_ddc_get_modes(intel_output); 1233 ret = intel_ddc_get_modes(intel_encoder);
1234 if (ret) 1234 if (ret)
1235 return ret; 1235 return ret;
1236 1236
1237 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1237 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1238 if (IS_eDP(intel_output)) { 1238 if (IS_eDP(intel_encoder)) {
1239 if (dev_priv->panel_fixed_mode != NULL) { 1239 if (dev_priv->panel_fixed_mode != NULL) {
1240 struct drm_display_mode *mode; 1240 struct drm_display_mode *mode;
1241 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1241 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
@@ -1249,13 +1249,13 @@ static int intel_dp_get_modes(struct drm_connector *connector)
1249static void 1249static void
1250intel_dp_destroy (struct drm_connector *connector) 1250intel_dp_destroy (struct drm_connector *connector)
1251{ 1251{
1252 struct intel_output *intel_output = to_intel_output(connector); 1252 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1253 1253
1254 if (intel_output->i2c_bus) 1254 if (intel_encoder->i2c_bus)
1255 intel_i2c_destroy(intel_output->i2c_bus); 1255 intel_i2c_destroy(intel_encoder->i2c_bus);
1256 drm_sysfs_connector_remove(connector); 1256 drm_sysfs_connector_remove(connector);
1257 drm_connector_cleanup(connector); 1257 drm_connector_cleanup(connector);
1258 kfree(intel_output); 1258 kfree(intel_encoder);
1259} 1259}
1260 1260
1261static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1261static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
@@ -1291,12 +1291,12 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1291}; 1291};
1292 1292
1293void 1293void
1294intel_dp_hot_plug(struct intel_output *intel_output) 1294intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1295{ 1295{
1296 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1296 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1297 1297
1298 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) 1298 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1299 intel_dp_check_link_status(intel_output); 1299 intel_dp_check_link_status(intel_encoder);
1300} 1300}
1301 1301
1302void 1302void
@@ -1304,53 +1304,53 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1304{ 1304{
1305 struct drm_i915_private *dev_priv = dev->dev_private; 1305 struct drm_i915_private *dev_priv = dev->dev_private;
1306 struct drm_connector *connector; 1306 struct drm_connector *connector;
1307 struct intel_output *intel_output; 1307 struct intel_encoder *intel_encoder;
1308 struct intel_dp_priv *dp_priv; 1308 struct intel_dp_priv *dp_priv;
1309 const char *name = NULL; 1309 const char *name = NULL;
1310 1310
1311 intel_output = kcalloc(sizeof(struct intel_output) + 1311 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1312 sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1312 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1313 if (!intel_output) 1313 if (!intel_encoder)
1314 return; 1314 return;
1315 1315
1316 dp_priv = (struct intel_dp_priv *)(intel_output + 1); 1316 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1317 1317
1318 connector = &intel_output->base; 1318 connector = &intel_encoder->base;
1319 drm_connector_init(dev, connector, &intel_dp_connector_funcs, 1319 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1320 DRM_MODE_CONNECTOR_DisplayPort); 1320 DRM_MODE_CONNECTOR_DisplayPort);
1321 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1321 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1322 1322
1323 if (output_reg == DP_A) 1323 if (output_reg == DP_A)
1324 intel_output->type = INTEL_OUTPUT_EDP; 1324 intel_encoder->type = INTEL_OUTPUT_EDP;
1325 else 1325 else
1326 intel_output->type = INTEL_OUTPUT_DISPLAYPORT; 1326 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1327 1327
1328 if (output_reg == DP_B || output_reg == PCH_DP_B) 1328 if (output_reg == DP_B || output_reg == PCH_DP_B)
1329 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 1329 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1330 else if (output_reg == DP_C || output_reg == PCH_DP_C) 1330 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1331 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 1331 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1332 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1332 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1333 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1333 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1334 1334
1335 if (IS_eDP(intel_output)) 1335 if (IS_eDP(intel_encoder))
1336 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1336 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1337 1337
1338 intel_output->crtc_mask = (1 << 0) | (1 << 1); 1338 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1339 connector->interlace_allowed = true; 1339 connector->interlace_allowed = true;
1340 connector->doublescan_allowed = 0; 1340 connector->doublescan_allowed = 0;
1341 1341
1342 dp_priv->intel_output = intel_output; 1342 dp_priv->intel_encoder = intel_encoder;
1343 dp_priv->output_reg = output_reg; 1343 dp_priv->output_reg = output_reg;
1344 dp_priv->has_audio = false; 1344 dp_priv->has_audio = false;
1345 dp_priv->dpms_mode = DRM_MODE_DPMS_ON; 1345 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1346 intel_output->dev_priv = dp_priv; 1346 intel_encoder->dev_priv = dp_priv;
1347 1347
1348 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs, 1348 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1349 DRM_MODE_ENCODER_TMDS); 1349 DRM_MODE_ENCODER_TMDS);
1350 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs); 1350 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1351 1351
1352 drm_mode_connector_attach_encoder(&intel_output->base, 1352 drm_mode_connector_attach_encoder(&intel_encoder->base,
1353 &intel_output->enc); 1353 &intel_encoder->enc);
1354 drm_sysfs_connector_add(connector); 1354 drm_sysfs_connector_add(connector);
1355 1355
1356 /* Set up the DDC bus. */ 1356 /* Set up the DDC bus. */
@@ -1378,10 +1378,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1378 break; 1378 break;
1379 } 1379 }
1380 1380
1381 intel_dp_i2c_init(intel_output, name); 1381 intel_dp_i2c_init(intel_encoder, name);
1382 1382
1383 intel_output->ddc_bus = &dp_priv->adapter; 1383 intel_encoder->ddc_bus = &dp_priv->adapter;
1384 intel_output->hot_plug = intel_dp_hot_plug; 1384 intel_encoder->hot_plug = intel_dp_hot_plug;
1385 1385
1386 if (output_reg == DP_A) { 1386 if (output_reg == DP_A) {
1387 /* initialize panel mode from VBT if available for eDP */ 1387 /* initialize panel mode from VBT if available for eDP */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3a467ca57857..e30253755f12 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -95,7 +95,7 @@ struct intel_framebuffer {
95}; 95};
96 96
97 97
98struct intel_output { 98struct intel_encoder {
99 struct drm_connector base; 99 struct drm_connector base;
100 100
101 struct drm_encoder enc; 101 struct drm_encoder enc;
@@ -105,7 +105,7 @@ struct intel_output {
105 bool load_detect_temp; 105 bool load_detect_temp;
106 bool needs_tv_clock; 106 bool needs_tv_clock;
107 void *dev_priv; 107 void *dev_priv;
108 void (*hot_plug)(struct intel_output *); 108 void (*hot_plug)(struct intel_encoder *);
109 int crtc_mask; 109 int crtc_mask;
110 int clone_mask; 110 int clone_mask;
111}; 111};
@@ -152,15 +152,15 @@ struct intel_crtc {
152}; 152};
153 153
154#define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 154#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
155#define to_intel_output(x) container_of(x, struct intel_output, base) 155#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
156#define enc_to_intel_output(x) container_of(x, struct intel_output, enc) 156#define enc_to_intel_encoder(x) container_of(x, struct intel_encoder, enc)
157#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 157#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
158 158
159struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg, 159struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
160 const char *name); 160 const char *name);
161void intel_i2c_destroy(struct i2c_adapter *adapter); 161void intel_i2c_destroy(struct i2c_adapter *adapter);
162int intel_ddc_get_modes(struct intel_output *intel_output); 162int intel_ddc_get_modes(struct intel_encoder *intel_encoder);
163extern bool intel_ddc_probe(struct intel_output *intel_output); 163extern bool intel_ddc_probe(struct intel_encoder *intel_encoder);
164void intel_i2c_quirk_set(struct drm_device *dev, bool enable); 164void intel_i2c_quirk_set(struct drm_device *dev, bool enable);
165void intel_i2c_reset_gmbus(struct drm_device *dev); 165void intel_i2c_reset_gmbus(struct drm_device *dev);
166 166
@@ -175,7 +175,7 @@ extern void intel_dp_init(struct drm_device *dev, int dp_reg);
175void 175void
176intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 176intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
177 struct drm_display_mode *adjusted_mode); 177 struct drm_display_mode *adjusted_mode);
178extern void intel_edp_link_config (struct intel_output *, int *, int *); 178extern void intel_edp_link_config (struct intel_encoder *, int *, int *);
179 179
180 180
181extern int intel_panel_fitter_pipe (struct drm_device *dev); 181extern int intel_panel_fitter_pipe (struct drm_device *dev);
@@ -191,10 +191,10 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
191 struct drm_file *file_priv); 191 struct drm_file *file_priv);
192extern void intel_wait_for_vblank(struct drm_device *dev); 192extern void intel_wait_for_vblank(struct drm_device *dev);
193extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe); 193extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe);
194extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, 194extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
195 struct drm_display_mode *mode, 195 struct drm_display_mode *mode,
196 int *dpms_mode); 196 int *dpms_mode);
197extern void intel_release_load_detect_pipe(struct intel_output *intel_output, 197extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
198 int dpms_mode); 198 int dpms_mode);
199 199
200extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB); 200extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB);
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 0427ca5a2514..ebf213c96b9c 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -80,8 +80,8 @@ static struct intel_dvo_device intel_dvo_devices[] = {
80static void intel_dvo_dpms(struct drm_encoder *encoder, int mode) 80static void intel_dvo_dpms(struct drm_encoder *encoder, int mode)
81{ 81{
82 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 82 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
83 struct intel_output *intel_output = enc_to_intel_output(encoder); 83 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
84 struct intel_dvo_device *dvo = intel_output->dev_priv; 84 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
85 u32 dvo_reg = dvo->dvo_reg; 85 u32 dvo_reg = dvo->dvo_reg;
86 u32 temp = I915_READ(dvo_reg); 86 u32 temp = I915_READ(dvo_reg);
87 87
@@ -99,8 +99,8 @@ static void intel_dvo_dpms(struct drm_encoder *encoder, int mode)
99static void intel_dvo_save(struct drm_connector *connector) 99static void intel_dvo_save(struct drm_connector *connector)
100{ 100{
101 struct drm_i915_private *dev_priv = connector->dev->dev_private; 101 struct drm_i915_private *dev_priv = connector->dev->dev_private;
102 struct intel_output *intel_output = to_intel_output(connector); 102 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
103 struct intel_dvo_device *dvo = intel_output->dev_priv; 103 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
104 104
105 /* Each output should probably just save the registers it touches, 105 /* Each output should probably just save the registers it touches,
106 * but for now, use more overkill. 106 * but for now, use more overkill.
@@ -115,8 +115,8 @@ static void intel_dvo_save(struct drm_connector *connector)
115static void intel_dvo_restore(struct drm_connector *connector) 115static void intel_dvo_restore(struct drm_connector *connector)
116{ 116{
117 struct drm_i915_private *dev_priv = connector->dev->dev_private; 117 struct drm_i915_private *dev_priv = connector->dev->dev_private;
118 struct intel_output *intel_output = to_intel_output(connector); 118 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
119 struct intel_dvo_device *dvo = intel_output->dev_priv; 119 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
120 120
121 dvo->dev_ops->restore(dvo); 121 dvo->dev_ops->restore(dvo);
122 122
@@ -128,8 +128,8 @@ static void intel_dvo_restore(struct drm_connector *connector)
128static int intel_dvo_mode_valid(struct drm_connector *connector, 128static int intel_dvo_mode_valid(struct drm_connector *connector,
129 struct drm_display_mode *mode) 129 struct drm_display_mode *mode)
130{ 130{
131 struct intel_output *intel_output = to_intel_output(connector); 131 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
132 struct intel_dvo_device *dvo = intel_output->dev_priv; 132 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
133 133
134 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 134 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
135 return MODE_NO_DBLESCAN; 135 return MODE_NO_DBLESCAN;
@@ -150,8 +150,8 @@ static bool intel_dvo_mode_fixup(struct drm_encoder *encoder,
150 struct drm_display_mode *mode, 150 struct drm_display_mode *mode,
151 struct drm_display_mode *adjusted_mode) 151 struct drm_display_mode *adjusted_mode)
152{ 152{
153 struct intel_output *intel_output = enc_to_intel_output(encoder); 153 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
154 struct intel_dvo_device *dvo = intel_output->dev_priv; 154 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
155 155
156 /* If we have timings from the BIOS for the panel, put them in 156 /* If we have timings from the BIOS for the panel, put them in
157 * to the adjusted mode. The CRTC will be set up for this mode, 157 * to the adjusted mode. The CRTC will be set up for this mode,
@@ -186,8 +186,8 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
186 struct drm_device *dev = encoder->dev; 186 struct drm_device *dev = encoder->dev;
187 struct drm_i915_private *dev_priv = dev->dev_private; 187 struct drm_i915_private *dev_priv = dev->dev_private;
188 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 188 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
189 struct intel_output *intel_output = enc_to_intel_output(encoder); 189 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
190 struct intel_dvo_device *dvo = intel_output->dev_priv; 190 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
191 int pipe = intel_crtc->pipe; 191 int pipe = intel_crtc->pipe;
192 u32 dvo_val; 192 u32 dvo_val;
193 u32 dvo_reg = dvo->dvo_reg, dvo_srcdim_reg; 193 u32 dvo_reg = dvo->dvo_reg, dvo_srcdim_reg;
@@ -241,23 +241,23 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
241 */ 241 */
242static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector) 242static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector)
243{ 243{
244 struct intel_output *intel_output = to_intel_output(connector); 244 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
245 struct intel_dvo_device *dvo = intel_output->dev_priv; 245 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
246 246
247 return dvo->dev_ops->detect(dvo); 247 return dvo->dev_ops->detect(dvo);
248} 248}
249 249
250static int intel_dvo_get_modes(struct drm_connector *connector) 250static int intel_dvo_get_modes(struct drm_connector *connector)
251{ 251{
252 struct intel_output *intel_output = to_intel_output(connector); 252 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
253 struct intel_dvo_device *dvo = intel_output->dev_priv; 253 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
254 254
255 /* We should probably have an i2c driver get_modes function for those 255 /* We should probably have an i2c driver get_modes function for those
256 * devices which will have a fixed set of modes determined by the chip 256 * devices which will have a fixed set of modes determined by the chip
257 * (TV-out, for example), but for now with just TMDS and LVDS, 257 * (TV-out, for example), but for now with just TMDS and LVDS,
258 * that's not the case. 258 * that's not the case.
259 */ 259 */
260 intel_ddc_get_modes(intel_output); 260 intel_ddc_get_modes(intel_encoder);
261 if (!list_empty(&connector->probed_modes)) 261 if (!list_empty(&connector->probed_modes))
262 return 1; 262 return 1;
263 263
@@ -275,8 +275,8 @@ static int intel_dvo_get_modes(struct drm_connector *connector)
275 275
276static void intel_dvo_destroy (struct drm_connector *connector) 276static void intel_dvo_destroy (struct drm_connector *connector)
277{ 277{
278 struct intel_output *intel_output = to_intel_output(connector); 278 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
279 struct intel_dvo_device *dvo = intel_output->dev_priv; 279 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
280 280
281 if (dvo) { 281 if (dvo) {
282 if (dvo->dev_ops->destroy) 282 if (dvo->dev_ops->destroy)
@@ -286,13 +286,13 @@ static void intel_dvo_destroy (struct drm_connector *connector)
286 /* no need, in i830_dvoices[] now */ 286 /* no need, in i830_dvoices[] now */
287 //kfree(dvo); 287 //kfree(dvo);
288 } 288 }
289 if (intel_output->i2c_bus) 289 if (intel_encoder->i2c_bus)
290 intel_i2c_destroy(intel_output->i2c_bus); 290 intel_i2c_destroy(intel_encoder->i2c_bus);
291 if (intel_output->ddc_bus) 291 if (intel_encoder->ddc_bus)
292 intel_i2c_destroy(intel_output->ddc_bus); 292 intel_i2c_destroy(intel_encoder->ddc_bus);
293 drm_sysfs_connector_remove(connector); 293 drm_sysfs_connector_remove(connector);
294 drm_connector_cleanup(connector); 294 drm_connector_cleanup(connector);
295 kfree(intel_output); 295 kfree(intel_encoder);
296} 296}
297 297
298#ifdef RANDR_GET_CRTC_INTERFACE 298#ifdef RANDR_GET_CRTC_INTERFACE
@@ -300,8 +300,8 @@ static struct drm_crtc *intel_dvo_get_crtc(struct drm_connector *connector)
300{ 300{
301 struct drm_device *dev = connector->dev; 301 struct drm_device *dev = connector->dev;
302 struct drm_i915_private *dev_priv = dev->dev_private; 302 struct drm_i915_private *dev_priv = dev->dev_private;
303 struct intel_output *intel_output = to_intel_output(connector); 303 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
304 struct intel_dvo_device *dvo = intel_output->dev_priv; 304 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
305 int pipe = !!(I915_READ(dvo->dvo_reg) & SDVO_PIPE_B_SELECT); 305 int pipe = !!(I915_READ(dvo->dvo_reg) & SDVO_PIPE_B_SELECT);
306 306
307 return intel_pipe_to_crtc(pScrn, pipe); 307 return intel_pipe_to_crtc(pScrn, pipe);
@@ -352,8 +352,8 @@ intel_dvo_get_current_mode (struct drm_connector *connector)
352{ 352{
353 struct drm_device *dev = connector->dev; 353 struct drm_device *dev = connector->dev;
354 struct drm_i915_private *dev_priv = dev->dev_private; 354 struct drm_i915_private *dev_priv = dev->dev_private;
355 struct intel_output *intel_output = to_intel_output(connector); 355 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
356 struct intel_dvo_device *dvo = intel_output->dev_priv; 356 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
357 uint32_t dvo_reg = dvo->dvo_reg; 357 uint32_t dvo_reg = dvo->dvo_reg;
358 uint32_t dvo_val = I915_READ(dvo_reg); 358 uint32_t dvo_val = I915_READ(dvo_reg);
359 struct drm_display_mode *mode = NULL; 359 struct drm_display_mode *mode = NULL;
@@ -383,24 +383,24 @@ intel_dvo_get_current_mode (struct drm_connector *connector)
383 383
384void intel_dvo_init(struct drm_device *dev) 384void intel_dvo_init(struct drm_device *dev)
385{ 385{
386 struct intel_output *intel_output; 386 struct intel_encoder *intel_encoder;
387 struct intel_dvo_device *dvo; 387 struct intel_dvo_device *dvo;
388 struct i2c_adapter *i2cbus = NULL; 388 struct i2c_adapter *i2cbus = NULL;
389 int ret = 0; 389 int ret = 0;
390 int i; 390 int i;
391 int encoder_type = DRM_MODE_ENCODER_NONE; 391 int encoder_type = DRM_MODE_ENCODER_NONE;
392 intel_output = kzalloc (sizeof(struct intel_output), GFP_KERNEL); 392 intel_encoder = kzalloc (sizeof(struct intel_encoder), GFP_KERNEL);
393 if (!intel_output) 393 if (!intel_encoder)
394 return; 394 return;
395 395
396 /* Set up the DDC bus */ 396 /* Set up the DDC bus */
397 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "DVODDC_D"); 397 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "DVODDC_D");
398 if (!intel_output->ddc_bus) 398 if (!intel_encoder->ddc_bus)
399 goto free_intel; 399 goto free_intel;
400 400
401 /* Now, try to find a controller */ 401 /* Now, try to find a controller */
402 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 402 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
403 struct drm_connector *connector = &intel_output->base; 403 struct drm_connector *connector = &intel_encoder->base;
404 int gpio; 404 int gpio;
405 405
406 dvo = &intel_dvo_devices[i]; 406 dvo = &intel_dvo_devices[i];
@@ -435,11 +435,11 @@ void intel_dvo_init(struct drm_device *dev)
435 if (!ret) 435 if (!ret)
436 continue; 436 continue;
437 437
438 intel_output->type = INTEL_OUTPUT_DVO; 438 intel_encoder->type = INTEL_OUTPUT_DVO;
439 intel_output->crtc_mask = (1 << 0) | (1 << 1); 439 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
440 switch (dvo->type) { 440 switch (dvo->type) {
441 case INTEL_DVO_CHIP_TMDS: 441 case INTEL_DVO_CHIP_TMDS:
442 intel_output->clone_mask = 442 intel_encoder->clone_mask =
443 (1 << INTEL_DVO_TMDS_CLONE_BIT) | 443 (1 << INTEL_DVO_TMDS_CLONE_BIT) |
444 (1 << INTEL_ANALOG_CLONE_BIT); 444 (1 << INTEL_ANALOG_CLONE_BIT);
445 drm_connector_init(dev, connector, 445 drm_connector_init(dev, connector,
@@ -448,7 +448,7 @@ void intel_dvo_init(struct drm_device *dev)
448 encoder_type = DRM_MODE_ENCODER_TMDS; 448 encoder_type = DRM_MODE_ENCODER_TMDS;
449 break; 449 break;
450 case INTEL_DVO_CHIP_LVDS: 450 case INTEL_DVO_CHIP_LVDS:
451 intel_output->clone_mask = 451 intel_encoder->clone_mask =
452 (1 << INTEL_DVO_LVDS_CLONE_BIT); 452 (1 << INTEL_DVO_LVDS_CLONE_BIT);
453 drm_connector_init(dev, connector, 453 drm_connector_init(dev, connector,
454 &intel_dvo_connector_funcs, 454 &intel_dvo_connector_funcs,
@@ -463,16 +463,16 @@ void intel_dvo_init(struct drm_device *dev)
463 connector->interlace_allowed = false; 463 connector->interlace_allowed = false;
464 connector->doublescan_allowed = false; 464 connector->doublescan_allowed = false;
465 465
466 intel_output->dev_priv = dvo; 466 intel_encoder->dev_priv = dvo;
467 intel_output->i2c_bus = i2cbus; 467 intel_encoder->i2c_bus = i2cbus;
468 468
469 drm_encoder_init(dev, &intel_output->enc, 469 drm_encoder_init(dev, &intel_encoder->enc,
470 &intel_dvo_enc_funcs, encoder_type); 470 &intel_dvo_enc_funcs, encoder_type);
471 drm_encoder_helper_add(&intel_output->enc, 471 drm_encoder_helper_add(&intel_encoder->enc,
472 &intel_dvo_helper_funcs); 472 &intel_dvo_helper_funcs);
473 473
474 drm_mode_connector_attach_encoder(&intel_output->base, 474 drm_mode_connector_attach_encoder(&intel_encoder->base,
475 &intel_output->enc); 475 &intel_encoder->enc);
476 if (dvo->type == INTEL_DVO_CHIP_LVDS) { 476 if (dvo->type == INTEL_DVO_CHIP_LVDS) {
477 /* For our LVDS chipsets, we should hopefully be able 477 /* For our LVDS chipsets, we should hopefully be able
478 * to dig the fixed panel mode out of the BIOS data. 478 * to dig the fixed panel mode out of the BIOS data.
@@ -490,10 +490,10 @@ void intel_dvo_init(struct drm_device *dev)
490 return; 490 return;
491 } 491 }
492 492
493 intel_i2c_destroy(intel_output->ddc_bus); 493 intel_i2c_destroy(intel_encoder->ddc_bus);
494 /* Didn't find a chip, so tear down. */ 494 /* Didn't find a chip, so tear down. */
495 if (i2cbus != NULL) 495 if (i2cbus != NULL)
496 intel_i2c_destroy(i2cbus); 496 intel_i2c_destroy(i2cbus);
497free_intel: 497free_intel:
498 kfree(intel_output); 498 kfree(intel_encoder);
499} 499}
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 69bbef92f130..8a0b3bcdc7b1 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -144,7 +144,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
144 ret = -ENOMEM; 144 ret = -ENOMEM;
145 goto out; 145 goto out;
146 } 146 }
147 obj_priv = fbo->driver_private; 147 obj_priv = to_intel_bo(fbo);
148 148
149 mutex_lock(&dev->struct_mutex); 149 mutex_lock(&dev->struct_mutex);
150 150
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 1ed02f641258..48cade0cf7b1 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -51,8 +51,8 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
51 struct drm_i915_private *dev_priv = dev->dev_private; 51 struct drm_i915_private *dev_priv = dev->dev_private;
52 struct drm_crtc *crtc = encoder->crtc; 52 struct drm_crtc *crtc = encoder->crtc;
53 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 53 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
54 struct intel_output *intel_output = enc_to_intel_output(encoder); 54 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
55 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 55 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
56 u32 sdvox; 56 u32 sdvox;
57 57
58 sdvox = SDVO_ENCODING_HDMI | 58 sdvox = SDVO_ENCODING_HDMI |
@@ -74,8 +74,8 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
74{ 74{
75 struct drm_device *dev = encoder->dev; 75 struct drm_device *dev = encoder->dev;
76 struct drm_i915_private *dev_priv = dev->dev_private; 76 struct drm_i915_private *dev_priv = dev->dev_private;
77 struct intel_output *intel_output = enc_to_intel_output(encoder); 77 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
78 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 78 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
79 u32 temp; 79 u32 temp;
80 80
81 temp = I915_READ(hdmi_priv->sdvox_reg); 81 temp = I915_READ(hdmi_priv->sdvox_reg);
@@ -110,8 +110,8 @@ static void intel_hdmi_save(struct drm_connector *connector)
110{ 110{
111 struct drm_device *dev = connector->dev; 111 struct drm_device *dev = connector->dev;
112 struct drm_i915_private *dev_priv = dev->dev_private; 112 struct drm_i915_private *dev_priv = dev->dev_private;
113 struct intel_output *intel_output = to_intel_output(connector); 113 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
114 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 114 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
115 115
116 hdmi_priv->save_SDVOX = I915_READ(hdmi_priv->sdvox_reg); 116 hdmi_priv->save_SDVOX = I915_READ(hdmi_priv->sdvox_reg);
117} 117}
@@ -120,8 +120,8 @@ static void intel_hdmi_restore(struct drm_connector *connector)
120{ 120{
121 struct drm_device *dev = connector->dev; 121 struct drm_device *dev = connector->dev;
122 struct drm_i915_private *dev_priv = dev->dev_private; 122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct intel_output *intel_output = to_intel_output(connector); 123 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
124 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 124 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
125 125
126 I915_WRITE(hdmi_priv->sdvox_reg, hdmi_priv->save_SDVOX); 126 I915_WRITE(hdmi_priv->sdvox_reg, hdmi_priv->save_SDVOX);
127 POSTING_READ(hdmi_priv->sdvox_reg); 127 POSTING_READ(hdmi_priv->sdvox_reg);
@@ -151,21 +151,21 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
151static enum drm_connector_status 151static enum drm_connector_status
152intel_hdmi_detect(struct drm_connector *connector) 152intel_hdmi_detect(struct drm_connector *connector)
153{ 153{
154 struct intel_output *intel_output = to_intel_output(connector); 154 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
155 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 155 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
156 struct edid *edid = NULL; 156 struct edid *edid = NULL;
157 enum drm_connector_status status = connector_status_disconnected; 157 enum drm_connector_status status = connector_status_disconnected;
158 158
159 hdmi_priv->has_hdmi_sink = false; 159 hdmi_priv->has_hdmi_sink = false;
160 edid = drm_get_edid(&intel_output->base, 160 edid = drm_get_edid(&intel_encoder->base,
161 intel_output->ddc_bus); 161 intel_encoder->ddc_bus);
162 162
163 if (edid) { 163 if (edid) {
164 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 164 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
165 status = connector_status_connected; 165 status = connector_status_connected;
166 hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 166 hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
167 } 167 }
168 intel_output->base.display_info.raw_edid = NULL; 168 intel_encoder->base.display_info.raw_edid = NULL;
169 kfree(edid); 169 kfree(edid);
170 } 170 }
171 171
@@ -174,24 +174,24 @@ intel_hdmi_detect(struct drm_connector *connector)
174 174
175static int intel_hdmi_get_modes(struct drm_connector *connector) 175static int intel_hdmi_get_modes(struct drm_connector *connector)
176{ 176{
177 struct intel_output *intel_output = to_intel_output(connector); 177 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
178 178
179 /* We should parse the EDID data and find out if it's an HDMI sink so 179 /* We should parse the EDID data and find out if it's an HDMI sink so
180 * we can send audio to it. 180 * we can send audio to it.
181 */ 181 */
182 182
183 return intel_ddc_get_modes(intel_output); 183 return intel_ddc_get_modes(intel_encoder);
184} 184}
185 185
186static void intel_hdmi_destroy(struct drm_connector *connector) 186static void intel_hdmi_destroy(struct drm_connector *connector)
187{ 187{
188 struct intel_output *intel_output = to_intel_output(connector); 188 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
189 189
190 if (intel_output->i2c_bus) 190 if (intel_encoder->i2c_bus)
191 intel_i2c_destroy(intel_output->i2c_bus); 191 intel_i2c_destroy(intel_encoder->i2c_bus);
192 drm_sysfs_connector_remove(connector); 192 drm_sysfs_connector_remove(connector);
193 drm_connector_cleanup(connector); 193 drm_connector_cleanup(connector);
194 kfree(intel_output); 194 kfree(intel_encoder);
195} 195}
196 196
197static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 197static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
@@ -230,63 +230,63 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
230{ 230{
231 struct drm_i915_private *dev_priv = dev->dev_private; 231 struct drm_i915_private *dev_priv = dev->dev_private;
232 struct drm_connector *connector; 232 struct drm_connector *connector;
233 struct intel_output *intel_output; 233 struct intel_encoder *intel_encoder;
234 struct intel_hdmi_priv *hdmi_priv; 234 struct intel_hdmi_priv *hdmi_priv;
235 235
236 intel_output = kcalloc(sizeof(struct intel_output) + 236 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
237 sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL); 237 sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL);
238 if (!intel_output) 238 if (!intel_encoder)
239 return; 239 return;
240 hdmi_priv = (struct intel_hdmi_priv *)(intel_output + 1); 240 hdmi_priv = (struct intel_hdmi_priv *)(intel_encoder + 1);
241 241
242 connector = &intel_output->base; 242 connector = &intel_encoder->base;
243 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 243 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
244 DRM_MODE_CONNECTOR_HDMIA); 244 DRM_MODE_CONNECTOR_HDMIA);
245 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 245 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
246 246
247 intel_output->type = INTEL_OUTPUT_HDMI; 247 intel_encoder->type = INTEL_OUTPUT_HDMI;
248 248
249 connector->interlace_allowed = 0; 249 connector->interlace_allowed = 0;
250 connector->doublescan_allowed = 0; 250 connector->doublescan_allowed = 0;
251 intel_output->crtc_mask = (1 << 0) | (1 << 1); 251 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
252 252
253 /* Set up the DDC bus. */ 253 /* Set up the DDC bus. */
254 if (sdvox_reg == SDVOB) { 254 if (sdvox_reg == SDVOB) {
255 intel_output->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); 255 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
256 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB"); 256 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB");
257 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 257 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
258 } else if (sdvox_reg == SDVOC) { 258 } else if (sdvox_reg == SDVOC) {
259 intel_output->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); 259 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
260 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC"); 260 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC");
261 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 261 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
262 } else if (sdvox_reg == HDMIB) { 262 } else if (sdvox_reg == HDMIB) {
263 intel_output->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); 263 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
264 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE, 264 intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOE,
265 "HDMIB"); 265 "HDMIB");
266 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 266 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
267 } else if (sdvox_reg == HDMIC) { 267 } else if (sdvox_reg == HDMIC) {
268 intel_output->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); 268 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
269 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD, 269 intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOD,
270 "HDMIC"); 270 "HDMIC");
271 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 271 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
272 } else if (sdvox_reg == HDMID) { 272 } else if (sdvox_reg == HDMID) {
273 intel_output->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); 273 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
274 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF, 274 intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOF,
275 "HDMID"); 275 "HDMID");
276 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; 276 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
277 } 277 }
278 if (!intel_output->ddc_bus) 278 if (!intel_encoder->ddc_bus)
279 goto err_connector; 279 goto err_connector;
280 280
281 hdmi_priv->sdvox_reg = sdvox_reg; 281 hdmi_priv->sdvox_reg = sdvox_reg;
282 intel_output->dev_priv = hdmi_priv; 282 intel_encoder->dev_priv = hdmi_priv;
283 283
284 drm_encoder_init(dev, &intel_output->enc, &intel_hdmi_enc_funcs, 284 drm_encoder_init(dev, &intel_encoder->enc, &intel_hdmi_enc_funcs,
285 DRM_MODE_ENCODER_TMDS); 285 DRM_MODE_ENCODER_TMDS);
286 drm_encoder_helper_add(&intel_output->enc, &intel_hdmi_helper_funcs); 286 drm_encoder_helper_add(&intel_encoder->enc, &intel_hdmi_helper_funcs);
287 287
288 drm_mode_connector_attach_encoder(&intel_output->base, 288 drm_mode_connector_attach_encoder(&intel_encoder->base,
289 &intel_output->enc); 289 &intel_encoder->enc);
290 drm_sysfs_connector_add(connector); 290 drm_sysfs_connector_add(connector);
291 291
292 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 292 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
@@ -302,7 +302,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
302 302
303err_connector: 303err_connector:
304 drm_connector_cleanup(connector); 304 drm_connector_cleanup(connector);
305 kfree(intel_output); 305 kfree(intel_encoder);
306 306
307 return; 307 return;
308} 308}
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 216e9f52b6e0..b66806a37d37 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -239,8 +239,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
239 struct drm_i915_private *dev_priv = dev->dev_private; 239 struct drm_i915_private *dev_priv = dev->dev_private;
240 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 240 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
241 struct drm_encoder *tmp_encoder; 241 struct drm_encoder *tmp_encoder;
242 struct intel_output *intel_output = enc_to_intel_output(encoder); 242 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
243 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; 243 struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
244 u32 pfit_control = 0, pfit_pgm_ratios = 0; 244 u32 pfit_control = 0, pfit_pgm_ratios = 0;
245 int left_border = 0, right_border = 0, top_border = 0; 245 int left_border = 0, right_border = 0, top_border = 0;
246 int bottom_border = 0; 246 int bottom_border = 0;
@@ -587,8 +587,8 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
587{ 587{
588 struct drm_device *dev = encoder->dev; 588 struct drm_device *dev = encoder->dev;
589 struct drm_i915_private *dev_priv = dev->dev_private; 589 struct drm_i915_private *dev_priv = dev->dev_private;
590 struct intel_output *intel_output = enc_to_intel_output(encoder); 590 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
591 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; 591 struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
592 592
593 /* 593 /*
594 * The LVDS pin pair will already have been turned on in the 594 * The LVDS pin pair will already have been turned on in the
@@ -635,14 +635,16 @@ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connect
635static int intel_lvds_get_modes(struct drm_connector *connector) 635static int intel_lvds_get_modes(struct drm_connector *connector)
636{ 636{
637 struct drm_device *dev = connector->dev; 637 struct drm_device *dev = connector->dev;
638 struct intel_output *intel_output = to_intel_output(connector); 638 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
639 struct drm_i915_private *dev_priv = dev->dev_private; 639 struct drm_i915_private *dev_priv = dev->dev_private;
640 int ret = 0; 640 int ret = 0;
641 641
642 ret = intel_ddc_get_modes(intel_output); 642 if (dev_priv->lvds_edid_good) {
643 ret = intel_ddc_get_modes(intel_encoder);
643 644
644 if (ret) 645 if (ret)
645 return ret; 646 return ret;
647 }
646 648
647 /* Didn't get an EDID, so 649 /* Didn't get an EDID, so
648 * Set wide sync ranges so we get all modes 650 * Set wide sync ranges so we get all modes
@@ -715,11 +717,11 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
715static void intel_lvds_destroy(struct drm_connector *connector) 717static void intel_lvds_destroy(struct drm_connector *connector)
716{ 718{
717 struct drm_device *dev = connector->dev; 719 struct drm_device *dev = connector->dev;
718 struct intel_output *intel_output = to_intel_output(connector); 720 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
719 struct drm_i915_private *dev_priv = dev->dev_private; 721 struct drm_i915_private *dev_priv = dev->dev_private;
720 722
721 if (intel_output->ddc_bus) 723 if (intel_encoder->ddc_bus)
722 intel_i2c_destroy(intel_output->ddc_bus); 724 intel_i2c_destroy(intel_encoder->ddc_bus);
723 if (dev_priv->lid_notifier.notifier_call) 725 if (dev_priv->lid_notifier.notifier_call)
724 acpi_lid_notifier_unregister(&dev_priv->lid_notifier); 726 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
725 drm_sysfs_connector_remove(connector); 727 drm_sysfs_connector_remove(connector);
@@ -732,13 +734,13 @@ static int intel_lvds_set_property(struct drm_connector *connector,
732 uint64_t value) 734 uint64_t value)
733{ 735{
734 struct drm_device *dev = connector->dev; 736 struct drm_device *dev = connector->dev;
735 struct intel_output *intel_output = 737 struct intel_encoder *intel_encoder =
736 to_intel_output(connector); 738 to_intel_encoder(connector);
737 739
738 if (property == dev->mode_config.scaling_mode_property && 740 if (property == dev->mode_config.scaling_mode_property &&
739 connector->encoder) { 741 connector->encoder) {
740 struct drm_crtc *crtc = connector->encoder->crtc; 742 struct drm_crtc *crtc = connector->encoder->crtc;
741 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; 743 struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
742 if (value == DRM_MODE_SCALE_NONE) { 744 if (value == DRM_MODE_SCALE_NONE) {
743 DRM_DEBUG_KMS("no scaling not supported\n"); 745 DRM_DEBUG_KMS("no scaling not supported\n");
744 return 0; 746 return 0;
@@ -858,6 +860,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
858 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 860 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
859 }, 861 },
860 }, 862 },
863 {
864 .callback = intel_no_lvds_dmi_callback,
865 .ident = "Clientron U800",
866 .matches = {
867 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
868 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
869 },
870 },
861 871
862 { } /* terminating entry */ 872 { } /* terminating entry */
863}; 873};
@@ -968,7 +978,7 @@ static int lvds_is_present_in_vbt(struct drm_device *dev)
968void intel_lvds_init(struct drm_device *dev) 978void intel_lvds_init(struct drm_device *dev)
969{ 979{
970 struct drm_i915_private *dev_priv = dev->dev_private; 980 struct drm_i915_private *dev_priv = dev->dev_private;
971 struct intel_output *intel_output; 981 struct intel_encoder *intel_encoder;
972 struct drm_connector *connector; 982 struct drm_connector *connector;
973 struct drm_encoder *encoder; 983 struct drm_encoder *encoder;
974 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 984 struct drm_display_mode *scan; /* *modes, *bios_mode; */
@@ -996,40 +1006,40 @@ void intel_lvds_init(struct drm_device *dev)
996 gpio = PCH_GPIOC; 1006 gpio = PCH_GPIOC;
997 } 1007 }
998 1008
999 intel_output = kzalloc(sizeof(struct intel_output) + 1009 intel_encoder = kzalloc(sizeof(struct intel_encoder) +
1000 sizeof(struct intel_lvds_priv), GFP_KERNEL); 1010 sizeof(struct intel_lvds_priv), GFP_KERNEL);
1001 if (!intel_output) { 1011 if (!intel_encoder) {
1002 return; 1012 return;
1003 } 1013 }
1004 1014
1005 connector = &intel_output->base; 1015 connector = &intel_encoder->base;
1006 encoder = &intel_output->enc; 1016 encoder = &intel_encoder->enc;
1007 drm_connector_init(dev, &intel_output->base, &intel_lvds_connector_funcs, 1017 drm_connector_init(dev, &intel_encoder->base, &intel_lvds_connector_funcs,
1008 DRM_MODE_CONNECTOR_LVDS); 1018 DRM_MODE_CONNECTOR_LVDS);
1009 1019
1010 drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs, 1020 drm_encoder_init(dev, &intel_encoder->enc, &intel_lvds_enc_funcs,
1011 DRM_MODE_ENCODER_LVDS); 1021 DRM_MODE_ENCODER_LVDS);
1012 1022
1013 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); 1023 drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc);
1014 intel_output->type = INTEL_OUTPUT_LVDS; 1024 intel_encoder->type = INTEL_OUTPUT_LVDS;
1015 1025
1016 intel_output->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); 1026 intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
1017 intel_output->crtc_mask = (1 << 1); 1027 intel_encoder->crtc_mask = (1 << 1);
1018 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); 1028 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
1019 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 1029 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1020 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1030 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1021 connector->interlace_allowed = false; 1031 connector->interlace_allowed = false;
1022 connector->doublescan_allowed = false; 1032 connector->doublescan_allowed = false;
1023 1033
1024 lvds_priv = (struct intel_lvds_priv *)(intel_output + 1); 1034 lvds_priv = (struct intel_lvds_priv *)(intel_encoder + 1);
1025 intel_output->dev_priv = lvds_priv; 1035 intel_encoder->dev_priv = lvds_priv;
1026 /* create the scaling mode property */ 1036 /* create the scaling mode property */
1027 drm_mode_create_scaling_mode_property(dev); 1037 drm_mode_create_scaling_mode_property(dev);
1028 /* 1038 /*
1029 * the initial panel fitting mode will be FULL_SCREEN. 1039 * the initial panel fitting mode will be FULL_SCREEN.
1030 */ 1040 */
1031 1041
1032 drm_connector_attach_property(&intel_output->base, 1042 drm_connector_attach_property(&intel_encoder->base,
1033 dev->mode_config.scaling_mode_property, 1043 dev->mode_config.scaling_mode_property,
1034 DRM_MODE_SCALE_FULLSCREEN); 1044 DRM_MODE_SCALE_FULLSCREEN);
1035 lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN; 1045 lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN;
@@ -1044,8 +1054,8 @@ void intel_lvds_init(struct drm_device *dev)
1044 */ 1054 */
1045 1055
1046 /* Set up the DDC bus. */ 1056 /* Set up the DDC bus. */
1047 intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C"); 1057 intel_encoder->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C");
1048 if (!intel_output->ddc_bus) { 1058 if (!intel_encoder->ddc_bus) {
1049 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " 1059 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
1050 "failed.\n"); 1060 "failed.\n");
1051 goto failed; 1061 goto failed;
@@ -1055,7 +1065,10 @@ void intel_lvds_init(struct drm_device *dev)
1055 * Attempt to get the fixed panel mode from DDC. Assume that the 1065 * Attempt to get the fixed panel mode from DDC. Assume that the
1056 * preferred mode is the right one. 1066 * preferred mode is the right one.
1057 */ 1067 */
1058 intel_ddc_get_modes(intel_output); 1068 dev_priv->lvds_edid_good = true;
1069
1070 if (!intel_ddc_get_modes(intel_encoder))
1071 dev_priv->lvds_edid_good = false;
1059 1072
1060 list_for_each_entry(scan, &connector->probed_modes, head) { 1073 list_for_each_entry(scan, &connector->probed_modes, head) {
1061 mutex_lock(&dev->mode_config.mutex); 1074 mutex_lock(&dev->mode_config.mutex);
@@ -1133,9 +1146,9 @@ out:
1133 1146
1134failed: 1147failed:
1135 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1148 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1136 if (intel_output->ddc_bus) 1149 if (intel_encoder->ddc_bus)
1137 intel_i2c_destroy(intel_output->ddc_bus); 1150 intel_i2c_destroy(intel_encoder->ddc_bus);
1138 drm_connector_cleanup(connector); 1151 drm_connector_cleanup(connector);
1139 drm_encoder_cleanup(encoder); 1152 drm_encoder_cleanup(encoder);
1140 kfree(intel_output); 1153 kfree(intel_encoder);
1141} 1154}
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index 89d303d1d3fb..8e5c83b2d120 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -34,7 +34,7 @@
34 * intel_ddc_probe 34 * intel_ddc_probe
35 * 35 *
36 */ 36 */
37bool intel_ddc_probe(struct intel_output *intel_output) 37bool intel_ddc_probe(struct intel_encoder *intel_encoder)
38{ 38{
39 u8 out_buf[] = { 0x0, 0x0}; 39 u8 out_buf[] = { 0x0, 0x0};
40 u8 buf[2]; 40 u8 buf[2];
@@ -54,9 +54,9 @@ bool intel_ddc_probe(struct intel_output *intel_output)
54 } 54 }
55 }; 55 };
56 56
57 intel_i2c_quirk_set(intel_output->base.dev, true); 57 intel_i2c_quirk_set(intel_encoder->base.dev, true);
58 ret = i2c_transfer(intel_output->ddc_bus, msgs, 2); 58 ret = i2c_transfer(intel_encoder->ddc_bus, msgs, 2);
59 intel_i2c_quirk_set(intel_output->base.dev, false); 59 intel_i2c_quirk_set(intel_encoder->base.dev, false);
60 if (ret == 2) 60 if (ret == 2)
61 return true; 61 return true;
62 62
@@ -69,19 +69,19 @@ bool intel_ddc_probe(struct intel_output *intel_output)
69 * 69 *
70 * Fetch the EDID information from @connector using the DDC bus. 70 * Fetch the EDID information from @connector using the DDC bus.
71 */ 71 */
72int intel_ddc_get_modes(struct intel_output *intel_output) 72int intel_ddc_get_modes(struct intel_encoder *intel_encoder)
73{ 73{
74 struct edid *edid; 74 struct edid *edid;
75 int ret = 0; 75 int ret = 0;
76 76
77 intel_i2c_quirk_set(intel_output->base.dev, true); 77 intel_i2c_quirk_set(intel_encoder->base.dev, true);
78 edid = drm_get_edid(&intel_output->base, intel_output->ddc_bus); 78 edid = drm_get_edid(&intel_encoder->base, intel_encoder->ddc_bus);
79 intel_i2c_quirk_set(intel_output->base.dev, false); 79 intel_i2c_quirk_set(intel_encoder->base.dev, false);
80 if (edid) { 80 if (edid) {
81 drm_mode_connector_update_edid_property(&intel_output->base, 81 drm_mode_connector_update_edid_property(&intel_encoder->base,
82 edid); 82 edid);
83 ret = drm_add_edid_modes(&intel_output->base, edid); 83 ret = drm_add_edid_modes(&intel_encoder->base, edid);
84 intel_output->base.display_info.raw_edid = NULL; 84 intel_encoder->base.display_info.raw_edid = NULL;
85 kfree(edid); 85 kfree(edid);
86 } 86 }
87 87
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 60595fc26fdd..6d524a1fc271 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -724,7 +724,7 @@ int intel_overlay_do_put_image(struct intel_overlay *overlay,
724 int ret, tmp_width; 724 int ret, tmp_width;
725 struct overlay_registers *regs; 725 struct overlay_registers *regs;
726 bool scale_changed = false; 726 bool scale_changed = false;
727 struct drm_i915_gem_object *bo_priv = new_bo->driver_private; 727 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
728 struct drm_device *dev = overlay->dev; 728 struct drm_device *dev = overlay->dev;
729 729
730 BUG_ON(!mutex_is_locked(&dev->struct_mutex)); 730 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -809,7 +809,7 @@ int intel_overlay_do_put_image(struct intel_overlay *overlay,
809 intel_overlay_continue(overlay, scale_changed); 809 intel_overlay_continue(overlay, scale_changed);
810 810
811 overlay->old_vid_bo = overlay->vid_bo; 811 overlay->old_vid_bo = overlay->vid_bo;
812 overlay->vid_bo = new_bo->driver_private; 812 overlay->vid_bo = to_intel_bo(new_bo);
813 813
814 return 0; 814 return 0;
815 815
@@ -1344,7 +1344,7 @@ void intel_setup_overlay(struct drm_device *dev)
1344 reg_bo = drm_gem_object_alloc(dev, PAGE_SIZE); 1344 reg_bo = drm_gem_object_alloc(dev, PAGE_SIZE);
1345 if (!reg_bo) 1345 if (!reg_bo)
1346 goto out_free; 1346 goto out_free;
1347 overlay->reg_bo = reg_bo->driver_private; 1347 overlay->reg_bo = to_intel_bo(reg_bo);
1348 1348
1349 if (OVERLAY_NONPHYSICAL(dev)) { 1349 if (OVERLAY_NONPHYSICAL(dev)) {
1350 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE); 1350 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 26e13a0bf30b..87d953664cb0 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -54,7 +54,7 @@ struct intel_sdvo_priv {
54 u8 slave_addr; 54 u8 slave_addr;
55 55
56 /* Register for the SDVO device: SDVOB or SDVOC */ 56 /* Register for the SDVO device: SDVOB or SDVOC */
57 int output_device; 57 int sdvo_reg;
58 58
59 /* Active outputs controlled by this SDVO output */ 59 /* Active outputs controlled by this SDVO output */
60 uint16_t controlled_output; 60 uint16_t controlled_output;
@@ -124,7 +124,7 @@ struct intel_sdvo_priv {
124 */ 124 */
125 struct intel_sdvo_encode encode; 125 struct intel_sdvo_encode encode;
126 126
127 /* DDC bus used by this SDVO output */ 127 /* DDC bus used by this SDVO encoder */
128 uint8_t ddc_bus; 128 uint8_t ddc_bus;
129 129
130 /* Mac mini hack -- use the same DDC as the analog connector */ 130 /* Mac mini hack -- use the same DDC as the analog connector */
@@ -162,22 +162,22 @@ struct intel_sdvo_priv {
162}; 162};
163 163
164static bool 164static bool
165intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags); 165intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags);
166 166
167/** 167/**
168 * Writes the SDVOB or SDVOC with the given value, but always writes both 168 * Writes the SDVOB or SDVOC with the given value, but always writes both
169 * SDVOB and SDVOC to work around apparent hardware issues (according to 169 * SDVOB and SDVOC to work around apparent hardware issues (according to
170 * comments in the BIOS). 170 * comments in the BIOS).
171 */ 171 */
172static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val) 172static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
173{ 173{
174 struct drm_device *dev = intel_output->base.dev; 174 struct drm_device *dev = intel_encoder->base.dev;
175 struct drm_i915_private *dev_priv = dev->dev_private; 175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 176 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
177 u32 bval = val, cval = val; 177 u32 bval = val, cval = val;
178 int i; 178 int i;
179 179
180 if (sdvo_priv->output_device == SDVOB) { 180 if (sdvo_priv->sdvo_reg == SDVOB) {
181 cval = I915_READ(SDVOC); 181 cval = I915_READ(SDVOC);
182 } else { 182 } else {
183 bval = I915_READ(SDVOB); 183 bval = I915_READ(SDVOB);
@@ -196,10 +196,10 @@ static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
196 } 196 }
197} 197}
198 198
199static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr, 199static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
200 u8 *ch) 200 u8 *ch)
201{ 201{
202 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 202 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
203 u8 out_buf[2]; 203 u8 out_buf[2];
204 u8 buf[2]; 204 u8 buf[2];
205 int ret; 205 int ret;
@@ -222,7 +222,7 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
222 out_buf[0] = addr; 222 out_buf[0] = addr;
223 out_buf[1] = 0; 223 out_buf[1] = 0;
224 224
225 if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2) 225 if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
226 { 226 {
227 *ch = buf[0]; 227 *ch = buf[0];
228 return true; 228 return true;
@@ -232,10 +232,10 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
232 return false; 232 return false;
233} 233}
234 234
235static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr, 235static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
236 u8 ch) 236 u8 ch)
237{ 237{
238 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 238 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
239 u8 out_buf[2]; 239 u8 out_buf[2];
240 struct i2c_msg msgs[] = { 240 struct i2c_msg msgs[] = {
241 { 241 {
@@ -249,7 +249,7 @@ static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
249 out_buf[0] = addr; 249 out_buf[0] = addr;
250 out_buf[1] = ch; 250 out_buf[1] = ch;
251 251
252 if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1) 252 if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
253 { 253 {
254 return true; 254 return true;
255 } 255 }
@@ -353,13 +353,13 @@ static const struct _sdvo_cmd_name {
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
354}; 354};
355 355
356#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC") 356#define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC")
357#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv) 357#define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)
358 358
359static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd, 359static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
360 void *args, int args_len) 360 void *args, int args_len)
361{ 361{
362 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 362 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
363 int i; 363 int i;
364 364
365 DRM_DEBUG_KMS("%s: W: %02X ", 365 DRM_DEBUG_KMS("%s: W: %02X ",
@@ -379,19 +379,19 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
379 DRM_LOG_KMS("\n"); 379 DRM_LOG_KMS("\n");
380} 380}
381 381
382static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd, 382static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
383 void *args, int args_len) 383 void *args, int args_len)
384{ 384{
385 int i; 385 int i;
386 386
387 intel_sdvo_debug_write(intel_output, cmd, args, args_len); 387 intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
388 388
389 for (i = 0; i < args_len; i++) { 389 for (i = 0; i < args_len; i++) {
390 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i, 390 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
391 ((u8*)args)[i]); 391 ((u8*)args)[i]);
392 } 392 }
393 393
394 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd); 394 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
395} 395}
396 396
397static const char *cmd_status_names[] = { 397static const char *cmd_status_names[] = {
@@ -404,11 +404,11 @@ static const char *cmd_status_names[] = {
404 "Scaling not supported" 404 "Scaling not supported"
405}; 405};
406 406
407static void intel_sdvo_debug_response(struct intel_output *intel_output, 407static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
408 void *response, int response_len, 408 void *response, int response_len,
409 u8 status) 409 u8 status)
410{ 410{
411 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 411 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
412 int i; 412 int i;
413 413
414 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); 414 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
@@ -423,7 +423,7 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output,
423 DRM_LOG_KMS("\n"); 423 DRM_LOG_KMS("\n");
424} 424}
425 425
426static u8 intel_sdvo_read_response(struct intel_output *intel_output, 426static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
427 void *response, int response_len) 427 void *response, int response_len)
428{ 428{
429 int i; 429 int i;
@@ -433,16 +433,16 @@ static u8 intel_sdvo_read_response(struct intel_output *intel_output,
433 while (retry--) { 433 while (retry--) {
434 /* Read the command response */ 434 /* Read the command response */
435 for (i = 0; i < response_len; i++) { 435 for (i = 0; i < response_len; i++) {
436 intel_sdvo_read_byte(intel_output, 436 intel_sdvo_read_byte(intel_encoder,
437 SDVO_I2C_RETURN_0 + i, 437 SDVO_I2C_RETURN_0 + i,
438 &((u8 *)response)[i]); 438 &((u8 *)response)[i]);
439 } 439 }
440 440
441 /* read the return status */ 441 /* read the return status */
442 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS, 442 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
443 &status); 443 &status);
444 444
445 intel_sdvo_debug_response(intel_output, response, response_len, 445 intel_sdvo_debug_response(intel_encoder, response, response_len,
446 status); 446 status);
447 if (status != SDVO_CMD_STATUS_PENDING) 447 if (status != SDVO_CMD_STATUS_PENDING)
448 return status; 448 return status;
@@ -470,10 +470,10 @@ static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
470 * another I2C transaction after issuing the DDC bus switch, it will be 470 * another I2C transaction after issuing the DDC bus switch, it will be
471 * switched to the internal SDVO register. 471 * switched to the internal SDVO register.
472 */ 472 */
473static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output, 473static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
474 u8 target) 474 u8 target)
475{ 475{
476 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 476 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
477 u8 out_buf[2], cmd_buf[2], ret_value[2], ret; 477 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
478 struct i2c_msg msgs[] = { 478 struct i2c_msg msgs[] = {
479 { 479 {
@@ -497,10 +497,10 @@ static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
497 }, 497 },
498 }; 498 };
499 499
500 intel_sdvo_debug_write(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, 500 intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
501 &target, 1); 501 &target, 1);
502 /* write the DDC switch command argument */ 502 /* write the DDC switch command argument */
503 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0, target); 503 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
504 504
505 out_buf[0] = SDVO_I2C_OPCODE; 505 out_buf[0] = SDVO_I2C_OPCODE;
506 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; 506 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
@@ -509,7 +509,7 @@ static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
509 ret_value[0] = 0; 509 ret_value[0] = 0;
510 ret_value[1] = 0; 510 ret_value[1] = 0;
511 511
512 ret = i2c_transfer(intel_output->i2c_bus, msgs, 3); 512 ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
513 if (ret != 3) { 513 if (ret != 3) {
514 /* failure in I2C transfer */ 514 /* failure in I2C transfer */
515 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 515 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
@@ -523,7 +523,7 @@ static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
523 return; 523 return;
524} 524}
525 525
526static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1) 526static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
527{ 527{
528 struct intel_sdvo_set_target_input_args targets = {0}; 528 struct intel_sdvo_set_target_input_args targets = {0};
529 u8 status; 529 u8 status;
@@ -534,10 +534,10 @@ static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool
534 if (target_1) 534 if (target_1)
535 targets.target_1 = 1; 535 targets.target_1 = 1;
536 536
537 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets, 537 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
538 sizeof(targets)); 538 sizeof(targets));
539 539
540 status = intel_sdvo_read_response(intel_output, NULL, 0); 540 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
541 541
542 return (status == SDVO_CMD_STATUS_SUCCESS); 542 return (status == SDVO_CMD_STATUS_SUCCESS);
543} 543}
@@ -548,13 +548,13 @@ static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool
548 * This function is making an assumption about the layout of the response, 548 * This function is making an assumption about the layout of the response,
549 * which should be checked against the docs. 549 * which should be checked against the docs.
550 */ 550 */
551static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2) 551static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
552{ 552{
553 struct intel_sdvo_get_trained_inputs_response response; 553 struct intel_sdvo_get_trained_inputs_response response;
554 u8 status; 554 u8 status;
555 555
556 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0); 556 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
557 status = intel_sdvo_read_response(intel_output, &response, sizeof(response)); 557 status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
558 if (status != SDVO_CMD_STATUS_SUCCESS) 558 if (status != SDVO_CMD_STATUS_SUCCESS)
559 return false; 559 return false;
560 560
@@ -563,29 +563,29 @@ static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, boo
563 return true; 563 return true;
564} 564}
565 565
566static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output, 566static bool intel_sdvo_get_active_outputs(struct intel_encoder *intel_encoder,
567 u16 *outputs) 567 u16 *outputs)
568{ 568{
569 u8 status; 569 u8 status;
570 570
571 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0); 571 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
572 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs)); 572 status = intel_sdvo_read_response(intel_encoder, outputs, sizeof(*outputs));
573 573
574 return (status == SDVO_CMD_STATUS_SUCCESS); 574 return (status == SDVO_CMD_STATUS_SUCCESS);
575} 575}
576 576
577static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output, 577static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
578 u16 outputs) 578 u16 outputs)
579{ 579{
580 u8 status; 580 u8 status;
581 581
582 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs, 582 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
583 sizeof(outputs)); 583 sizeof(outputs));
584 status = intel_sdvo_read_response(intel_output, NULL, 0); 584 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
585 return (status == SDVO_CMD_STATUS_SUCCESS); 585 return (status == SDVO_CMD_STATUS_SUCCESS);
586} 586}
587 587
588static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output, 588static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
589 int mode) 589 int mode)
590{ 590{
591 u8 status, state = SDVO_ENCODER_STATE_ON; 591 u8 status, state = SDVO_ENCODER_STATE_ON;
@@ -605,24 +605,24 @@ static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output
605 break; 605 break;
606 } 606 }
607 607
608 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state, 608 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
609 sizeof(state)); 609 sizeof(state));
610 status = intel_sdvo_read_response(intel_output, NULL, 0); 610 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
611 611
612 return (status == SDVO_CMD_STATUS_SUCCESS); 612 return (status == SDVO_CMD_STATUS_SUCCESS);
613} 613}
614 614
615static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output, 615static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
616 int *clock_min, 616 int *clock_min,
617 int *clock_max) 617 int *clock_max)
618{ 618{
619 struct intel_sdvo_pixel_clock_range clocks; 619 struct intel_sdvo_pixel_clock_range clocks;
620 u8 status; 620 u8 status;
621 621
622 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 622 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
623 NULL, 0); 623 NULL, 0);
624 624
625 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks)); 625 status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
626 626
627 if (status != SDVO_CMD_STATUS_SUCCESS) 627 if (status != SDVO_CMD_STATUS_SUCCESS)
628 return false; 628 return false;
@@ -634,31 +634,31 @@ static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_ou
634 return true; 634 return true;
635} 635}
636 636
637static bool intel_sdvo_set_target_output(struct intel_output *intel_output, 637static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
638 u16 outputs) 638 u16 outputs)
639{ 639{
640 u8 status; 640 u8 status;
641 641
642 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs, 642 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
643 sizeof(outputs)); 643 sizeof(outputs));
644 644
645 status = intel_sdvo_read_response(intel_output, NULL, 0); 645 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
646 return (status == SDVO_CMD_STATUS_SUCCESS); 646 return (status == SDVO_CMD_STATUS_SUCCESS);
647} 647}
648 648
649static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd, 649static bool intel_sdvo_get_timing(struct intel_encoder *intel_encoder, u8 cmd,
650 struct intel_sdvo_dtd *dtd) 650 struct intel_sdvo_dtd *dtd)
651{ 651{
652 u8 status; 652 u8 status;
653 653
654 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0); 654 intel_sdvo_write_cmd(intel_encoder, cmd, NULL, 0);
655 status = intel_sdvo_read_response(intel_output, &dtd->part1, 655 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
656 sizeof(dtd->part1)); 656 sizeof(dtd->part1));
657 if (status != SDVO_CMD_STATUS_SUCCESS) 657 if (status != SDVO_CMD_STATUS_SUCCESS)
658 return false; 658 return false;
659 659
660 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0); 660 intel_sdvo_write_cmd(intel_encoder, cmd + 1, NULL, 0);
661 status = intel_sdvo_read_response(intel_output, &dtd->part2, 661 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
662 sizeof(dtd->part2)); 662 sizeof(dtd->part2));
663 if (status != SDVO_CMD_STATUS_SUCCESS) 663 if (status != SDVO_CMD_STATUS_SUCCESS)
664 return false; 664 return false;
@@ -666,60 +666,60 @@ static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
666 return true; 666 return true;
667} 667}
668 668
669static bool intel_sdvo_get_input_timing(struct intel_output *intel_output, 669static bool intel_sdvo_get_input_timing(struct intel_encoder *intel_encoder,
670 struct intel_sdvo_dtd *dtd) 670 struct intel_sdvo_dtd *dtd)
671{ 671{
672 return intel_sdvo_get_timing(intel_output, 672 return intel_sdvo_get_timing(intel_encoder,
673 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 673 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
674} 674}
675 675
676static bool intel_sdvo_get_output_timing(struct intel_output *intel_output, 676static bool intel_sdvo_get_output_timing(struct intel_encoder *intel_encoder,
677 struct intel_sdvo_dtd *dtd) 677 struct intel_sdvo_dtd *dtd)
678{ 678{
679 return intel_sdvo_get_timing(intel_output, 679 return intel_sdvo_get_timing(intel_encoder,
680 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd); 680 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
681} 681}
682 682
683static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd, 683static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
684 struct intel_sdvo_dtd *dtd) 684 struct intel_sdvo_dtd *dtd)
685{ 685{
686 u8 status; 686 u8 status;
687 687
688 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1)); 688 intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
689 status = intel_sdvo_read_response(intel_output, NULL, 0); 689 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
690 if (status != SDVO_CMD_STATUS_SUCCESS) 690 if (status != SDVO_CMD_STATUS_SUCCESS)
691 return false; 691 return false;
692 692
693 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 693 intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
694 status = intel_sdvo_read_response(intel_output, NULL, 0); 694 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
695 if (status != SDVO_CMD_STATUS_SUCCESS) 695 if (status != SDVO_CMD_STATUS_SUCCESS)
696 return false; 696 return false;
697 697
698 return true; 698 return true;
699} 699}
700 700
701static bool intel_sdvo_set_input_timing(struct intel_output *intel_output, 701static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
702 struct intel_sdvo_dtd *dtd) 702 struct intel_sdvo_dtd *dtd)
703{ 703{
704 return intel_sdvo_set_timing(intel_output, 704 return intel_sdvo_set_timing(intel_encoder,
705 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 705 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
706} 706}
707 707
708static bool intel_sdvo_set_output_timing(struct intel_output *intel_output, 708static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
709 struct intel_sdvo_dtd *dtd) 709 struct intel_sdvo_dtd *dtd)
710{ 710{
711 return intel_sdvo_set_timing(intel_output, 711 return intel_sdvo_set_timing(intel_encoder,
712 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 712 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
713} 713}
714 714
715static bool 715static bool
716intel_sdvo_create_preferred_input_timing(struct intel_output *output, 716intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
717 uint16_t clock, 717 uint16_t clock,
718 uint16_t width, 718 uint16_t width,
719 uint16_t height) 719 uint16_t height)
720{ 720{
721 struct intel_sdvo_preferred_input_timing_args args; 721 struct intel_sdvo_preferred_input_timing_args args;
722 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 722 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
723 uint8_t status; 723 uint8_t status;
724 724
725 memset(&args, 0, sizeof(args)); 725 memset(&args, 0, sizeof(args));
@@ -733,32 +733,33 @@ intel_sdvo_create_preferred_input_timing(struct intel_output *output,
733 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height)) 733 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
734 args.scaled = 1; 734 args.scaled = 1;
735 735
736 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 736 intel_sdvo_write_cmd(intel_encoder,
737 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
737 &args, sizeof(args)); 738 &args, sizeof(args));
738 status = intel_sdvo_read_response(output, NULL, 0); 739 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
739 if (status != SDVO_CMD_STATUS_SUCCESS) 740 if (status != SDVO_CMD_STATUS_SUCCESS)
740 return false; 741 return false;
741 742
742 return true; 743 return true;
743} 744}
744 745
745static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output, 746static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
746 struct intel_sdvo_dtd *dtd) 747 struct intel_sdvo_dtd *dtd)
747{ 748{
748 bool status; 749 bool status;
749 750
750 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 751 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
751 NULL, 0); 752 NULL, 0);
752 753
753 status = intel_sdvo_read_response(output, &dtd->part1, 754 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
754 sizeof(dtd->part1)); 755 sizeof(dtd->part1));
755 if (status != SDVO_CMD_STATUS_SUCCESS) 756 if (status != SDVO_CMD_STATUS_SUCCESS)
756 return false; 757 return false;
757 758
758 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 759 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
759 NULL, 0); 760 NULL, 0);
760 761
761 status = intel_sdvo_read_response(output, &dtd->part2, 762 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
762 sizeof(dtd->part2)); 763 sizeof(dtd->part2));
763 if (status != SDVO_CMD_STATUS_SUCCESS) 764 if (status != SDVO_CMD_STATUS_SUCCESS)
764 return false; 765 return false;
@@ -766,12 +767,12 @@ static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
766 return false; 767 return false;
767} 768}
768 769
769static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output) 770static int intel_sdvo_get_clock_rate_mult(struct intel_encoder *intel_encoder)
770{ 771{
771 u8 response, status; 772 u8 response, status;
772 773
773 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0); 774 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
774 status = intel_sdvo_read_response(intel_output, &response, 1); 775 status = intel_sdvo_read_response(intel_encoder, &response, 1);
775 776
776 if (status != SDVO_CMD_STATUS_SUCCESS) { 777 if (status != SDVO_CMD_STATUS_SUCCESS) {
777 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n"); 778 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
@@ -783,12 +784,12 @@ static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
783 return response; 784 return response;
784} 785}
785 786
786static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val) 787static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
787{ 788{
788 u8 status; 789 u8 status;
789 790
790 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 791 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
791 status = intel_sdvo_read_response(intel_output, NULL, 0); 792 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
792 if (status != SDVO_CMD_STATUS_SUCCESS) 793 if (status != SDVO_CMD_STATUS_SUCCESS)
793 return false; 794 return false;
794 795
@@ -877,13 +878,13 @@ static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
877 mode->flags |= DRM_MODE_FLAG_PVSYNC; 878 mode->flags |= DRM_MODE_FLAG_PVSYNC;
878} 879}
879 880
880static bool intel_sdvo_get_supp_encode(struct intel_output *output, 881static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
881 struct intel_sdvo_encode *encode) 882 struct intel_sdvo_encode *encode)
882{ 883{
883 uint8_t status; 884 uint8_t status;
884 885
885 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); 886 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
886 status = intel_sdvo_read_response(output, encode, sizeof(*encode)); 887 status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
887 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ 888 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
888 memset(encode, 0, sizeof(*encode)); 889 memset(encode, 0, sizeof(*encode));
889 return false; 890 return false;
@@ -892,29 +893,30 @@ static bool intel_sdvo_get_supp_encode(struct intel_output *output,
892 return true; 893 return true;
893} 894}
894 895
895static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode) 896static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
897 uint8_t mode)
896{ 898{
897 uint8_t status; 899 uint8_t status;
898 900
899 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1); 901 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
900 status = intel_sdvo_read_response(output, NULL, 0); 902 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
901 903
902 return (status == SDVO_CMD_STATUS_SUCCESS); 904 return (status == SDVO_CMD_STATUS_SUCCESS);
903} 905}
904 906
905static bool intel_sdvo_set_colorimetry(struct intel_output *output, 907static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
906 uint8_t mode) 908 uint8_t mode)
907{ 909{
908 uint8_t status; 910 uint8_t status;
909 911
910 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 912 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
911 status = intel_sdvo_read_response(output, NULL, 0); 913 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
912 914
913 return (status == SDVO_CMD_STATUS_SUCCESS); 915 return (status == SDVO_CMD_STATUS_SUCCESS);
914} 916}
915 917
916#if 0 918#if 0
917static void intel_sdvo_dump_hdmi_buf(struct intel_output *output) 919static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
918{ 920{
919 int i, j; 921 int i, j;
920 uint8_t set_buf_index[2]; 922 uint8_t set_buf_index[2];
@@ -923,43 +925,45 @@ static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
923 uint8_t buf[48]; 925 uint8_t buf[48];
924 uint8_t *pos; 926 uint8_t *pos;
925 927
926 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); 928 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
927 intel_sdvo_read_response(output, &av_split, 1); 929 intel_sdvo_read_response(encoder, &av_split, 1);
928 930
929 for (i = 0; i <= av_split; i++) { 931 for (i = 0; i <= av_split; i++) {
930 set_buf_index[0] = i; set_buf_index[1] = 0; 932 set_buf_index[0] = i; set_buf_index[1] = 0;
931 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, 933 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
932 set_buf_index, 2); 934 set_buf_index, 2);
933 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 935 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
934 intel_sdvo_read_response(output, &buf_size, 1); 936 intel_sdvo_read_response(encoder, &buf_size, 1);
935 937
936 pos = buf; 938 pos = buf;
937 for (j = 0; j <= buf_size; j += 8) { 939 for (j = 0; j <= buf_size; j += 8) {
938 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA, 940 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
939 NULL, 0); 941 NULL, 0);
940 intel_sdvo_read_response(output, pos, 8); 942 intel_sdvo_read_response(encoder, pos, 8);
941 pos += 8; 943 pos += 8;
942 } 944 }
943 } 945 }
944} 946}
945#endif 947#endif
946 948
947static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index, 949static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
948 uint8_t *data, int8_t size, uint8_t tx_rate) 950 int index,
951 uint8_t *data, int8_t size, uint8_t tx_rate)
949{ 952{
950 uint8_t set_buf_index[2]; 953 uint8_t set_buf_index[2];
951 954
952 set_buf_index[0] = index; 955 set_buf_index[0] = index;
953 set_buf_index[1] = 0; 956 set_buf_index[1] = 0;
954 957
955 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2); 958 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
959 set_buf_index, 2);
956 960
957 for (; size > 0; size -= 8) { 961 for (; size > 0; size -= 8) {
958 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8); 962 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
959 data += 8; 963 data += 8;
960 } 964 }
961 965
962 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); 966 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
963} 967}
964 968
965static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) 969static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
@@ -1034,7 +1038,7 @@ struct dip_infoframe {
1034 } __attribute__ ((packed)) u; 1038 } __attribute__ ((packed)) u;
1035} __attribute__((packed)); 1039} __attribute__((packed));
1036 1040
1037static void intel_sdvo_set_avi_infoframe(struct intel_output *output, 1041static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
1038 struct drm_display_mode * mode) 1042 struct drm_display_mode * mode)
1039{ 1043{
1040 struct dip_infoframe avi_if = { 1044 struct dip_infoframe avi_if = {
@@ -1045,15 +1049,16 @@ static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
1045 1049
1046 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, 1050 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1047 4 + avi_if.len); 1051 4 + avi_if.len);
1048 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len, 1052 intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
1053 4 + avi_if.len,
1049 SDVO_HBUF_TX_VSYNC); 1054 SDVO_HBUF_TX_VSYNC);
1050} 1055}
1051 1056
1052static void intel_sdvo_set_tv_format(struct intel_output *output) 1057static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
1053{ 1058{
1054 1059
1055 struct intel_sdvo_tv_format format; 1060 struct intel_sdvo_tv_format format;
1056 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1061 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1057 uint32_t format_map, i; 1062 uint32_t format_map, i;
1058 uint8_t status; 1063 uint8_t status;
1059 1064
@@ -1066,10 +1071,10 @@ static void intel_sdvo_set_tv_format(struct intel_output *output)
1066 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? 1071 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1067 sizeof(format) : sizeof(format_map)); 1072 sizeof(format) : sizeof(format_map));
1068 1073
1069 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map, 1074 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map,
1070 sizeof(format)); 1075 sizeof(format));
1071 1076
1072 status = intel_sdvo_read_response(output, NULL, 0); 1077 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1073 if (status != SDVO_CMD_STATUS_SUCCESS) 1078 if (status != SDVO_CMD_STATUS_SUCCESS)
1074 DRM_DEBUG_KMS("%s: Failed to set TV format\n", 1079 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1075 SDVO_NAME(sdvo_priv)); 1080 SDVO_NAME(sdvo_priv));
@@ -1079,8 +1084,8 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1079 struct drm_display_mode *mode, 1084 struct drm_display_mode *mode,
1080 struct drm_display_mode *adjusted_mode) 1085 struct drm_display_mode *adjusted_mode)
1081{ 1086{
1082 struct intel_output *output = enc_to_intel_output(encoder); 1087 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1083 struct intel_sdvo_priv *dev_priv = output->dev_priv; 1088 struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
1084 1089
1085 if (dev_priv->is_tv) { 1090 if (dev_priv->is_tv) {
1086 struct intel_sdvo_dtd output_dtd; 1091 struct intel_sdvo_dtd output_dtd;
@@ -1095,22 +1100,22 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1095 1100
1096 /* Set output timings */ 1101 /* Set output timings */
1097 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1102 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1098 intel_sdvo_set_target_output(output, 1103 intel_sdvo_set_target_output(intel_encoder,
1099 dev_priv->controlled_output); 1104 dev_priv->controlled_output);
1100 intel_sdvo_set_output_timing(output, &output_dtd); 1105 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1101 1106
1102 /* Set the input timing to the screen. Assume always input 0. */ 1107 /* Set the input timing to the screen. Assume always input 0. */
1103 intel_sdvo_set_target_input(output, true, false); 1108 intel_sdvo_set_target_input(intel_encoder, true, false);
1104 1109
1105 1110
1106 success = intel_sdvo_create_preferred_input_timing(output, 1111 success = intel_sdvo_create_preferred_input_timing(intel_encoder,
1107 mode->clock / 10, 1112 mode->clock / 10,
1108 mode->hdisplay, 1113 mode->hdisplay,
1109 mode->vdisplay); 1114 mode->vdisplay);
1110 if (success) { 1115 if (success) {
1111 struct intel_sdvo_dtd input_dtd; 1116 struct intel_sdvo_dtd input_dtd;
1112 1117
1113 intel_sdvo_get_preferred_input_timing(output, 1118 intel_sdvo_get_preferred_input_timing(intel_encoder,
1114 &input_dtd); 1119 &input_dtd);
1115 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1120 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1116 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; 1121 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
@@ -1133,16 +1138,16 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1133 intel_sdvo_get_dtd_from_mode(&output_dtd, 1138 intel_sdvo_get_dtd_from_mode(&output_dtd,
1134 dev_priv->sdvo_lvds_fixed_mode); 1139 dev_priv->sdvo_lvds_fixed_mode);
1135 1140
1136 intel_sdvo_set_target_output(output, 1141 intel_sdvo_set_target_output(intel_encoder,
1137 dev_priv->controlled_output); 1142 dev_priv->controlled_output);
1138 intel_sdvo_set_output_timing(output, &output_dtd); 1143 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1139 1144
1140 /* Set the input timing to the screen. Assume always input 0. */ 1145 /* Set the input timing to the screen. Assume always input 0. */
1141 intel_sdvo_set_target_input(output, true, false); 1146 intel_sdvo_set_target_input(intel_encoder, true, false);
1142 1147
1143 1148
1144 success = intel_sdvo_create_preferred_input_timing( 1149 success = intel_sdvo_create_preferred_input_timing(
1145 output, 1150 intel_encoder,
1146 mode->clock / 10, 1151 mode->clock / 10,
1147 mode->hdisplay, 1152 mode->hdisplay,
1148 mode->vdisplay); 1153 mode->vdisplay);
@@ -1150,7 +1155,7 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1150 if (success) { 1155 if (success) {
1151 struct intel_sdvo_dtd input_dtd; 1156 struct intel_sdvo_dtd input_dtd;
1152 1157
1153 intel_sdvo_get_preferred_input_timing(output, 1158 intel_sdvo_get_preferred_input_timing(intel_encoder,
1154 &input_dtd); 1159 &input_dtd);
1155 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1160 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1156 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags; 1161 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
@@ -1182,8 +1187,8 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1182 struct drm_i915_private *dev_priv = dev->dev_private; 1187 struct drm_i915_private *dev_priv = dev->dev_private;
1183 struct drm_crtc *crtc = encoder->crtc; 1188 struct drm_crtc *crtc = encoder->crtc;
1184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1185 struct intel_output *output = enc_to_intel_output(encoder); 1190 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1186 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1191 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1187 u32 sdvox = 0; 1192 u32 sdvox = 0;
1188 int sdvo_pixel_multiply; 1193 int sdvo_pixel_multiply;
1189 struct intel_sdvo_in_out_map in_out; 1194 struct intel_sdvo_in_out_map in_out;
@@ -1202,12 +1207,12 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1202 in_out.in0 = sdvo_priv->controlled_output; 1207 in_out.in0 = sdvo_priv->controlled_output;
1203 in_out.in1 = 0; 1208 in_out.in1 = 0;
1204 1209
1205 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP, 1210 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
1206 &in_out, sizeof(in_out)); 1211 &in_out, sizeof(in_out));
1207 status = intel_sdvo_read_response(output, NULL, 0); 1212 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1208 1213
1209 if (sdvo_priv->is_hdmi) { 1214 if (sdvo_priv->is_hdmi) {
1210 intel_sdvo_set_avi_infoframe(output, mode); 1215 intel_sdvo_set_avi_infoframe(intel_encoder, mode);
1211 sdvox |= SDVO_AUDIO_ENABLE; 1216 sdvox |= SDVO_AUDIO_ENABLE;
1212 } 1217 }
1213 1218
@@ -1224,16 +1229,16 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1224 */ 1229 */
1225 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) { 1230 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1226 /* Set the output timing to the screen */ 1231 /* Set the output timing to the screen */
1227 intel_sdvo_set_target_output(output, 1232 intel_sdvo_set_target_output(intel_encoder,
1228 sdvo_priv->controlled_output); 1233 sdvo_priv->controlled_output);
1229 intel_sdvo_set_output_timing(output, &input_dtd); 1234 intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
1230 } 1235 }
1231 1236
1232 /* Set the input timing to the screen. Assume always input 0. */ 1237 /* Set the input timing to the screen. Assume always input 0. */
1233 intel_sdvo_set_target_input(output, true, false); 1238 intel_sdvo_set_target_input(intel_encoder, true, false);
1234 1239
1235 if (sdvo_priv->is_tv) 1240 if (sdvo_priv->is_tv)
1236 intel_sdvo_set_tv_format(output); 1241 intel_sdvo_set_tv_format(intel_encoder);
1237 1242
1238 /* We would like to use intel_sdvo_create_preferred_input_timing() to 1243 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1239 * provide the device with a timing it can support, if it supports that 1244 * provide the device with a timing it can support, if it supports that
@@ -1241,29 +1246,29 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1241 * output the preferred timing, and we don't support that currently. 1246 * output the preferred timing, and we don't support that currently.
1242 */ 1247 */
1243#if 0 1248#if 0
1244 success = intel_sdvo_create_preferred_input_timing(output, clock, 1249 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
1245 width, height); 1250 width, height);
1246 if (success) { 1251 if (success) {
1247 struct intel_sdvo_dtd *input_dtd; 1252 struct intel_sdvo_dtd *input_dtd;
1248 1253
1249 intel_sdvo_get_preferred_input_timing(output, &input_dtd); 1254 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1250 intel_sdvo_set_input_timing(output, &input_dtd); 1255 intel_sdvo_set_input_timing(encoder, &input_dtd);
1251 } 1256 }
1252#else 1257#else
1253 intel_sdvo_set_input_timing(output, &input_dtd); 1258 intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
1254#endif 1259#endif
1255 1260
1256 switch (intel_sdvo_get_pixel_multiplier(mode)) { 1261 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1257 case 1: 1262 case 1:
1258 intel_sdvo_set_clock_rate_mult(output, 1263 intel_sdvo_set_clock_rate_mult(intel_encoder,
1259 SDVO_CLOCK_RATE_MULT_1X); 1264 SDVO_CLOCK_RATE_MULT_1X);
1260 break; 1265 break;
1261 case 2: 1266 case 2:
1262 intel_sdvo_set_clock_rate_mult(output, 1267 intel_sdvo_set_clock_rate_mult(intel_encoder,
1263 SDVO_CLOCK_RATE_MULT_2X); 1268 SDVO_CLOCK_RATE_MULT_2X);
1264 break; 1269 break;
1265 case 4: 1270 case 4:
1266 intel_sdvo_set_clock_rate_mult(output, 1271 intel_sdvo_set_clock_rate_mult(intel_encoder,
1267 SDVO_CLOCK_RATE_MULT_4X); 1272 SDVO_CLOCK_RATE_MULT_4X);
1268 break; 1273 break;
1269 } 1274 }
@@ -1274,8 +1279,8 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1274 SDVO_VSYNC_ACTIVE_HIGH | 1279 SDVO_VSYNC_ACTIVE_HIGH |
1275 SDVO_HSYNC_ACTIVE_HIGH; 1280 SDVO_HSYNC_ACTIVE_HIGH;
1276 } else { 1281 } else {
1277 sdvox |= I915_READ(sdvo_priv->output_device); 1282 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
1278 switch (sdvo_priv->output_device) { 1283 switch (sdvo_priv->sdvo_reg) {
1279 case SDVOB: 1284 case SDVOB:
1280 sdvox &= SDVOB_PRESERVE_MASK; 1285 sdvox &= SDVOB_PRESERVE_MASK;
1281 break; 1286 break;
@@ -1299,26 +1304,26 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1299 1304
1300 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL) 1305 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1301 sdvox |= SDVO_STALL_SELECT; 1306 sdvox |= SDVO_STALL_SELECT;
1302 intel_sdvo_write_sdvox(output, sdvox); 1307 intel_sdvo_write_sdvox(intel_encoder, sdvox);
1303} 1308}
1304 1309
1305static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) 1310static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1306{ 1311{
1307 struct drm_device *dev = encoder->dev; 1312 struct drm_device *dev = encoder->dev;
1308 struct drm_i915_private *dev_priv = dev->dev_private; 1313 struct drm_i915_private *dev_priv = dev->dev_private;
1309 struct intel_output *intel_output = enc_to_intel_output(encoder); 1314 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1310 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1315 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1311 u32 temp; 1316 u32 temp;
1312 1317
1313 if (mode != DRM_MODE_DPMS_ON) { 1318 if (mode != DRM_MODE_DPMS_ON) {
1314 intel_sdvo_set_active_outputs(intel_output, 0); 1319 intel_sdvo_set_active_outputs(intel_encoder, 0);
1315 if (0) 1320 if (0)
1316 intel_sdvo_set_encoder_power_state(intel_output, mode); 1321 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1317 1322
1318 if (mode == DRM_MODE_DPMS_OFF) { 1323 if (mode == DRM_MODE_DPMS_OFF) {
1319 temp = I915_READ(sdvo_priv->output_device); 1324 temp = I915_READ(sdvo_priv->sdvo_reg);
1320 if ((temp & SDVO_ENABLE) != 0) { 1325 if ((temp & SDVO_ENABLE) != 0) {
1321 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE); 1326 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
1322 } 1327 }
1323 } 1328 }
1324 } else { 1329 } else {
@@ -1326,13 +1331,13 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1326 int i; 1331 int i;
1327 u8 status; 1332 u8 status;
1328 1333
1329 temp = I915_READ(sdvo_priv->output_device); 1334 temp = I915_READ(sdvo_priv->sdvo_reg);
1330 if ((temp & SDVO_ENABLE) == 0) 1335 if ((temp & SDVO_ENABLE) == 0)
1331 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE); 1336 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
1332 for (i = 0; i < 2; i++) 1337 for (i = 0; i < 2; i++)
1333 intel_wait_for_vblank(dev); 1338 intel_wait_for_vblank(dev);
1334 1339
1335 status = intel_sdvo_get_trained_inputs(intel_output, &input1, 1340 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
1336 &input2); 1341 &input2);
1337 1342
1338 1343
@@ -1346,8 +1351,8 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1346 } 1351 }
1347 1352
1348 if (0) 1353 if (0)
1349 intel_sdvo_set_encoder_power_state(intel_output, mode); 1354 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1350 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output); 1355 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->controlled_output);
1351 } 1356 }
1352 return; 1357 return;
1353} 1358}
@@ -1356,22 +1361,22 @@ static void intel_sdvo_save(struct drm_connector *connector)
1356{ 1361{
1357 struct drm_device *dev = connector->dev; 1362 struct drm_device *dev = connector->dev;
1358 struct drm_i915_private *dev_priv = dev->dev_private; 1363 struct drm_i915_private *dev_priv = dev->dev_private;
1359 struct intel_output *intel_output = to_intel_output(connector); 1364 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1360 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1365 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1361 int o; 1366 int o;
1362 1367
1363 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output); 1368 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_encoder);
1364 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs); 1369 intel_sdvo_get_active_outputs(intel_encoder, &sdvo_priv->save_active_outputs);
1365 1370
1366 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { 1371 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1367 intel_sdvo_set_target_input(intel_output, true, false); 1372 intel_sdvo_set_target_input(intel_encoder, true, false);
1368 intel_sdvo_get_input_timing(intel_output, 1373 intel_sdvo_get_input_timing(intel_encoder,
1369 &sdvo_priv->save_input_dtd_1); 1374 &sdvo_priv->save_input_dtd_1);
1370 } 1375 }
1371 1376
1372 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { 1377 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1373 intel_sdvo_set_target_input(intel_output, false, true); 1378 intel_sdvo_set_target_input(intel_encoder, false, true);
1374 intel_sdvo_get_input_timing(intel_output, 1379 intel_sdvo_get_input_timing(intel_encoder,
1375 &sdvo_priv->save_input_dtd_2); 1380 &sdvo_priv->save_input_dtd_2);
1376 } 1381 }
1377 1382
@@ -1380,8 +1385,8 @@ static void intel_sdvo_save(struct drm_connector *connector)
1380 u16 this_output = (1 << o); 1385 u16 this_output = (1 << o);
1381 if (sdvo_priv->caps.output_flags & this_output) 1386 if (sdvo_priv->caps.output_flags & this_output)
1382 { 1387 {
1383 intel_sdvo_set_target_output(intel_output, this_output); 1388 intel_sdvo_set_target_output(intel_encoder, this_output);
1384 intel_sdvo_get_output_timing(intel_output, 1389 intel_sdvo_get_output_timing(intel_encoder,
1385 &sdvo_priv->save_output_dtd[o]); 1390 &sdvo_priv->save_output_dtd[o]);
1386 } 1391 }
1387 } 1392 }
@@ -1389,66 +1394,66 @@ static void intel_sdvo_save(struct drm_connector *connector)
1389 /* XXX: Save TV format/enhancements. */ 1394 /* XXX: Save TV format/enhancements. */
1390 } 1395 }
1391 1396
1392 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device); 1397 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->sdvo_reg);
1393} 1398}
1394 1399
1395static void intel_sdvo_restore(struct drm_connector *connector) 1400static void intel_sdvo_restore(struct drm_connector *connector)
1396{ 1401{
1397 struct drm_device *dev = connector->dev; 1402 struct drm_device *dev = connector->dev;
1398 struct intel_output *intel_output = to_intel_output(connector); 1403 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1399 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1404 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1400 int o; 1405 int o;
1401 int i; 1406 int i;
1402 bool input1, input2; 1407 bool input1, input2;
1403 u8 status; 1408 u8 status;
1404 1409
1405 intel_sdvo_set_active_outputs(intel_output, 0); 1410 intel_sdvo_set_active_outputs(intel_encoder, 0);
1406 1411
1407 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) 1412 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1408 { 1413 {
1409 u16 this_output = (1 << o); 1414 u16 this_output = (1 << o);
1410 if (sdvo_priv->caps.output_flags & this_output) { 1415 if (sdvo_priv->caps.output_flags & this_output) {
1411 intel_sdvo_set_target_output(intel_output, this_output); 1416 intel_sdvo_set_target_output(intel_encoder, this_output);
1412 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]); 1417 intel_sdvo_set_output_timing(intel_encoder, &sdvo_priv->save_output_dtd[o]);
1413 } 1418 }
1414 } 1419 }
1415 1420
1416 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { 1421 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1417 intel_sdvo_set_target_input(intel_output, true, false); 1422 intel_sdvo_set_target_input(intel_encoder, true, false);
1418 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1); 1423 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_1);
1419 } 1424 }
1420 1425
1421 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { 1426 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1422 intel_sdvo_set_target_input(intel_output, false, true); 1427 intel_sdvo_set_target_input(intel_encoder, false, true);
1423 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2); 1428 intel_sdvo_set_input_timing(intel_encoder, &sdvo_priv->save_input_dtd_2);
1424 } 1429 }
1425 1430
1426 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult); 1431 intel_sdvo_set_clock_rate_mult(intel_encoder, sdvo_priv->save_sdvo_mult);
1427 1432
1428 if (sdvo_priv->is_tv) { 1433 if (sdvo_priv->is_tv) {
1429 /* XXX: Restore TV format/enhancements. */ 1434 /* XXX: Restore TV format/enhancements. */
1430 } 1435 }
1431 1436
1432 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX); 1437 intel_sdvo_write_sdvox(intel_encoder, sdvo_priv->save_SDVOX);
1433 1438
1434 if (sdvo_priv->save_SDVOX & SDVO_ENABLE) 1439 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1435 { 1440 {
1436 for (i = 0; i < 2; i++) 1441 for (i = 0; i < 2; i++)
1437 intel_wait_for_vblank(dev); 1442 intel_wait_for_vblank(dev);
1438 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2); 1443 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1, &input2);
1439 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) 1444 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1440 DRM_DEBUG_KMS("First %s output reported failure to " 1445 DRM_DEBUG_KMS("First %s output reported failure to "
1441 "sync\n", SDVO_NAME(sdvo_priv)); 1446 "sync\n", SDVO_NAME(sdvo_priv));
1442 } 1447 }
1443 1448
1444 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs); 1449 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->save_active_outputs);
1445} 1450}
1446 1451
1447static int intel_sdvo_mode_valid(struct drm_connector *connector, 1452static int intel_sdvo_mode_valid(struct drm_connector *connector,
1448 struct drm_display_mode *mode) 1453 struct drm_display_mode *mode)
1449{ 1454{
1450 struct intel_output *intel_output = to_intel_output(connector); 1455 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1451 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1456 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1452 1457
1453 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1458 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1454 return MODE_NO_DBLESCAN; 1459 return MODE_NO_DBLESCAN;
@@ -1473,12 +1478,12 @@ static int intel_sdvo_mode_valid(struct drm_connector *connector,
1473 return MODE_OK; 1478 return MODE_OK;
1474} 1479}
1475 1480
1476static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps) 1481static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
1477{ 1482{
1478 u8 status; 1483 u8 status;
1479 1484
1480 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0); 1485 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1481 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps)); 1486 status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
1482 if (status != SDVO_CMD_STATUS_SUCCESS) 1487 if (status != SDVO_CMD_STATUS_SUCCESS)
1483 return false; 1488 return false;
1484 1489
@@ -1488,22 +1493,22 @@ static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struc
1488struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) 1493struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1489{ 1494{
1490 struct drm_connector *connector = NULL; 1495 struct drm_connector *connector = NULL;
1491 struct intel_output *iout = NULL; 1496 struct intel_encoder *iout = NULL;
1492 struct intel_sdvo_priv *sdvo; 1497 struct intel_sdvo_priv *sdvo;
1493 1498
1494 /* find the sdvo connector */ 1499 /* find the sdvo connector */
1495 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1500 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1496 iout = to_intel_output(connector); 1501 iout = to_intel_encoder(connector);
1497 1502
1498 if (iout->type != INTEL_OUTPUT_SDVO) 1503 if (iout->type != INTEL_OUTPUT_SDVO)
1499 continue; 1504 continue;
1500 1505
1501 sdvo = iout->dev_priv; 1506 sdvo = iout->dev_priv;
1502 1507
1503 if (sdvo->output_device == SDVOB && sdvoB) 1508 if (sdvo->sdvo_reg == SDVOB && sdvoB)
1504 return connector; 1509 return connector;
1505 1510
1506 if (sdvo->output_device == SDVOC && !sdvoB) 1511 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
1507 return connector; 1512 return connector;
1508 1513
1509 } 1514 }
@@ -1515,16 +1520,16 @@ int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1515{ 1520{
1516 u8 response[2]; 1521 u8 response[2];
1517 u8 status; 1522 u8 status;
1518 struct intel_output *intel_output; 1523 struct intel_encoder *intel_encoder;
1519 DRM_DEBUG_KMS("\n"); 1524 DRM_DEBUG_KMS("\n");
1520 1525
1521 if (!connector) 1526 if (!connector)
1522 return 0; 1527 return 0;
1523 1528
1524 intel_output = to_intel_output(connector); 1529 intel_encoder = to_intel_encoder(connector);
1525 1530
1526 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); 1531 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1527 status = intel_sdvo_read_response(intel_output, &response, 2); 1532 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1528 1533
1529 if (response[0] !=0) 1534 if (response[0] !=0)
1530 return 1; 1535 return 1;
@@ -1536,30 +1541,30 @@ void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1536{ 1541{
1537 u8 response[2]; 1542 u8 response[2];
1538 u8 status; 1543 u8 status;
1539 struct intel_output *intel_output = to_intel_output(connector); 1544 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1540 1545
1541 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1546 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1542 intel_sdvo_read_response(intel_output, &response, 2); 1547 intel_sdvo_read_response(intel_encoder, &response, 2);
1543 1548
1544 if (on) { 1549 if (on) {
1545 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); 1550 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1546 status = intel_sdvo_read_response(intel_output, &response, 2); 1551 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1547 1552
1548 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1553 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1549 } else { 1554 } else {
1550 response[0] = 0; 1555 response[0] = 0;
1551 response[1] = 0; 1556 response[1] = 0;
1552 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1557 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1553 } 1558 }
1554 1559
1555 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1560 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1556 intel_sdvo_read_response(intel_output, &response, 2); 1561 intel_sdvo_read_response(intel_encoder, &response, 2);
1557} 1562}
1558 1563
1559static bool 1564static bool
1560intel_sdvo_multifunc_encoder(struct intel_output *intel_output) 1565intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
1561{ 1566{
1562 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1567 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1563 int caps = 0; 1568 int caps = 0;
1564 1569
1565 if (sdvo_priv->caps.output_flags & 1570 if (sdvo_priv->caps.output_flags &
@@ -1593,11 +1598,11 @@ static struct drm_connector *
1593intel_find_analog_connector(struct drm_device *dev) 1598intel_find_analog_connector(struct drm_device *dev)
1594{ 1599{
1595 struct drm_connector *connector; 1600 struct drm_connector *connector;
1596 struct intel_output *intel_output; 1601 struct intel_encoder *intel_encoder;
1597 1602
1598 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1599 intel_output = to_intel_output(connector); 1604 intel_encoder = to_intel_encoder(connector);
1600 if (intel_output->type == INTEL_OUTPUT_ANALOG) 1605 if (intel_encoder->type == INTEL_OUTPUT_ANALOG)
1601 return connector; 1606 return connector;
1602 } 1607 }
1603 return NULL; 1608 return NULL;
@@ -1622,16 +1627,16 @@ intel_analog_is_connected(struct drm_device *dev)
1622enum drm_connector_status 1627enum drm_connector_status
1623intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response) 1628intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1624{ 1629{
1625 struct intel_output *intel_output = to_intel_output(connector); 1630 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1626 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1631 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1627 enum drm_connector_status status = connector_status_connected; 1632 enum drm_connector_status status = connector_status_connected;
1628 struct edid *edid = NULL; 1633 struct edid *edid = NULL;
1629 1634
1630 edid = drm_get_edid(&intel_output->base, 1635 edid = drm_get_edid(&intel_encoder->base,
1631 intel_output->ddc_bus); 1636 intel_encoder->ddc_bus);
1632 1637
1633 /* This is only applied to SDVO cards with multiple outputs */ 1638 /* This is only applied to SDVO cards with multiple outputs */
1634 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_output)) { 1639 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
1635 uint8_t saved_ddc, temp_ddc; 1640 uint8_t saved_ddc, temp_ddc;
1636 saved_ddc = sdvo_priv->ddc_bus; 1641 saved_ddc = sdvo_priv->ddc_bus;
1637 temp_ddc = sdvo_priv->ddc_bus >> 1; 1642 temp_ddc = sdvo_priv->ddc_bus >> 1;
@@ -1641,8 +1646,8 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1641 */ 1646 */
1642 while(temp_ddc > 1) { 1647 while(temp_ddc > 1) {
1643 sdvo_priv->ddc_bus = temp_ddc; 1648 sdvo_priv->ddc_bus = temp_ddc;
1644 edid = drm_get_edid(&intel_output->base, 1649 edid = drm_get_edid(&intel_encoder->base,
1645 intel_output->ddc_bus); 1650 intel_encoder->ddc_bus);
1646 if (edid) { 1651 if (edid) {
1647 /* 1652 /*
1648 * When we can get the EDID, maybe it is the 1653 * When we can get the EDID, maybe it is the
@@ -1661,8 +1666,8 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1661 */ 1666 */
1662 if (edid == NULL && 1667 if (edid == NULL &&
1663 sdvo_priv->analog_ddc_bus && 1668 sdvo_priv->analog_ddc_bus &&
1664 !intel_analog_is_connected(intel_output->base.dev)) 1669 !intel_analog_is_connected(intel_encoder->base.dev))
1665 edid = drm_get_edid(&intel_output->base, 1670 edid = drm_get_edid(&intel_encoder->base,
1666 sdvo_priv->analog_ddc_bus); 1671 sdvo_priv->analog_ddc_bus);
1667 if (edid != NULL) { 1672 if (edid != NULL) {
1668 /* Don't report the output as connected if it's a DVI-I 1673 /* Don't report the output as connected if it's a DVI-I
@@ -1677,7 +1682,7 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1677 } 1682 }
1678 1683
1679 kfree(edid); 1684 kfree(edid);
1680 intel_output->base.display_info.raw_edid = NULL; 1685 intel_encoder->base.display_info.raw_edid = NULL;
1681 1686
1682 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) 1687 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1683 status = connector_status_disconnected; 1688 status = connector_status_disconnected;
@@ -1689,16 +1694,16 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
1689{ 1694{
1690 uint16_t response; 1695 uint16_t response;
1691 u8 status; 1696 u8 status;
1692 struct intel_output *intel_output = to_intel_output(connector); 1697 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1693 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1698 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1694 1699
1695 intel_sdvo_write_cmd(intel_output, 1700 intel_sdvo_write_cmd(intel_encoder,
1696 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); 1701 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1697 if (sdvo_priv->is_tv) { 1702 if (sdvo_priv->is_tv) {
1698 /* add 30ms delay when the output type is SDVO-TV */ 1703 /* add 30ms delay when the output type is SDVO-TV */
1699 mdelay(30); 1704 mdelay(30);
1700 } 1705 }
1701 status = intel_sdvo_read_response(intel_output, &response, 2); 1706 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1702 1707
1703 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); 1708 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1704 1709
@@ -1708,10 +1713,10 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
1708 if (response == 0) 1713 if (response == 0)
1709 return connector_status_disconnected; 1714 return connector_status_disconnected;
1710 1715
1711 if (intel_sdvo_multifunc_encoder(intel_output) && 1716 if (intel_sdvo_multifunc_encoder(intel_encoder) &&
1712 sdvo_priv->attached_output != response) { 1717 sdvo_priv->attached_output != response) {
1713 if (sdvo_priv->controlled_output != response && 1718 if (sdvo_priv->controlled_output != response &&
1714 intel_sdvo_output_setup(intel_output, response) != true) 1719 intel_sdvo_output_setup(intel_encoder, response) != true)
1715 return connector_status_unknown; 1720 return connector_status_unknown;
1716 sdvo_priv->attached_output = response; 1721 sdvo_priv->attached_output = response;
1717 } 1722 }
@@ -1720,12 +1725,12 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
1720 1725
1721static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1726static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1722{ 1727{
1723 struct intel_output *intel_output = to_intel_output(connector); 1728 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1724 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1729 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1725 int num_modes; 1730 int num_modes;
1726 1731
1727 /* set the bus switch and get the modes */ 1732 /* set the bus switch and get the modes */
1728 num_modes = intel_ddc_get_modes(intel_output); 1733 num_modes = intel_ddc_get_modes(intel_encoder);
1729 1734
1730 /* 1735 /*
1731 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1736 * Mac mini hack. On this device, the DVI-I connector shares one DDC
@@ -1735,17 +1740,17 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1735 */ 1740 */
1736 if (num_modes == 0 && 1741 if (num_modes == 0 &&
1737 sdvo_priv->analog_ddc_bus && 1742 sdvo_priv->analog_ddc_bus &&
1738 !intel_analog_is_connected(intel_output->base.dev)) { 1743 !intel_analog_is_connected(intel_encoder->base.dev)) {
1739 struct i2c_adapter *digital_ddc_bus; 1744 struct i2c_adapter *digital_ddc_bus;
1740 1745
1741 /* Switch to the analog ddc bus and try that 1746 /* Switch to the analog ddc bus and try that
1742 */ 1747 */
1743 digital_ddc_bus = intel_output->ddc_bus; 1748 digital_ddc_bus = intel_encoder->ddc_bus;
1744 intel_output->ddc_bus = sdvo_priv->analog_ddc_bus; 1749 intel_encoder->ddc_bus = sdvo_priv->analog_ddc_bus;
1745 1750
1746 (void) intel_ddc_get_modes(intel_output); 1751 (void) intel_ddc_get_modes(intel_encoder);
1747 1752
1748 intel_output->ddc_bus = digital_ddc_bus; 1753 intel_encoder->ddc_bus = digital_ddc_bus;
1749 } 1754 }
1750} 1755}
1751 1756
@@ -1816,7 +1821,7 @@ struct drm_display_mode sdvo_tv_modes[] = {
1816 1821
1817static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1822static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1818{ 1823{
1819 struct intel_output *output = to_intel_output(connector); 1824 struct intel_encoder *output = to_intel_encoder(connector);
1820 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1825 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1821 struct intel_sdvo_sdtv_resolution_request tv_res; 1826 struct intel_sdvo_sdtv_resolution_request tv_res;
1822 uint32_t reply = 0, format_map = 0; 1827 uint32_t reply = 0, format_map = 0;
@@ -1858,9 +1863,9 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1858 1863
1859static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1864static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1860{ 1865{
1861 struct intel_output *intel_output = to_intel_output(connector); 1866 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1862 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1867 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1863 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1868 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1864 struct drm_display_mode *newmode; 1869 struct drm_display_mode *newmode;
1865 1870
1866 /* 1871 /*
@@ -1868,7 +1873,7 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1868 * Assume that the preferred modes are 1873 * Assume that the preferred modes are
1869 * arranged in priority order. 1874 * arranged in priority order.
1870 */ 1875 */
1871 intel_ddc_get_modes(intel_output); 1876 intel_ddc_get_modes(intel_encoder);
1872 if (list_empty(&connector->probed_modes) == false) 1877 if (list_empty(&connector->probed_modes) == false)
1873 goto end; 1878 goto end;
1874 1879
@@ -1897,7 +1902,7 @@ end:
1897 1902
1898static int intel_sdvo_get_modes(struct drm_connector *connector) 1903static int intel_sdvo_get_modes(struct drm_connector *connector)
1899{ 1904{
1900 struct intel_output *output = to_intel_output(connector); 1905 struct intel_encoder *output = to_intel_encoder(connector);
1901 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1906 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1902 1907
1903 if (sdvo_priv->is_tv) 1908 if (sdvo_priv->is_tv)
@@ -1915,8 +1920,8 @@ static int intel_sdvo_get_modes(struct drm_connector *connector)
1915static 1920static
1916void intel_sdvo_destroy_enhance_property(struct drm_connector *connector) 1921void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1917{ 1922{
1918 struct intel_output *intel_output = to_intel_output(connector); 1923 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1919 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1924 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1920 struct drm_device *dev = connector->dev; 1925 struct drm_device *dev = connector->dev;
1921 1926
1922 if (sdvo_priv->is_tv) { 1927 if (sdvo_priv->is_tv) {
@@ -1953,13 +1958,13 @@ void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1953 1958
1954static void intel_sdvo_destroy(struct drm_connector *connector) 1959static void intel_sdvo_destroy(struct drm_connector *connector)
1955{ 1960{
1956 struct intel_output *intel_output = to_intel_output(connector); 1961 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1957 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1962 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1958 1963
1959 if (intel_output->i2c_bus) 1964 if (intel_encoder->i2c_bus)
1960 intel_i2c_destroy(intel_output->i2c_bus); 1965 intel_i2c_destroy(intel_encoder->i2c_bus);
1961 if (intel_output->ddc_bus) 1966 if (intel_encoder->ddc_bus)
1962 intel_i2c_destroy(intel_output->ddc_bus); 1967 intel_i2c_destroy(intel_encoder->ddc_bus);
1963 if (sdvo_priv->analog_ddc_bus) 1968 if (sdvo_priv->analog_ddc_bus)
1964 intel_i2c_destroy(sdvo_priv->analog_ddc_bus); 1969 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1965 1970
@@ -1977,7 +1982,7 @@ static void intel_sdvo_destroy(struct drm_connector *connector)
1977 drm_sysfs_connector_remove(connector); 1982 drm_sysfs_connector_remove(connector);
1978 drm_connector_cleanup(connector); 1983 drm_connector_cleanup(connector);
1979 1984
1980 kfree(intel_output); 1985 kfree(intel_encoder);
1981} 1986}
1982 1987
1983static int 1988static int
@@ -1985,9 +1990,9 @@ intel_sdvo_set_property(struct drm_connector *connector,
1985 struct drm_property *property, 1990 struct drm_property *property,
1986 uint64_t val) 1991 uint64_t val)
1987{ 1992{
1988 struct intel_output *intel_output = to_intel_output(connector); 1993 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1989 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1994 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1990 struct drm_encoder *encoder = &intel_output->enc; 1995 struct drm_encoder *encoder = &intel_encoder->enc;
1991 struct drm_crtc *crtc = encoder->crtc; 1996 struct drm_crtc *crtc = encoder->crtc;
1992 int ret = 0; 1997 int ret = 0;
1993 bool changed = false; 1998 bool changed = false;
@@ -2095,8 +2100,8 @@ intel_sdvo_set_property(struct drm_connector *connector,
2095 sdvo_priv->cur_brightness = temp_value; 2100 sdvo_priv->cur_brightness = temp_value;
2096 } 2101 }
2097 if (cmd) { 2102 if (cmd) {
2098 intel_sdvo_write_cmd(intel_output, cmd, &temp_value, 2); 2103 intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
2099 status = intel_sdvo_read_response(intel_output, 2104 status = intel_sdvo_read_response(intel_encoder,
2100 NULL, 0); 2105 NULL, 0);
2101 if (status != SDVO_CMD_STATUS_SUCCESS) { 2106 if (status != SDVO_CMD_STATUS_SUCCESS) {
2102 DRM_DEBUG_KMS("Incorrect SDVO command \n"); 2107 DRM_DEBUG_KMS("Incorrect SDVO command \n");
@@ -2191,7 +2196,7 @@ intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2191} 2196}
2192 2197
2193static bool 2198static bool
2194intel_sdvo_get_digital_encoding_mode(struct intel_output *output) 2199intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output)
2195{ 2200{
2196 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 2201 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2197 uint8_t status; 2202 uint8_t status;
@@ -2205,42 +2210,42 @@ intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
2205 return true; 2210 return true;
2206} 2211}
2207 2212
2208static struct intel_output * 2213static struct intel_encoder *
2209intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan) 2214intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
2210{ 2215{
2211 struct drm_device *dev = chan->drm_dev; 2216 struct drm_device *dev = chan->drm_dev;
2212 struct drm_connector *connector; 2217 struct drm_connector *connector;
2213 struct intel_output *intel_output = NULL; 2218 struct intel_encoder *intel_encoder = NULL;
2214 2219
2215 list_for_each_entry(connector, 2220 list_for_each_entry(connector,
2216 &dev->mode_config.connector_list, head) { 2221 &dev->mode_config.connector_list, head) {
2217 if (to_intel_output(connector)->ddc_bus == &chan->adapter) { 2222 if (to_intel_encoder(connector)->ddc_bus == &chan->adapter) {
2218 intel_output = to_intel_output(connector); 2223 intel_encoder = to_intel_encoder(connector);
2219 break; 2224 break;
2220 } 2225 }
2221 } 2226 }
2222 return intel_output; 2227 return intel_encoder;
2223} 2228}
2224 2229
2225static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, 2230static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2226 struct i2c_msg msgs[], int num) 2231 struct i2c_msg msgs[], int num)
2227{ 2232{
2228 struct intel_output *intel_output; 2233 struct intel_encoder *intel_encoder;
2229 struct intel_sdvo_priv *sdvo_priv; 2234 struct intel_sdvo_priv *sdvo_priv;
2230 struct i2c_algo_bit_data *algo_data; 2235 struct i2c_algo_bit_data *algo_data;
2231 const struct i2c_algorithm *algo; 2236 const struct i2c_algorithm *algo;
2232 2237
2233 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; 2238 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2234 intel_output = 2239 intel_encoder =
2235 intel_sdvo_chan_to_intel_output( 2240 intel_sdvo_chan_to_intel_encoder(
2236 (struct intel_i2c_chan *)(algo_data->data)); 2241 (struct intel_i2c_chan *)(algo_data->data));
2237 if (intel_output == NULL) 2242 if (intel_encoder == NULL)
2238 return -EINVAL; 2243 return -EINVAL;
2239 2244
2240 sdvo_priv = intel_output->dev_priv; 2245 sdvo_priv = intel_encoder->dev_priv;
2241 algo = intel_output->i2c_bus->algo; 2246 algo = intel_encoder->i2c_bus->algo;
2242 2247
2243 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus); 2248 intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
2244 return algo->master_xfer(i2c_adap, msgs, num); 2249 return algo->master_xfer(i2c_adap, msgs, num);
2245} 2250}
2246 2251
@@ -2249,12 +2254,12 @@ static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2249}; 2254};
2250 2255
2251static u8 2256static u8
2252intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device) 2257intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
2253{ 2258{
2254 struct drm_i915_private *dev_priv = dev->dev_private; 2259 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct sdvo_device_mapping *my_mapping, *other_mapping; 2260 struct sdvo_device_mapping *my_mapping, *other_mapping;
2256 2261
2257 if (output_device == SDVOB) { 2262 if (sdvo_reg == SDVOB) {
2258 my_mapping = &dev_priv->sdvo_mappings[0]; 2263 my_mapping = &dev_priv->sdvo_mappings[0];
2259 other_mapping = &dev_priv->sdvo_mappings[1]; 2264 other_mapping = &dev_priv->sdvo_mappings[1];
2260 } else { 2265 } else {
@@ -2279,7 +2284,7 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
2279 /* No SDVO device info is found for another DVO port, 2284 /* No SDVO device info is found for another DVO port,
2280 * so use mapping assumption we had before BIOS parsing. 2285 * so use mapping assumption we had before BIOS parsing.
2281 */ 2286 */
2282 if (output_device == SDVOB) 2287 if (sdvo_reg == SDVOB)
2283 return 0x70; 2288 return 0x70;
2284 else 2289 else
2285 return 0x72; 2290 return 0x72;
@@ -2305,15 +2310,15 @@ static struct dmi_system_id intel_sdvo_bad_tv[] = {
2305}; 2310};
2306 2311
2307static bool 2312static bool
2308intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) 2313intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
2309{ 2314{
2310 struct drm_connector *connector = &intel_output->base; 2315 struct drm_connector *connector = &intel_encoder->base;
2311 struct drm_encoder *encoder = &intel_output->enc; 2316 struct drm_encoder *encoder = &intel_encoder->enc;
2312 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 2317 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2313 bool ret = true, registered = false; 2318 bool ret = true, registered = false;
2314 2319
2315 sdvo_priv->is_tv = false; 2320 sdvo_priv->is_tv = false;
2316 intel_output->needs_tv_clock = false; 2321 intel_encoder->needs_tv_clock = false;
2317 sdvo_priv->is_lvds = false; 2322 sdvo_priv->is_lvds = false;
2318 2323
2319 if (device_is_registered(&connector->kdev)) { 2324 if (device_is_registered(&connector->kdev)) {
@@ -2331,16 +2336,16 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2331 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2336 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2332 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2337 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2333 2338
2334 if (intel_sdvo_get_supp_encode(intel_output, 2339 if (intel_sdvo_get_supp_encode(intel_encoder,
2335 &sdvo_priv->encode) && 2340 &sdvo_priv->encode) &&
2336 intel_sdvo_get_digital_encoding_mode(intel_output) && 2341 intel_sdvo_get_digital_encoding_mode(intel_encoder) &&
2337 sdvo_priv->is_hdmi) { 2342 sdvo_priv->is_hdmi) {
2338 /* enable hdmi encoding mode if supported */ 2343 /* enable hdmi encoding mode if supported */
2339 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI); 2344 intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
2340 intel_sdvo_set_colorimetry(intel_output, 2345 intel_sdvo_set_colorimetry(intel_encoder,
2341 SDVO_COLORIMETRY_RGB256); 2346 SDVO_COLORIMETRY_RGB256);
2342 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2347 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2343 intel_output->clone_mask = 2348 intel_encoder->clone_mask =
2344 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2349 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2345 (1 << INTEL_ANALOG_CLONE_BIT); 2350 (1 << INTEL_ANALOG_CLONE_BIT);
2346 } 2351 }
@@ -2351,21 +2356,21 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2351 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2356 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2352 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2357 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2353 sdvo_priv->is_tv = true; 2358 sdvo_priv->is_tv = true;
2354 intel_output->needs_tv_clock = true; 2359 intel_encoder->needs_tv_clock = true;
2355 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2360 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2356 } else if (flags & SDVO_OUTPUT_RGB0) { 2361 } else if (flags & SDVO_OUTPUT_RGB0) {
2357 2362
2358 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0; 2363 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2359 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2364 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2360 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2365 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2361 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2366 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2362 (1 << INTEL_ANALOG_CLONE_BIT); 2367 (1 << INTEL_ANALOG_CLONE_BIT);
2363 } else if (flags & SDVO_OUTPUT_RGB1) { 2368 } else if (flags & SDVO_OUTPUT_RGB1) {
2364 2369
2365 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1; 2370 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2366 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2371 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2367 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2372 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2368 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2373 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2369 (1 << INTEL_ANALOG_CLONE_BIT); 2374 (1 << INTEL_ANALOG_CLONE_BIT);
2370 } else if (flags & SDVO_OUTPUT_CVBS0) { 2375 } else if (flags & SDVO_OUTPUT_CVBS0) {
2371 2376
@@ -2373,15 +2378,15 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2373 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2378 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2374 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2379 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2375 sdvo_priv->is_tv = true; 2380 sdvo_priv->is_tv = true;
2376 intel_output->needs_tv_clock = true; 2381 intel_encoder->needs_tv_clock = true;
2377 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2382 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2378 } else if (flags & SDVO_OUTPUT_LVDS0) { 2383 } else if (flags & SDVO_OUTPUT_LVDS0) {
2379 2384
2380 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0; 2385 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2381 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2386 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2382 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2387 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2383 sdvo_priv->is_lvds = true; 2388 sdvo_priv->is_lvds = true;
2384 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) | 2389 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2385 (1 << INTEL_SDVO_LVDS_CLONE_BIT); 2390 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2386 } else if (flags & SDVO_OUTPUT_LVDS1) { 2391 } else if (flags & SDVO_OUTPUT_LVDS1) {
2387 2392
@@ -2389,7 +2394,7 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2389 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2394 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2390 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2395 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2391 sdvo_priv->is_lvds = true; 2396 sdvo_priv->is_lvds = true;
2392 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) | 2397 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2393 (1 << INTEL_SDVO_LVDS_CLONE_BIT); 2398 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2394 } else { 2399 } else {
2395 2400
@@ -2402,7 +2407,7 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2402 bytes[0], bytes[1]); 2407 bytes[0], bytes[1]);
2403 ret = false; 2408 ret = false;
2404 } 2409 }
2405 intel_output->crtc_mask = (1 << 0) | (1 << 1); 2410 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2406 2411
2407 if (ret && registered) 2412 if (ret && registered)
2408 ret = drm_sysfs_connector_add(connector) == 0 ? true : false; 2413 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
@@ -2414,18 +2419,18 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2414 2419
2415static void intel_sdvo_tv_create_property(struct drm_connector *connector) 2420static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2416{ 2421{
2417 struct intel_output *intel_output = to_intel_output(connector); 2422 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2418 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 2423 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2419 struct intel_sdvo_tv_format format; 2424 struct intel_sdvo_tv_format format;
2420 uint32_t format_map, i; 2425 uint32_t format_map, i;
2421 uint8_t status; 2426 uint8_t status;
2422 2427
2423 intel_sdvo_set_target_output(intel_output, 2428 intel_sdvo_set_target_output(intel_encoder,
2424 sdvo_priv->controlled_output); 2429 sdvo_priv->controlled_output);
2425 2430
2426 intel_sdvo_write_cmd(intel_output, 2431 intel_sdvo_write_cmd(intel_encoder,
2427 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); 2432 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2428 status = intel_sdvo_read_response(intel_output, 2433 status = intel_sdvo_read_response(intel_encoder,
2429 &format, sizeof(format)); 2434 &format, sizeof(format));
2430 if (status != SDVO_CMD_STATUS_SUCCESS) 2435 if (status != SDVO_CMD_STATUS_SUCCESS)
2431 return; 2436 return;
@@ -2463,16 +2468,16 @@ static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2463 2468
2464static void intel_sdvo_create_enhance_property(struct drm_connector *connector) 2469static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2465{ 2470{
2466 struct intel_output *intel_output = to_intel_output(connector); 2471 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2467 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 2472 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2468 struct intel_sdvo_enhancements_reply sdvo_data; 2473 struct intel_sdvo_enhancements_reply sdvo_data;
2469 struct drm_device *dev = connector->dev; 2474 struct drm_device *dev = connector->dev;
2470 uint8_t status; 2475 uint8_t status;
2471 uint16_t response, data_value[2]; 2476 uint16_t response, data_value[2];
2472 2477
2473 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2478 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2474 NULL, 0); 2479 NULL, 0);
2475 status = intel_sdvo_read_response(intel_output, &sdvo_data, 2480 status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
2476 sizeof(sdvo_data)); 2481 sizeof(sdvo_data));
2477 if (status != SDVO_CMD_STATUS_SUCCESS) { 2482 if (status != SDVO_CMD_STATUS_SUCCESS) {
2478 DRM_DEBUG_KMS(" incorrect response is returned\n"); 2483 DRM_DEBUG_KMS(" incorrect response is returned\n");
@@ -2488,18 +2493,18 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2488 * property 2493 * property
2489 */ 2494 */
2490 if (sdvo_data.overscan_h) { 2495 if (sdvo_data.overscan_h) {
2491 intel_sdvo_write_cmd(intel_output, 2496 intel_sdvo_write_cmd(intel_encoder,
2492 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0); 2497 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2493 status = intel_sdvo_read_response(intel_output, 2498 status = intel_sdvo_read_response(intel_encoder,
2494 &data_value, 4); 2499 &data_value, 4);
2495 if (status != SDVO_CMD_STATUS_SUCCESS) { 2500 if (status != SDVO_CMD_STATUS_SUCCESS) {
2496 DRM_DEBUG_KMS("Incorrect SDVO max " 2501 DRM_DEBUG_KMS("Incorrect SDVO max "
2497 "h_overscan\n"); 2502 "h_overscan\n");
2498 return; 2503 return;
2499 } 2504 }
2500 intel_sdvo_write_cmd(intel_output, 2505 intel_sdvo_write_cmd(intel_encoder,
2501 SDVO_CMD_GET_OVERSCAN_H, NULL, 0); 2506 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2502 status = intel_sdvo_read_response(intel_output, 2507 status = intel_sdvo_read_response(intel_encoder,
2503 &response, 2); 2508 &response, 2);
2504 if (status != SDVO_CMD_STATUS_SUCCESS) { 2509 if (status != SDVO_CMD_STATUS_SUCCESS) {
2505 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n"); 2510 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
@@ -2529,18 +2534,18 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2529 data_value[0], data_value[1], response); 2534 data_value[0], data_value[1], response);
2530 } 2535 }
2531 if (sdvo_data.overscan_v) { 2536 if (sdvo_data.overscan_v) {
2532 intel_sdvo_write_cmd(intel_output, 2537 intel_sdvo_write_cmd(intel_encoder,
2533 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0); 2538 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2534 status = intel_sdvo_read_response(intel_output, 2539 status = intel_sdvo_read_response(intel_encoder,
2535 &data_value, 4); 2540 &data_value, 4);
2536 if (status != SDVO_CMD_STATUS_SUCCESS) { 2541 if (status != SDVO_CMD_STATUS_SUCCESS) {
2537 DRM_DEBUG_KMS("Incorrect SDVO max " 2542 DRM_DEBUG_KMS("Incorrect SDVO max "
2538 "v_overscan\n"); 2543 "v_overscan\n");
2539 return; 2544 return;
2540 } 2545 }
2541 intel_sdvo_write_cmd(intel_output, 2546 intel_sdvo_write_cmd(intel_encoder,
2542 SDVO_CMD_GET_OVERSCAN_V, NULL, 0); 2547 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2543 status = intel_sdvo_read_response(intel_output, 2548 status = intel_sdvo_read_response(intel_encoder,
2544 &response, 2); 2549 &response, 2);
2545 if (status != SDVO_CMD_STATUS_SUCCESS) { 2550 if (status != SDVO_CMD_STATUS_SUCCESS) {
2546 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n"); 2551 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
@@ -2570,17 +2575,17 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2570 data_value[0], data_value[1], response); 2575 data_value[0], data_value[1], response);
2571 } 2576 }
2572 if (sdvo_data.position_h) { 2577 if (sdvo_data.position_h) {
2573 intel_sdvo_write_cmd(intel_output, 2578 intel_sdvo_write_cmd(intel_encoder,
2574 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0); 2579 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2575 status = intel_sdvo_read_response(intel_output, 2580 status = intel_sdvo_read_response(intel_encoder,
2576 &data_value, 4); 2581 &data_value, 4);
2577 if (status != SDVO_CMD_STATUS_SUCCESS) { 2582 if (status != SDVO_CMD_STATUS_SUCCESS) {
2578 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n"); 2583 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2579 return; 2584 return;
2580 } 2585 }
2581 intel_sdvo_write_cmd(intel_output, 2586 intel_sdvo_write_cmd(intel_encoder,
2582 SDVO_CMD_GET_POSITION_H, NULL, 0); 2587 SDVO_CMD_GET_POSITION_H, NULL, 0);
2583 status = intel_sdvo_read_response(intel_output, 2588 status = intel_sdvo_read_response(intel_encoder,
2584 &response, 2); 2589 &response, 2);
2585 if (status != SDVO_CMD_STATUS_SUCCESS) { 2590 if (status != SDVO_CMD_STATUS_SUCCESS) {
2586 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n"); 2591 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
@@ -2601,17 +2606,17 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2601 data_value[0], data_value[1], response); 2606 data_value[0], data_value[1], response);
2602 } 2607 }
2603 if (sdvo_data.position_v) { 2608 if (sdvo_data.position_v) {
2604 intel_sdvo_write_cmd(intel_output, 2609 intel_sdvo_write_cmd(intel_encoder,
2605 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0); 2610 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2606 status = intel_sdvo_read_response(intel_output, 2611 status = intel_sdvo_read_response(intel_encoder,
2607 &data_value, 4); 2612 &data_value, 4);
2608 if (status != SDVO_CMD_STATUS_SUCCESS) { 2613 if (status != SDVO_CMD_STATUS_SUCCESS) {
2609 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n"); 2614 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2610 return; 2615 return;
2611 } 2616 }
2612 intel_sdvo_write_cmd(intel_output, 2617 intel_sdvo_write_cmd(intel_encoder,
2613 SDVO_CMD_GET_POSITION_V, NULL, 0); 2618 SDVO_CMD_GET_POSITION_V, NULL, 0);
2614 status = intel_sdvo_read_response(intel_output, 2619 status = intel_sdvo_read_response(intel_encoder,
2615 &response, 2); 2620 &response, 2);
2616 if (status != SDVO_CMD_STATUS_SUCCESS) { 2621 if (status != SDVO_CMD_STATUS_SUCCESS) {
2617 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n"); 2622 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
@@ -2634,17 +2639,17 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2634 } 2639 }
2635 if (sdvo_priv->is_tv) { 2640 if (sdvo_priv->is_tv) {
2636 if (sdvo_data.saturation) { 2641 if (sdvo_data.saturation) {
2637 intel_sdvo_write_cmd(intel_output, 2642 intel_sdvo_write_cmd(intel_encoder,
2638 SDVO_CMD_GET_MAX_SATURATION, NULL, 0); 2643 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2639 status = intel_sdvo_read_response(intel_output, 2644 status = intel_sdvo_read_response(intel_encoder,
2640 &data_value, 4); 2645 &data_value, 4);
2641 if (status != SDVO_CMD_STATUS_SUCCESS) { 2646 if (status != SDVO_CMD_STATUS_SUCCESS) {
2642 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n"); 2647 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2643 return; 2648 return;
2644 } 2649 }
2645 intel_sdvo_write_cmd(intel_output, 2650 intel_sdvo_write_cmd(intel_encoder,
2646 SDVO_CMD_GET_SATURATION, NULL, 0); 2651 SDVO_CMD_GET_SATURATION, NULL, 0);
2647 status = intel_sdvo_read_response(intel_output, 2652 status = intel_sdvo_read_response(intel_encoder,
2648 &response, 2); 2653 &response, 2);
2649 if (status != SDVO_CMD_STATUS_SUCCESS) { 2654 if (status != SDVO_CMD_STATUS_SUCCESS) {
2650 DRM_DEBUG_KMS("Incorrect SDVO get sat\n"); 2655 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
@@ -2666,17 +2671,17 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2666 data_value[0], data_value[1], response); 2671 data_value[0], data_value[1], response);
2667 } 2672 }
2668 if (sdvo_data.contrast) { 2673 if (sdvo_data.contrast) {
2669 intel_sdvo_write_cmd(intel_output, 2674 intel_sdvo_write_cmd(intel_encoder,
2670 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0); 2675 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2671 status = intel_sdvo_read_response(intel_output, 2676 status = intel_sdvo_read_response(intel_encoder,
2672 &data_value, 4); 2677 &data_value, 4);
2673 if (status != SDVO_CMD_STATUS_SUCCESS) { 2678 if (status != SDVO_CMD_STATUS_SUCCESS) {
2674 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n"); 2679 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2675 return; 2680 return;
2676 } 2681 }
2677 intel_sdvo_write_cmd(intel_output, 2682 intel_sdvo_write_cmd(intel_encoder,
2678 SDVO_CMD_GET_CONTRAST, NULL, 0); 2683 SDVO_CMD_GET_CONTRAST, NULL, 0);
2679 status = intel_sdvo_read_response(intel_output, 2684 status = intel_sdvo_read_response(intel_encoder,
2680 &response, 2); 2685 &response, 2);
2681 if (status != SDVO_CMD_STATUS_SUCCESS) { 2686 if (status != SDVO_CMD_STATUS_SUCCESS) {
2682 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n"); 2687 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
@@ -2697,17 +2702,17 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2697 data_value[0], data_value[1], response); 2702 data_value[0], data_value[1], response);
2698 } 2703 }
2699 if (sdvo_data.hue) { 2704 if (sdvo_data.hue) {
2700 intel_sdvo_write_cmd(intel_output, 2705 intel_sdvo_write_cmd(intel_encoder,
2701 SDVO_CMD_GET_MAX_HUE, NULL, 0); 2706 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2702 status = intel_sdvo_read_response(intel_output, 2707 status = intel_sdvo_read_response(intel_encoder,
2703 &data_value, 4); 2708 &data_value, 4);
2704 if (status != SDVO_CMD_STATUS_SUCCESS) { 2709 if (status != SDVO_CMD_STATUS_SUCCESS) {
2705 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n"); 2710 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2706 return; 2711 return;
2707 } 2712 }
2708 intel_sdvo_write_cmd(intel_output, 2713 intel_sdvo_write_cmd(intel_encoder,
2709 SDVO_CMD_GET_HUE, NULL, 0); 2714 SDVO_CMD_GET_HUE, NULL, 0);
2710 status = intel_sdvo_read_response(intel_output, 2715 status = intel_sdvo_read_response(intel_encoder,
2711 &response, 2); 2716 &response, 2);
2712 if (status != SDVO_CMD_STATUS_SUCCESS) { 2717 if (status != SDVO_CMD_STATUS_SUCCESS) {
2713 DRM_DEBUG_KMS("Incorrect SDVO get hue\n"); 2718 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
@@ -2730,17 +2735,17 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2730 } 2735 }
2731 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { 2736 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2732 if (sdvo_data.brightness) { 2737 if (sdvo_data.brightness) {
2733 intel_sdvo_write_cmd(intel_output, 2738 intel_sdvo_write_cmd(intel_encoder,
2734 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0); 2739 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2735 status = intel_sdvo_read_response(intel_output, 2740 status = intel_sdvo_read_response(intel_encoder,
2736 &data_value, 4); 2741 &data_value, 4);
2737 if (status != SDVO_CMD_STATUS_SUCCESS) { 2742 if (status != SDVO_CMD_STATUS_SUCCESS) {
2738 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n"); 2743 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2739 return; 2744 return;
2740 } 2745 }
2741 intel_sdvo_write_cmd(intel_output, 2746 intel_sdvo_write_cmd(intel_encoder,
2742 SDVO_CMD_GET_BRIGHTNESS, NULL, 0); 2747 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2743 status = intel_sdvo_read_response(intel_output, 2748 status = intel_sdvo_read_response(intel_encoder,
2744 &response, 2); 2749 &response, 2);
2745 if (status != SDVO_CMD_STATUS_SUCCESS) { 2750 if (status != SDVO_CMD_STATUS_SUCCESS) {
2746 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n"); 2751 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
@@ -2765,81 +2770,81 @@ static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2765 return; 2770 return;
2766} 2771}
2767 2772
2768bool intel_sdvo_init(struct drm_device *dev, int output_device) 2773bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2769{ 2774{
2770 struct drm_i915_private *dev_priv = dev->dev_private; 2775 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct drm_connector *connector; 2776 struct drm_connector *connector;
2772 struct intel_output *intel_output; 2777 struct intel_encoder *intel_encoder;
2773 struct intel_sdvo_priv *sdvo_priv; 2778 struct intel_sdvo_priv *sdvo_priv;
2774 2779
2775 u8 ch[0x40]; 2780 u8 ch[0x40];
2776 int i; 2781 int i;
2777 2782
2778 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); 2783 intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2779 if (!intel_output) { 2784 if (!intel_encoder) {
2780 return false; 2785 return false;
2781 } 2786 }
2782 2787
2783 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1); 2788 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
2784 sdvo_priv->output_device = output_device; 2789 sdvo_priv->sdvo_reg = sdvo_reg;
2785 2790
2786 intel_output->dev_priv = sdvo_priv; 2791 intel_encoder->dev_priv = sdvo_priv;
2787 intel_output->type = INTEL_OUTPUT_SDVO; 2792 intel_encoder->type = INTEL_OUTPUT_SDVO;
2788 2793
2789 /* setup the DDC bus. */ 2794 /* setup the DDC bus. */
2790 if (output_device == SDVOB) 2795 if (sdvo_reg == SDVOB)
2791 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB"); 2796 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2792 else 2797 else
2793 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); 2798 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2794 2799
2795 if (!intel_output->i2c_bus) 2800 if (!intel_encoder->i2c_bus)
2796 goto err_inteloutput; 2801 goto err_inteloutput;
2797 2802
2798 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device); 2803 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
2799 2804
2800 /* Save the bit-banging i2c functionality for use by the DDC wrapper */ 2805 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2801 intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality; 2806 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
2802 2807
2803 /* Read the regs to test if we can talk to the device */ 2808 /* Read the regs to test if we can talk to the device */
2804 for (i = 0; i < 0x40; i++) { 2809 for (i = 0; i < 0x40; i++) {
2805 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { 2810 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
2806 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2811 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2807 output_device == SDVOB ? 'B' : 'C'); 2812 sdvo_reg == SDVOB ? 'B' : 'C');
2808 goto err_i2c; 2813 goto err_i2c;
2809 } 2814 }
2810 } 2815 }
2811 2816
2812 /* setup the DDC bus. */ 2817 /* setup the DDC bus. */
2813 if (output_device == SDVOB) { 2818 if (sdvo_reg == SDVOB) {
2814 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS"); 2819 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2815 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, 2820 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2816 "SDVOB/VGA DDC BUS"); 2821 "SDVOB/VGA DDC BUS");
2817 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; 2822 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2818 } else { 2823 } else {
2819 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS"); 2824 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2820 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA, 2825 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2821 "SDVOC/VGA DDC BUS"); 2826 "SDVOC/VGA DDC BUS");
2822 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; 2827 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2823 } 2828 }
2824 2829
2825 if (intel_output->ddc_bus == NULL) 2830 if (intel_encoder->ddc_bus == NULL)
2826 goto err_i2c; 2831 goto err_i2c;
2827 2832
2828 /* Wrap with our custom algo which switches to DDC mode */ 2833 /* Wrap with our custom algo which switches to DDC mode */
2829 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; 2834 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2830 2835
2831 /* In default case sdvo lvds is false */ 2836 /* In default case sdvo lvds is false */
2832 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps); 2837 intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
2833 2838
2834 if (intel_sdvo_output_setup(intel_output, 2839 if (intel_sdvo_output_setup(intel_encoder,
2835 sdvo_priv->caps.output_flags) != true) { 2840 sdvo_priv->caps.output_flags) != true) {
2836 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2841 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2837 output_device == SDVOB ? 'B' : 'C'); 2842 sdvo_reg == SDVOB ? 'B' : 'C');
2838 goto err_i2c; 2843 goto err_i2c;
2839 } 2844 }
2840 2845
2841 2846
2842 connector = &intel_output->base; 2847 connector = &intel_encoder->base;
2843 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs, 2848 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2844 connector->connector_type); 2849 connector->connector_type);
2845 2850
@@ -2848,12 +2853,12 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2848 connector->doublescan_allowed = 0; 2853 connector->doublescan_allowed = 0;
2849 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2854 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2850 2855
2851 drm_encoder_init(dev, &intel_output->enc, 2856 drm_encoder_init(dev, &intel_encoder->enc,
2852 &intel_sdvo_enc_funcs, intel_output->enc.encoder_type); 2857 &intel_sdvo_enc_funcs, intel_encoder->enc.encoder_type);
2853 2858
2854 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); 2859 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2855 2860
2856 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); 2861 drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc);
2857 if (sdvo_priv->is_tv) 2862 if (sdvo_priv->is_tv)
2858 intel_sdvo_tv_create_property(connector); 2863 intel_sdvo_tv_create_property(connector);
2859 2864
@@ -2865,9 +2870,9 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2865 intel_sdvo_select_ddc_bus(sdvo_priv); 2870 intel_sdvo_select_ddc_bus(sdvo_priv);
2866 2871
2867 /* Set the input timing to the screen. Assume always input 0. */ 2872 /* Set the input timing to the screen. Assume always input 0. */
2868 intel_sdvo_set_target_input(intel_output, true, false); 2873 intel_sdvo_set_target_input(intel_encoder, true, false);
2869 2874
2870 intel_sdvo_get_input_pixel_clock_range(intel_output, 2875 intel_sdvo_get_input_pixel_clock_range(intel_encoder,
2871 &sdvo_priv->pixel_clock_min, 2876 &sdvo_priv->pixel_clock_min,
2872 &sdvo_priv->pixel_clock_max); 2877 &sdvo_priv->pixel_clock_max);
2873 2878
@@ -2894,12 +2899,12 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
2894err_i2c: 2899err_i2c:
2895 if (sdvo_priv->analog_ddc_bus != NULL) 2900 if (sdvo_priv->analog_ddc_bus != NULL)
2896 intel_i2c_destroy(sdvo_priv->analog_ddc_bus); 2901 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2897 if (intel_output->ddc_bus != NULL) 2902 if (intel_encoder->ddc_bus != NULL)
2898 intel_i2c_destroy(intel_output->ddc_bus); 2903 intel_i2c_destroy(intel_encoder->ddc_bus);
2899 if (intel_output->i2c_bus != NULL) 2904 if (intel_encoder->i2c_bus != NULL)
2900 intel_i2c_destroy(intel_output->i2c_bus); 2905 intel_i2c_destroy(intel_encoder->i2c_bus);
2901err_inteloutput: 2906err_inteloutput:
2902 kfree(intel_output); 2907 kfree(intel_encoder);
2903 2908
2904 return false; 2909 return false;
2905} 2910}
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 552ec110b741..d7d39b2327df 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -921,8 +921,8 @@ intel_tv_save(struct drm_connector *connector)
921{ 921{
922 struct drm_device *dev = connector->dev; 922 struct drm_device *dev = connector->dev;
923 struct drm_i915_private *dev_priv = dev->dev_private; 923 struct drm_i915_private *dev_priv = dev->dev_private;
924 struct intel_output *intel_output = to_intel_output(connector); 924 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
925 struct intel_tv_priv *tv_priv = intel_output->dev_priv; 925 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
926 int i; 926 int i;
927 927
928 tv_priv->save_TV_H_CTL_1 = I915_READ(TV_H_CTL_1); 928 tv_priv->save_TV_H_CTL_1 = I915_READ(TV_H_CTL_1);
@@ -971,8 +971,8 @@ intel_tv_restore(struct drm_connector *connector)
971{ 971{
972 struct drm_device *dev = connector->dev; 972 struct drm_device *dev = connector->dev;
973 struct drm_i915_private *dev_priv = dev->dev_private; 973 struct drm_i915_private *dev_priv = dev->dev_private;
974 struct intel_output *intel_output = to_intel_output(connector); 974 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
975 struct intel_tv_priv *tv_priv = intel_output->dev_priv; 975 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
976 struct drm_crtc *crtc = connector->encoder->crtc; 976 struct drm_crtc *crtc = connector->encoder->crtc;
977 struct intel_crtc *intel_crtc; 977 struct intel_crtc *intel_crtc;
978 int i; 978 int i;
@@ -1068,9 +1068,9 @@ intel_tv_mode_lookup (char *tv_format)
1068} 1068}
1069 1069
1070static const struct tv_mode * 1070static const struct tv_mode *
1071intel_tv_mode_find (struct intel_output *intel_output) 1071intel_tv_mode_find (struct intel_encoder *intel_encoder)
1072{ 1072{
1073 struct intel_tv_priv *tv_priv = intel_output->dev_priv; 1073 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
1074 1074
1075 return intel_tv_mode_lookup(tv_priv->tv_format); 1075 return intel_tv_mode_lookup(tv_priv->tv_format);
1076} 1076}
@@ -1078,8 +1078,8 @@ intel_tv_mode_find (struct intel_output *intel_output)
1078static enum drm_mode_status 1078static enum drm_mode_status
1079intel_tv_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) 1079intel_tv_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode)
1080{ 1080{
1081 struct intel_output *intel_output = to_intel_output(connector); 1081 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1082 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); 1082 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder);
1083 1083
1084 /* Ensure TV refresh is close to desired refresh */ 1084 /* Ensure TV refresh is close to desired refresh */
1085 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) 1085 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
@@ -1095,8 +1095,8 @@ intel_tv_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
1095{ 1095{
1096 struct drm_device *dev = encoder->dev; 1096 struct drm_device *dev = encoder->dev;
1097 struct drm_mode_config *drm_config = &dev->mode_config; 1097 struct drm_mode_config *drm_config = &dev->mode_config;
1098 struct intel_output *intel_output = enc_to_intel_output(encoder); 1098 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1099 const struct tv_mode *tv_mode = intel_tv_mode_find (intel_output); 1099 const struct tv_mode *tv_mode = intel_tv_mode_find (intel_encoder);
1100 struct drm_encoder *other_encoder; 1100 struct drm_encoder *other_encoder;
1101 1101
1102 if (!tv_mode) 1102 if (!tv_mode)
@@ -1121,9 +1121,9 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1121 struct drm_i915_private *dev_priv = dev->dev_private; 1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122 struct drm_crtc *crtc = encoder->crtc; 1122 struct drm_crtc *crtc = encoder->crtc;
1123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1124 struct intel_output *intel_output = enc_to_intel_output(encoder); 1124 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1125 struct intel_tv_priv *tv_priv = intel_output->dev_priv; 1125 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
1126 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); 1126 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder);
1127 u32 tv_ctl; 1127 u32 tv_ctl;
1128 u32 hctl1, hctl2, hctl3; 1128 u32 hctl1, hctl2, hctl3;
1129 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; 1129 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
@@ -1360,9 +1360,9 @@ static const struct drm_display_mode reported_modes[] = {
1360 * \return false if TV is disconnected. 1360 * \return false if TV is disconnected.
1361 */ 1361 */
1362static int 1362static int
1363intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output) 1363intel_tv_detect_type (struct drm_crtc *crtc, struct intel_encoder *intel_encoder)
1364{ 1364{
1365 struct drm_encoder *encoder = &intel_output->enc; 1365 struct drm_encoder *encoder = &intel_encoder->enc;
1366 struct drm_device *dev = encoder->dev; 1366 struct drm_device *dev = encoder->dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private; 1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 unsigned long irqflags; 1368 unsigned long irqflags;
@@ -1441,9 +1441,9 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
1441 */ 1441 */
1442static void intel_tv_find_better_format(struct drm_connector *connector) 1442static void intel_tv_find_better_format(struct drm_connector *connector)
1443{ 1443{
1444 struct intel_output *intel_output = to_intel_output(connector); 1444 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1445 struct intel_tv_priv *tv_priv = intel_output->dev_priv; 1445 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
1446 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); 1446 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder);
1447 int i; 1447 int i;
1448 1448
1449 if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == 1449 if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) ==
@@ -1475,9 +1475,9 @@ intel_tv_detect(struct drm_connector *connector)
1475{ 1475{
1476 struct drm_crtc *crtc; 1476 struct drm_crtc *crtc;
1477 struct drm_display_mode mode; 1477 struct drm_display_mode mode;
1478 struct intel_output *intel_output = to_intel_output(connector); 1478 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1479 struct intel_tv_priv *tv_priv = intel_output->dev_priv; 1479 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
1480 struct drm_encoder *encoder = &intel_output->enc; 1480 struct drm_encoder *encoder = &intel_encoder->enc;
1481 int dpms_mode; 1481 int dpms_mode;
1482 int type = tv_priv->type; 1482 int type = tv_priv->type;
1483 1483
@@ -1485,12 +1485,12 @@ intel_tv_detect(struct drm_connector *connector)
1485 drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V); 1485 drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V);
1486 1486
1487 if (encoder->crtc && encoder->crtc->enabled) { 1487 if (encoder->crtc && encoder->crtc->enabled) {
1488 type = intel_tv_detect_type(encoder->crtc, intel_output); 1488 type = intel_tv_detect_type(encoder->crtc, intel_encoder);
1489 } else { 1489 } else {
1490 crtc = intel_get_load_detect_pipe(intel_output, &mode, &dpms_mode); 1490 crtc = intel_get_load_detect_pipe(intel_encoder, &mode, &dpms_mode);
1491 if (crtc) { 1491 if (crtc) {
1492 type = intel_tv_detect_type(crtc, intel_output); 1492 type = intel_tv_detect_type(crtc, intel_encoder);
1493 intel_release_load_detect_pipe(intel_output, dpms_mode); 1493 intel_release_load_detect_pipe(intel_encoder, dpms_mode);
1494 } else 1494 } else
1495 type = -1; 1495 type = -1;
1496 } 1496 }
@@ -1525,8 +1525,8 @@ static void
1525intel_tv_chose_preferred_modes(struct drm_connector *connector, 1525intel_tv_chose_preferred_modes(struct drm_connector *connector,
1526 struct drm_display_mode *mode_ptr) 1526 struct drm_display_mode *mode_ptr)
1527{ 1527{
1528 struct intel_output *intel_output = to_intel_output(connector); 1528 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1529 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); 1529 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder);
1530 1530
1531 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480) 1531 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1532 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED; 1532 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
@@ -1550,8 +1550,8 @@ static int
1550intel_tv_get_modes(struct drm_connector *connector) 1550intel_tv_get_modes(struct drm_connector *connector)
1551{ 1551{
1552 struct drm_display_mode *mode_ptr; 1552 struct drm_display_mode *mode_ptr;
1553 struct intel_output *intel_output = to_intel_output(connector); 1553 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1554 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output); 1554 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder);
1555 int j, count = 0; 1555 int j, count = 0;
1556 u64 tmp; 1556 u64 tmp;
1557 1557
@@ -1604,11 +1604,11 @@ intel_tv_get_modes(struct drm_connector *connector)
1604static void 1604static void
1605intel_tv_destroy (struct drm_connector *connector) 1605intel_tv_destroy (struct drm_connector *connector)
1606{ 1606{
1607 struct intel_output *intel_output = to_intel_output(connector); 1607 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1608 1608
1609 drm_sysfs_connector_remove(connector); 1609 drm_sysfs_connector_remove(connector);
1610 drm_connector_cleanup(connector); 1610 drm_connector_cleanup(connector);
1611 kfree(intel_output); 1611 kfree(intel_encoder);
1612} 1612}
1613 1613
1614 1614
@@ -1617,9 +1617,9 @@ intel_tv_set_property(struct drm_connector *connector, struct drm_property *prop
1617 uint64_t val) 1617 uint64_t val)
1618{ 1618{
1619 struct drm_device *dev = connector->dev; 1619 struct drm_device *dev = connector->dev;
1620 struct intel_output *intel_output = to_intel_output(connector); 1620 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1621 struct intel_tv_priv *tv_priv = intel_output->dev_priv; 1621 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
1622 struct drm_encoder *encoder = &intel_output->enc; 1622 struct drm_encoder *encoder = &intel_encoder->enc;
1623 struct drm_crtc *crtc = encoder->crtc; 1623 struct drm_crtc *crtc = encoder->crtc;
1624 int ret = 0; 1624 int ret = 0;
1625 bool changed = false; 1625 bool changed = false;
@@ -1740,7 +1740,7 @@ intel_tv_init(struct drm_device *dev)
1740{ 1740{
1741 struct drm_i915_private *dev_priv = dev->dev_private; 1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 struct drm_connector *connector; 1742 struct drm_connector *connector;
1743 struct intel_output *intel_output; 1743 struct intel_encoder *intel_encoder;
1744 struct intel_tv_priv *tv_priv; 1744 struct intel_tv_priv *tv_priv;
1745 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1745 u32 tv_dac_on, tv_dac_off, save_tv_dac;
1746 char **tv_format_names; 1746 char **tv_format_names;
@@ -1780,28 +1780,28 @@ intel_tv_init(struct drm_device *dev)
1780 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) 1780 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1781 return; 1781 return;
1782 1782
1783 intel_output = kzalloc(sizeof(struct intel_output) + 1783 intel_encoder = kzalloc(sizeof(struct intel_encoder) +
1784 sizeof(struct intel_tv_priv), GFP_KERNEL); 1784 sizeof(struct intel_tv_priv), GFP_KERNEL);
1785 if (!intel_output) { 1785 if (!intel_encoder) {
1786 return; 1786 return;
1787 } 1787 }
1788 1788
1789 connector = &intel_output->base; 1789 connector = &intel_encoder->base;
1790 1790
1791 drm_connector_init(dev, connector, &intel_tv_connector_funcs, 1791 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1792 DRM_MODE_CONNECTOR_SVIDEO); 1792 DRM_MODE_CONNECTOR_SVIDEO);
1793 1793
1794 drm_encoder_init(dev, &intel_output->enc, &intel_tv_enc_funcs, 1794 drm_encoder_init(dev, &intel_encoder->enc, &intel_tv_enc_funcs,
1795 DRM_MODE_ENCODER_TVDAC); 1795 DRM_MODE_ENCODER_TVDAC);
1796 1796
1797 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); 1797 drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc);
1798 tv_priv = (struct intel_tv_priv *)(intel_output + 1); 1798 tv_priv = (struct intel_tv_priv *)(intel_encoder + 1);
1799 intel_output->type = INTEL_OUTPUT_TVOUT; 1799 intel_encoder->type = INTEL_OUTPUT_TVOUT;
1800 intel_output->crtc_mask = (1 << 0) | (1 << 1); 1800 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1801 intel_output->clone_mask = (1 << INTEL_TV_CLONE_BIT); 1801 intel_encoder->clone_mask = (1 << INTEL_TV_CLONE_BIT);
1802 intel_output->enc.possible_crtcs = ((1 << 0) | (1 << 1)); 1802 intel_encoder->enc.possible_crtcs = ((1 << 0) | (1 << 1));
1803 intel_output->enc.possible_clones = (1 << INTEL_OUTPUT_TVOUT); 1803 intel_encoder->enc.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
1804 intel_output->dev_priv = tv_priv; 1804 intel_encoder->dev_priv = tv_priv;
1805 tv_priv->type = DRM_MODE_CONNECTOR_Unknown; 1805 tv_priv->type = DRM_MODE_CONNECTOR_Unknown;
1806 1806
1807 /* BIOS margin values */ 1807 /* BIOS margin values */
@@ -1812,7 +1812,7 @@ intel_tv_init(struct drm_device *dev)
1812 1812
1813 tv_priv->tv_format = kstrdup(tv_modes[initial_mode].name, GFP_KERNEL); 1813 tv_priv->tv_format = kstrdup(tv_modes[initial_mode].name, GFP_KERNEL);
1814 1814
1815 drm_encoder_helper_add(&intel_output->enc, &intel_tv_helper_funcs); 1815 drm_encoder_helper_add(&intel_encoder->enc, &intel_tv_helper_funcs);
1816 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); 1816 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1817 connector->interlace_allowed = false; 1817 connector->interlace_allowed = false;
1818 connector->doublescan_allowed = false; 1818 connector->doublescan_allowed = false;
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 7f0d807a0d0d..453df3f6053f 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -22,7 +22,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
22 nv50_cursor.o nv50_display.o nv50_fbcon.o \ 22 nv50_cursor.o nv50_display.o nv50_fbcon.o \
23 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ 23 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
24 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ 24 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \
25 nv17_gpio.o 25 nv17_gpio.o nv50_gpio.o
26 26
27nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o 27nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
28nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o 28nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index b5a9336a2e88..abc382a9918b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -2573,48 +2573,34 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2573 * each GPIO according to various values listed in each entry 2573 * each GPIO according to various values listed in each entry
2574 */ 2574 */
2575 2575
2576 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 2576 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2577 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 2577 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
2578 const uint8_t *gpio_table = &bios->data[bios->dcb.gpio_table_ptr];
2579 const uint8_t *gpio_entry;
2580 int i; 2578 int i;
2581 2579
2582 if (!iexec->execute) 2580 if (dev_priv->card_type != NV_50) {
2583 return 1; 2581 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
2584 2582 return -ENODEV;
2585 if (bios->dcb.version != 0x40) {
2586 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
2587 return 0;
2588 }
2589
2590 if (!bios->dcb.gpio_table_ptr) {
2591 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
2592 return 0;
2593 } 2583 }
2594 2584
2595 gpio_entry = gpio_table + gpio_table[1]; 2585 if (!iexec->execute)
2596 for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) { 2586 return 1;
2597 uint32_t entry = ROM32(gpio_entry[0]), r, s, v;
2598 int line = (entry & 0x0000001f);
2599 2587
2600 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry); 2588 for (i = 0; i < bios->dcb.gpio.entries; i++) {
2589 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
2590 uint32_t r, s, v;
2601 2591
2602 if ((entry & 0x0000ff00) == 0x0000ff00) 2592 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
2603 continue;
2604 2593
2605 r = nv50_gpio_reg[line >> 3]; 2594 nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default);
2606 s = (line & 0x07) << 2;
2607 v = bios_rd32(bios, r) & ~(0x00000003 << s);
2608 if (entry & 0x01000000)
2609 v |= (((entry & 0x60000000) >> 29) ^ 2) << s;
2610 else
2611 v |= (((entry & 0x18000000) >> 27) ^ 2) << s;
2612 bios_wr32(bios, r, v);
2613 2595
2614 r = nv50_gpio_ctl[line >> 4]; 2596 /* The NVIDIA binary driver doesn't appear to actually do
2615 s = (line & 0x0f); 2597 * any of this, my VBIOS does however.
2598 */
2599 /* Not a clue, needs de-magicing */
2600 r = nv50_gpio_ctl[gpio->line >> 4];
2601 s = (gpio->line & 0x0f);
2616 v = bios_rd32(bios, r) & ~(0x00010001 << s); 2602 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2617 switch ((entry & 0x06000000) >> 25) { 2603 switch ((gpio->entry & 0x06000000) >> 25) {
2618 case 1: 2604 case 1:
2619 v |= (0x00000001 << s); 2605 v |= (0x00000001 << s);
2620 break; 2606 break;
@@ -3198,7 +3184,6 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int
3198 struct nvbios *bios = &dev_priv->vbios; 3184 struct nvbios *bios = &dev_priv->vbios;
3199 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3185 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3200 uint16_t scriptptr = 0, clktable; 3186 uint16_t scriptptr = 0, clktable;
3201 uint8_t clktableptr = 0;
3202 3187
3203 /* 3188 /*
3204 * For now we assume version 3.0 table - g80 support will need some 3189 * For now we assume version 3.0 table - g80 support will need some
@@ -3217,26 +3202,29 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int
3217 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3202 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3218 break; 3203 break;
3219 case LVDS_RESET: 3204 case LVDS_RESET:
3205 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3206 if (dcbent->or == 4)
3207 clktable += 8;
3208
3220 if (dcbent->lvdsconf.use_straps_for_mode) { 3209 if (dcbent->lvdsconf.use_straps_for_mode) {
3221 if (bios->fp.dual_link) 3210 if (bios->fp.dual_link)
3222 clktableptr += 2; 3211 clktable += 4;
3223 if (bios->fp.BITbit1) 3212 if (bios->fp.if_is_24bit)
3224 clktableptr++; 3213 clktable += 2;
3225 } else { 3214 } else {
3226 /* using EDID */ 3215 /* using EDID */
3227 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3216 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3228 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
3229 3217
3230 if (bios->fp.dual_link) { 3218 if (bios->fp.dual_link) {
3231 clktableptr += 2; 3219 clktable += 4;
3232 fallbackcmpval *= 2; 3220 cmpval_24bit <<= 1;
3233 } 3221 }
3234 if (fallbackcmpval & fallback) 3222
3235 clktableptr++; 3223 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3224 clktable += 2;
3236 } 3225 }
3237 3226
3238 /* adding outputset * 8 may not be correct */ 3227 clktable = ROM16(bios->data[clktable]);
3239 clktable = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
3240 if (!clktable) { 3228 if (!clktable) {
3241 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3229 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3242 return -ENOENT; 3230 return -ENOENT;
@@ -3638,37 +3626,40 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
3638 *if_is_24bit = bios->data[lvdsofs] & 16; 3626 *if_is_24bit = bios->data[lvdsofs] & 16;
3639 break; 3627 break;
3640 case 0x30: 3628 case 0x30:
3641 /* 3629 case 0x40:
3642 * My money would be on there being a 24 bit interface bit in
3643 * this table, but I have no example of a laptop bios with a
3644 * 24 bit panel to confirm that. Hence we shout loudly if any
3645 * bit other than bit 0 is set (I've not even seen bit 1)
3646 */
3647 if (bios->data[lvdsofs] > 1)
3648 NV_ERROR(dev,
3649 "You have a very unusual laptop display; please report it\n");
3650 /* 3630 /*
3651 * No sign of the "power off for reset" or "reset for panel 3631 * No sign of the "power off for reset" or "reset for panel
3652 * on" bits, but it's safer to assume we should 3632 * on" bits, but it's safer to assume we should
3653 */ 3633 */
3654 bios->fp.power_off_for_reset = true; 3634 bios->fp.power_off_for_reset = true;
3655 bios->fp.reset_after_pclk_change = true; 3635 bios->fp.reset_after_pclk_change = true;
3636
3656 /* 3637 /*
3657 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 3638 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3658 * over-written, and BITbit1 isn't used 3639 * over-written, and if_is_24bit isn't used
3659 */ 3640 */
3660 bios->fp.dual_link = bios->data[lvdsofs] & 1; 3641 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3661 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3662 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3663 break;
3664 case 0x40:
3665 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3666 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 3642 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3667 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 3643 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3668 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 3644 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3669 break; 3645 break;
3670 } 3646 }
3671 3647
3648 /* Dell Latitude D620 reports a too-high value for the dual-link
3649 * transition freq, causing us to program the panel incorrectly.
3650 *
3651 * It doesn't appear the VBIOS actually uses its transition freq
3652 * (90000kHz), instead it uses the "Number of LVDS channels" field
3653 * out of the panel ID structure (http://www.spwg.org/).
3654 *
3655 * For the moment, a quirk will do :)
3656 */
3657 if ((dev->pdev->device == 0x01d7) &&
3658 (dev->pdev->subsystem_vendor == 0x1028) &&
3659 (dev->pdev->subsystem_device == 0x01c2)) {
3660 bios->fp.duallink_transition_clk = 80000;
3661 }
3662
3672 /* set dual_link flag for EDID case */ 3663 /* set dual_link flag for EDID case */
3673 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 3664 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3674 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 3665 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
@@ -5077,25 +5068,25 @@ parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5077 gpio->tag = tag; 5068 gpio->tag = tag;
5078 gpio->line = line; 5069 gpio->line = line;
5079 gpio->invert = flags != 4; 5070 gpio->invert = flags != 4;
5071 gpio->entry = ent;
5080} 5072}
5081 5073
5082static void 5074static void
5083parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5075parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5084{ 5076{
5077 uint32_t entry = ROM32(bios->data[offset]);
5085 struct dcb_gpio_entry *gpio; 5078 struct dcb_gpio_entry *gpio;
5086 uint32_t ent = ROM32(bios->data[offset]);
5087 uint8_t line = ent & 0x1f,
5088 tag = ent >> 8 & 0xff;
5089 5079
5090 if (tag == 0xff) 5080 if ((entry & 0x0000ff00) == 0x0000ff00)
5091 return; 5081 return;
5092 5082
5093 gpio = new_gpio_entry(bios); 5083 gpio = new_gpio_entry(bios);
5094 5084 gpio->tag = (entry & 0x0000ff00) >> 8;
5095 /* Currently unused, we may need more fields parsed at some 5085 gpio->line = (entry & 0x0000001f) >> 0;
5096 * point. */ 5086 gpio->state_default = (entry & 0x01000000) >> 24;
5097 gpio->tag = tag; 5087 gpio->state[0] = (entry & 0x18000000) >> 27;
5098 gpio->line = line; 5088 gpio->state[1] = (entry & 0x60000000) >> 29;
5089 gpio->entry = entry;
5099} 5090}
5100 5091
5101static void 5092static void
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 4f88e6924d27..c0d7b0a3ece0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -49,6 +49,9 @@ struct dcb_gpio_entry {
49 enum dcb_gpio_tag tag; 49 enum dcb_gpio_tag tag;
50 int line; 50 int line;
51 bool invert; 51 bool invert;
52 uint32_t entry;
53 uint8_t state_default;
54 uint8_t state[2];
52}; 55};
53 56
54struct dcb_gpio_table { 57struct dcb_gpio_table {
@@ -267,7 +270,6 @@ struct nvbios {
267 bool reset_after_pclk_change; 270 bool reset_after_pclk_change;
268 bool dual_link; 271 bool dual_link;
269 bool link_c_increment; 272 bool link_c_increment;
270 bool BITbit1;
271 bool if_is_24bit; 273 bool if_is_24bit;
272 int duallink_transition_clk; 274 int duallink_transition_clk;
273 uint8_t strapless_is_24bit; 275 uint8_t strapless_is_24bit;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 9042dd7fb058..957d17629840 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -72,7 +72,7 @@ nouveau_bo_fixup_align(struct drm_device *dev,
72 * many small buffers. 72 * many small buffers.
73 */ 73 */
74 if (dev_priv->card_type == NV_50) { 74 if (dev_priv->card_type == NV_50) {
75 uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15; 75 uint32_t block_size = dev_priv->vram_size >> 15;
76 int i; 76 int i;
77 77
78 switch (tile_flags) { 78 switch (tile_flags) {
@@ -154,7 +154,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
154 154
155 nvbo->placement.fpfn = 0; 155 nvbo->placement.fpfn = 0;
156 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; 156 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
157 nouveau_bo_placement_set(nvbo, flags); 157 nouveau_bo_placement_set(nvbo, flags, 0);
158 158
159 nvbo->channel = chan; 159 nvbo->channel = chan;
160 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, 160 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
@@ -173,26 +173,33 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
173 return 0; 173 return 0;
174} 174}
175 175
176static void
177set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
178{
179 *n = 0;
180
181 if (type & TTM_PL_FLAG_VRAM)
182 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
183 if (type & TTM_PL_FLAG_TT)
184 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
185 if (type & TTM_PL_FLAG_SYSTEM)
186 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
187}
188
176void 189void
177nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype) 190nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
178{ 191{
179 int n = 0; 192 struct ttm_placement *pl = &nvbo->placement;
180 193 uint32_t flags = TTM_PL_MASK_CACHING |
181 if (memtype & TTM_PL_FLAG_VRAM) 194 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
182 nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING; 195
183 if (memtype & TTM_PL_FLAG_TT) 196 pl->placement = nvbo->placements;
184 nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; 197 set_placement_list(nvbo->placements, &pl->num_placement,
185 if (memtype & TTM_PL_FLAG_SYSTEM) 198 type, flags);
186 nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; 199
187 nvbo->placement.placement = nvbo->placements; 200 pl->busy_placement = nvbo->busy_placements;
188 nvbo->placement.busy_placement = nvbo->placements; 201 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
189 nvbo->placement.num_placement = n; 202 type | busy, flags);
190 nvbo->placement.num_busy_placement = n;
191
192 if (nvbo->pin_refcnt) {
193 while (n--)
194 nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT;
195 }
196} 203}
197 204
198int 205int
@@ -200,7 +207,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
200{ 207{
201 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 208 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
202 struct ttm_buffer_object *bo = &nvbo->bo; 209 struct ttm_buffer_object *bo = &nvbo->bo;
203 int ret, i; 210 int ret;
204 211
205 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { 212 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
206 NV_ERROR(nouveau_bdev(bo->bdev)->dev, 213 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
@@ -216,9 +223,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
216 if (ret) 223 if (ret)
217 goto out; 224 goto out;
218 225
219 nouveau_bo_placement_set(nvbo, memtype); 226 nouveau_bo_placement_set(nvbo, memtype, 0);
220 for (i = 0; i < nvbo->placement.num_placement; i++)
221 nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
222 227
223 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 228 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
224 if (ret == 0) { 229 if (ret == 0) {
@@ -245,7 +250,7 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo)
245{ 250{
246 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 251 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
247 struct ttm_buffer_object *bo = &nvbo->bo; 252 struct ttm_buffer_object *bo = &nvbo->bo;
248 int ret, i; 253 int ret;
249 254
250 if (--nvbo->pin_refcnt) 255 if (--nvbo->pin_refcnt)
251 return 0; 256 return 0;
@@ -254,8 +259,7 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo)
254 if (ret) 259 if (ret)
255 return ret; 260 return ret;
256 261
257 for (i = 0; i < nvbo->placement.num_placement; i++) 262 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
258 nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
259 263
260 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 264 ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
261 if (ret == 0) { 265 if (ret == 0) {
@@ -396,8 +400,8 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
396 man->io_addr = NULL; 400 man->io_addr = NULL;
397 man->io_offset = drm_get_resource_start(dev, 1); 401 man->io_offset = drm_get_resource_start(dev, 1);
398 man->io_size = drm_get_resource_len(dev, 1); 402 man->io_size = drm_get_resource_len(dev, 1);
399 if (man->io_size > nouveau_mem_fb_amount(dev)) 403 if (man->io_size > dev_priv->vram_size)
400 man->io_size = nouveau_mem_fb_amount(dev); 404 man->io_size = dev_priv->vram_size;
401 405
402 man->gpu_offset = dev_priv->vm_vram_base; 406 man->gpu_offset = dev_priv->vm_vram_base;
403 break; 407 break;
@@ -440,10 +444,11 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
440 444
441 switch (bo->mem.mem_type) { 445 switch (bo->mem.mem_type) {
442 case TTM_PL_VRAM: 446 case TTM_PL_VRAM:
443 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT); 447 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
448 TTM_PL_FLAG_SYSTEM);
444 break; 449 break;
445 default: 450 default:
446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); 451 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
447 break; 452 break;
448 } 453 }
449 454
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 6dfb425cbae9..1fc57ef58295 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -142,7 +142,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
142 GFP_KERNEL); 142 GFP_KERNEL);
143 if (!dev_priv->fifos[channel]) 143 if (!dev_priv->fifos[channel])
144 return -ENOMEM; 144 return -ENOMEM;
145 dev_priv->fifo_alloc_count++;
146 chan = dev_priv->fifos[channel]; 145 chan = dev_priv->fifos[channel];
147 INIT_LIST_HEAD(&chan->nvsw.vbl_wait); 146 INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
148 INIT_LIST_HEAD(&chan->fence.pending); 147 INIT_LIST_HEAD(&chan->fence.pending);
@@ -321,7 +320,6 @@ nouveau_channel_free(struct nouveau_channel *chan)
321 iounmap(chan->user); 320 iounmap(chan->user);
322 321
323 dev_priv->fifos[chan->id] = NULL; 322 dev_priv->fifos[chan->id] = NULL;
324 dev_priv->fifo_alloc_count--;
325 kfree(chan); 323 kfree(chan);
326} 324}
327 325
diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
index 8ff9ef5d4b47..a251886a0ce6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c
+++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c
@@ -137,10 +137,9 @@ nouveau_debugfs_memory_info(struct seq_file *m, void *data)
137{ 137{
138 struct drm_info_node *node = (struct drm_info_node *) m->private; 138 struct drm_info_node *node = (struct drm_info_node *) m->private;
139 struct drm_minor *minor = node->minor; 139 struct drm_minor *minor = node->minor;
140 struct drm_device *dev = minor->dev; 140 struct drm_nouveau_private *dev_priv = minor->dev->dev_private;
141 141
142 seq_printf(m, "VRAM total: %dKiB\n", 142 seq_printf(m, "VRAM total: %dKiB\n", (int)(dev_priv->vram_size >> 10));
143 (int)(nouveau_mem_fb_amount(dev) >> 10));
144 return 0; 143 return 0;
145} 144}
146 145
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index f954ad93e81f..deeb21c6865c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -483,7 +483,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
483 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT); 483 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
484 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT); 484 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
485 485
486 for (;;) { 486 for (i = 0; i < 16; i++) {
487 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000); 487 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
488 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl); 488 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
489 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000); 489 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
@@ -502,6 +502,12 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
502 break; 502 break;
503 } 503 }
504 504
505 if (i == 16) {
506 NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
507 ret = -EREMOTEIO;
508 goto out;
509 }
510
505 if (cmd & 1) { 511 if (cmd & 1) {
506 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { 512 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
507 ret = -EREMOTEIO; 513 ret = -EREMOTEIO;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index d8b559011777..ace630aa89e1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -76,6 +76,7 @@ struct nouveau_bo {
76 struct ttm_buffer_object bo; 76 struct ttm_buffer_object bo;
77 struct ttm_placement placement; 77 struct ttm_placement placement;
78 u32 placements[3]; 78 u32 placements[3];
79 u32 busy_placements[3];
79 struct ttm_bo_kmap_obj kmap; 80 struct ttm_bo_kmap_obj kmap;
80 struct list_head head; 81 struct list_head head;
81 82
@@ -519,6 +520,7 @@ struct drm_nouveau_private {
519 520
520 struct workqueue_struct *wq; 521 struct workqueue_struct *wq;
521 struct work_struct irq_work; 522 struct work_struct irq_work;
523 struct work_struct hpd_work;
522 524
523 struct list_head vbl_waiting; 525 struct list_head vbl_waiting;
524 526
@@ -533,7 +535,6 @@ struct drm_nouveau_private {
533 535
534 struct fb_info *fbdev_info; 536 struct fb_info *fbdev_info;
535 537
536 int fifo_alloc_count;
537 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 538 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
538 539
539 struct nouveau_engine engine; 540 struct nouveau_engine engine;
@@ -553,12 +554,6 @@ struct drm_nouveau_private {
553 uint32_t ramro_offset; 554 uint32_t ramro_offset;
554 uint32_t ramro_size; 555 uint32_t ramro_size;
555 556
556 /* base physical addresses */
557 uint64_t fb_phys;
558 uint64_t fb_available_size;
559 uint64_t fb_mappable_pages;
560 uint64_t fb_aper_free;
561
562 struct { 557 struct {
563 enum { 558 enum {
564 NOUVEAU_GART_NONE = 0, 559 NOUVEAU_GART_NONE = 0,
@@ -572,10 +567,6 @@ struct drm_nouveau_private {
572 struct nouveau_gpuobj *sg_ctxdma; 567 struct nouveau_gpuobj *sg_ctxdma;
573 struct page *sg_dummy_page; 568 struct page *sg_dummy_page;
574 dma_addr_t sg_dummy_bus; 569 dma_addr_t sg_dummy_bus;
575
576 /* nottm hack */
577 struct drm_ttm_backend *sg_be;
578 unsigned long sg_handle;
579 } gart_info; 570 } gart_info;
580 571
581 /* nv10-nv40 tiling regions */ 572 /* nv10-nv40 tiling regions */
@@ -584,6 +575,16 @@ struct drm_nouveau_private {
584 spinlock_t lock; 575 spinlock_t lock;
585 } tile; 576 } tile;
586 577
578 /* VRAM/fb configuration */
579 uint64_t vram_size;
580 uint64_t vram_sys_base;
581
582 uint64_t fb_phys;
583 uint64_t fb_available_size;
584 uint64_t fb_mappable_pages;
585 uint64_t fb_aper_free;
586 int fb_mtrr;
587
587 /* G8x/G9x virtual address space */ 588 /* G8x/G9x virtual address space */
588 uint64_t vm_gart_base; 589 uint64_t vm_gart_base;
589 uint64_t vm_gart_size; 590 uint64_t vm_gart_size;
@@ -592,10 +593,6 @@ struct drm_nouveau_private {
592 uint64_t vm_end; 593 uint64_t vm_end;
593 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 594 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
594 int vm_vram_pt_nr; 595 int vm_vram_pt_nr;
595 uint64_t vram_sys_base;
596
597 /* the mtrr covering the FB */
598 int fb_mtrr;
599 596
600 struct mem_block *ramin_heap; 597 struct mem_block *ramin_heap;
601 598
@@ -614,11 +611,7 @@ struct drm_nouveau_private {
614 uint32_t dac_users[4]; 611 uint32_t dac_users[4];
615 612
616 struct nouveau_suspend_resume { 613 struct nouveau_suspend_resume {
617 uint32_t fifo_mode;
618 uint32_t graph_ctx_control;
619 uint32_t graph_state;
620 uint32_t *ramin_copy; 614 uint32_t *ramin_copy;
621 uint64_t ramin_size;
622 } susres; 615 } susres;
623 616
624 struct backlight_device *backlight; 617 struct backlight_device *backlight;
@@ -717,7 +710,7 @@ extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
717 struct drm_file *, int tail); 710 struct drm_file *, int tail);
718extern void nouveau_mem_takedown(struct mem_block **heap); 711extern void nouveau_mem_takedown(struct mem_block **heap);
719extern void nouveau_mem_free_block(struct mem_block *); 712extern void nouveau_mem_free_block(struct mem_block *);
720extern uint64_t nouveau_mem_fb_amount(struct drm_device *); 713extern int nouveau_mem_detect(struct drm_device *dev);
721extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); 714extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
722extern int nouveau_mem_init(struct drm_device *); 715extern int nouveau_mem_init(struct drm_device *);
723extern int nouveau_mem_init_agp(struct drm_device *); 716extern int nouveau_mem_init_agp(struct drm_device *);
@@ -1124,7 +1117,8 @@ extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1124extern int nouveau_bo_unpin(struct nouveau_bo *); 1117extern int nouveau_bo_unpin(struct nouveau_bo *);
1125extern int nouveau_bo_map(struct nouveau_bo *); 1118extern int nouveau_bo_map(struct nouveau_bo *);
1126extern void nouveau_bo_unmap(struct nouveau_bo *); 1119extern void nouveau_bo_unmap(struct nouveau_bo *);
1127extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype); 1120extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1121 uint32_t busy);
1128extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1122extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1129extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1123extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1130extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1124extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
@@ -1168,6 +1162,10 @@ extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1168int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1162int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1169int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1163int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1170 1164
1165/* nv50_gpio.c */
1166int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1167int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1168
1171#ifndef ioread32_native 1169#ifndef ioread32_native
1172#ifdef __BIG_ENDIAN 1170#ifdef __BIG_ENDIAN
1173#define ioread16_native ioread16be 1171#define ioread16_native ioread16be
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index bc4a24029ed1..9f28b94e479b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -47,6 +47,7 @@ struct nouveau_encoder {
47 47
48 union { 48 union {
49 struct { 49 struct {
50 int mc_unknown;
50 int dpcd_version; 51 int dpcd_version;
51 int link_nr; 52 int link_nr;
52 int link_bw; 53 int link_bw;
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 0d22f66f1c79..1bc0b38a5167 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -180,40 +180,35 @@ nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains,
180{ 180{
181 struct nouveau_bo *nvbo = gem->driver_private; 181 struct nouveau_bo *nvbo = gem->driver_private;
182 struct ttm_buffer_object *bo = &nvbo->bo; 182 struct ttm_buffer_object *bo = &nvbo->bo;
183 uint64_t flags; 183 uint32_t domains = valid_domains &
184 (write_domains ? write_domains : read_domains);
185 uint32_t pref_flags = 0, valid_flags = 0;
184 186
185 if (!valid_domains || (!read_domains && !write_domains)) 187 if (!domains)
186 return -EINVAL; 188 return -EINVAL;
187 189
188 if (write_domains) { 190 if (valid_domains & NOUVEAU_GEM_DOMAIN_VRAM)
189 if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && 191 valid_flags |= TTM_PL_FLAG_VRAM;
190 (write_domains & NOUVEAU_GEM_DOMAIN_VRAM)) 192
191 flags = TTM_PL_FLAG_VRAM; 193 if (valid_domains & NOUVEAU_GEM_DOMAIN_GART)
192 else 194 valid_flags |= TTM_PL_FLAG_TT;
193 if ((valid_domains & NOUVEAU_GEM_DOMAIN_GART) && 195
194 (write_domains & NOUVEAU_GEM_DOMAIN_GART)) 196 if ((domains & NOUVEAU_GEM_DOMAIN_VRAM) &&
195 flags = TTM_PL_FLAG_TT; 197 bo->mem.mem_type == TTM_PL_VRAM)
196 else 198 pref_flags |= TTM_PL_FLAG_VRAM;
197 return -EINVAL; 199
198 } else { 200 else if ((domains & NOUVEAU_GEM_DOMAIN_GART) &&
199 if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && 201 bo->mem.mem_type == TTM_PL_TT)
200 (read_domains & NOUVEAU_GEM_DOMAIN_VRAM) && 202 pref_flags |= TTM_PL_FLAG_TT;
201 bo->mem.mem_type == TTM_PL_VRAM) 203
202 flags = TTM_PL_FLAG_VRAM; 204 else if (domains & NOUVEAU_GEM_DOMAIN_VRAM)
203 else 205 pref_flags |= TTM_PL_FLAG_VRAM;
204 if ((valid_domains & NOUVEAU_GEM_DOMAIN_GART) && 206
205 (read_domains & NOUVEAU_GEM_DOMAIN_GART) && 207 else
206 bo->mem.mem_type == TTM_PL_TT) 208 pref_flags |= TTM_PL_FLAG_TT;
207 flags = TTM_PL_FLAG_TT; 209
208 else 210 nouveau_bo_placement_set(nvbo, pref_flags, valid_flags);
209 if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) &&
210 (read_domains & NOUVEAU_GEM_DOMAIN_VRAM))
211 flags = TTM_PL_FLAG_VRAM;
212 else
213 flags = TTM_PL_FLAG_TT;
214 }
215 211
216 nouveau_bo_placement_set(nvbo, flags);
217 return 0; 212 return 0;
218} 213}
219 214
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 2bd59a92fee5..13e73cee4c44 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -51,6 +51,7 @@ nouveau_irq_preinstall(struct drm_device *dev)
51 51
52 if (dev_priv->card_type == NV_50) { 52 if (dev_priv->card_type == NV_50) {
53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); 53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
54 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
54 INIT_LIST_HEAD(&dev_priv->vbl_waiting); 55 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
55 } 56 }
56} 57}
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 2dc09dbd817d..775a7017af64 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -347,6 +347,20 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
347 return -EBUSY; 347 return -EBUSY;
348 } 348 }
349 349
350 nv_wr32(dev, 0x100c80, 0x00040001);
351 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
352 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
353 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
354 return -EBUSY;
355 }
356
357 nv_wr32(dev, 0x100c80, 0x00060001);
358 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
359 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
360 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
361 return -EBUSY;
362 }
363
350 return 0; 364 return 0;
351} 365}
352 366
@@ -387,6 +401,20 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
387 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 401 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
388 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); 402 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
389 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); 403 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
404 return;
405 }
406
407 nv_wr32(dev, 0x100c80, 0x00040001);
408 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
409 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
410 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
411 return;
412 }
413
414 nv_wr32(dev, 0x100c80, 0x00060001);
415 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
416 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
417 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
390 } 418 }
391} 419}
392 420
@@ -449,9 +477,30 @@ void nouveau_mem_close(struct drm_device *dev)
449 } 477 }
450} 478}
451 479
452/*XXX won't work on BSD because of pci_read_config_dword */
453static uint32_t 480static uint32_t
454nouveau_mem_fb_amount_igp(struct drm_device *dev) 481nouveau_mem_detect_nv04(struct drm_device *dev)
482{
483 uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);
484
485 if (boot0 & 0x00000100)
486 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
487
488 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
489 case NV04_BOOT_0_RAM_AMOUNT_32MB:
490 return 32 * 1024 * 1024;
491 case NV04_BOOT_0_RAM_AMOUNT_16MB:
492 return 16 * 1024 * 1024;
493 case NV04_BOOT_0_RAM_AMOUNT_8MB:
494 return 8 * 1024 * 1024;
495 case NV04_BOOT_0_RAM_AMOUNT_4MB:
496 return 4 * 1024 * 1024;
497 }
498
499 return 0;
500}
501
502static uint32_t
503nouveau_mem_detect_nforce(struct drm_device *dev)
455{ 504{
456 struct drm_nouveau_private *dev_priv = dev->dev_private; 505 struct drm_nouveau_private *dev_priv = dev->dev_private;
457 struct pci_dev *bridge; 506 struct pci_dev *bridge;
@@ -463,11 +512,11 @@ nouveau_mem_fb_amount_igp(struct drm_device *dev)
463 return 0; 512 return 0;
464 } 513 }
465 514
466 if (dev_priv->flags&NV_NFORCE) { 515 if (dev_priv->flags & NV_NFORCE) {
467 pci_read_config_dword(bridge, 0x7C, &mem); 516 pci_read_config_dword(bridge, 0x7C, &mem);
468 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; 517 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
469 } else 518 } else
470 if (dev_priv->flags&NV_NFORCE2) { 519 if (dev_priv->flags & NV_NFORCE2) {
471 pci_read_config_dword(bridge, 0x84, &mem); 520 pci_read_config_dword(bridge, 0x84, &mem);
472 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; 521 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
473 } 522 }
@@ -477,50 +526,32 @@ nouveau_mem_fb_amount_igp(struct drm_device *dev)
477} 526}
478 527
479/* returns the amount of FB ram in bytes */ 528/* returns the amount of FB ram in bytes */
480uint64_t nouveau_mem_fb_amount(struct drm_device *dev) 529int
530nouveau_mem_detect(struct drm_device *dev)
481{ 531{
482 struct drm_nouveau_private *dev_priv = dev->dev_private; 532 struct drm_nouveau_private *dev_priv = dev->dev_private;
483 uint32_t boot0; 533
484 534 if (dev_priv->card_type == NV_04) {
485 switch (dev_priv->card_type) { 535 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
486 case NV_04: 536 } else
487 boot0 = nv_rd32(dev, NV03_BOOT_0); 537 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
488 if (boot0 & 0x00000100) 538 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
489 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; 539 } else {
490 540 dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);
491 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) { 541 dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;
492 case NV04_BOOT_0_RAM_AMOUNT_32MB: 542 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
493 return 32 * 1024 * 1024; 543 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
494 case NV04_BOOT_0_RAM_AMOUNT_16MB:
495 return 16 * 1024 * 1024;
496 case NV04_BOOT_0_RAM_AMOUNT_8MB:
497 return 8 * 1024 * 1024;
498 case NV04_BOOT_0_RAM_AMOUNT_4MB:
499 return 4 * 1024 * 1024;
500 }
501 break;
502 case NV_10:
503 case NV_20:
504 case NV_30:
505 case NV_40:
506 case NV_50:
507 default:
508 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
509 return nouveau_mem_fb_amount_igp(dev);
510 } else {
511 uint64_t mem;
512 mem = (nv_rd32(dev, NV04_FIFO_DATA) &
513 NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
514 NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
515 return mem * 1024 * 1024;
516 }
517 break;
518 } 544 }
519 545
520 NV_ERROR(dev, 546 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
521 "Unable to detect video ram size. Please report your setup to " 547 if (dev_priv->vram_sys_base) {
522 DRIVER_EMAIL "\n"); 548 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
523 return 0; 549 dev_priv->vram_sys_base);
550 }
551
552 if (dev_priv->vram_size)
553 return 0;
554 return -ENOMEM;
524} 555}
525 556
526#if __OS_HAS_AGP 557#if __OS_HAS_AGP
@@ -631,15 +662,12 @@ nouveau_mem_init(struct drm_device *dev)
631 spin_lock_init(&dev_priv->ttm.bo_list_lock); 662 spin_lock_init(&dev_priv->ttm.bo_list_lock);
632 spin_lock_init(&dev_priv->tile.lock); 663 spin_lock_init(&dev_priv->tile.lock);
633 664
634 dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); 665 dev_priv->fb_available_size = dev_priv->vram_size;
635
636 dev_priv->fb_mappable_pages = dev_priv->fb_available_size; 666 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
637 if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1)) 667 if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1))
638 dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1); 668 dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1);
639 dev_priv->fb_mappable_pages >>= PAGE_SHIFT; 669 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
640 670
641 NV_INFO(dev, "%d MiB VRAM\n", (int)(dev_priv->fb_available_size >> 20));
642
643 /* remove reserved space at end of vram from available amount */ 671 /* remove reserved space at end of vram from available amount */
644 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; 672 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
645 dev_priv->fb_aper_free = dev_priv->fb_available_size; 673 dev_priv->fb_aper_free = dev_priv->fb_available_size;
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 86785b8d42ed..1d6ee8b55154 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -172,6 +172,24 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
172 } 172 }
173 dev_priv->engine.instmem.finish_access(nvbe->dev); 173 dev_priv->engine.instmem.finish_access(nvbe->dev);
174 174
175 if (dev_priv->card_type == NV_50) {
176 nv_wr32(dev, 0x100c80, 0x00050001);
177 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
178 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
179 NV_ERROR(dev, "0x100c80 = 0x%08x\n",
180 nv_rd32(dev, 0x100c80));
181 return -EBUSY;
182 }
183
184 nv_wr32(dev, 0x100c80, 0x00000001);
185 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
186 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
187 NV_ERROR(dev, "0x100c80 = 0x%08x\n",
188 nv_rd32(dev, 0x100c80));
189 return -EBUSY;
190 }
191 }
192
175 nvbe->bound = false; 193 nvbe->bound = false;
176 return 0; 194 return 0;
177} 195}
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 10656a6be8e6..e1710640a278 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -341,7 +341,7 @@ nouveau_card_init_channel(struct drm_device *dev)
341 341
342 gpuobj = NULL; 342 gpuobj = NULL;
343 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, 343 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
344 0, nouveau_mem_fb_amount(dev), 344 0, dev_priv->vram_size,
345 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM, 345 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
346 &gpuobj); 346 &gpuobj);
347 if (ret) 347 if (ret)
@@ -427,6 +427,10 @@ nouveau_card_init(struct drm_device *dev)
427 goto out; 427 goto out;
428 } 428 }
429 429
430 ret = nouveau_mem_detect(dev);
431 if (ret)
432 goto out_bios;
433
430 ret = nouveau_gpuobj_early_init(dev); 434 ret = nouveau_gpuobj_early_init(dev);
431 if (ret) 435 if (ret)
432 goto out_bios; 436 goto out_bios;
@@ -502,7 +506,7 @@ nouveau_card_init(struct drm_device *dev)
502 else 506 else
503 ret = nv04_display_create(dev); 507 ret = nv04_display_create(dev);
504 if (ret) 508 if (ret)
505 goto out_irq; 509 goto out_channel;
506 } 510 }
507 511
508 ret = nouveau_backlight_init(dev); 512 ret = nouveau_backlight_init(dev);
@@ -516,6 +520,11 @@ nouveau_card_init(struct drm_device *dev)
516 520
517 return 0; 521 return 0;
518 522
523out_channel:
524 if (dev_priv->channel) {
525 nouveau_channel_free(dev_priv->channel);
526 dev_priv->channel = NULL;
527 }
519out_irq: 528out_irq:
520 drm_irq_uninstall(dev); 529 drm_irq_uninstall(dev);
521out_fifo: 530out_fifo:
@@ -533,6 +542,7 @@ out_mc:
533out_gpuobj: 542out_gpuobj:
534 nouveau_gpuobj_takedown(dev); 543 nouveau_gpuobj_takedown(dev);
535out_mem: 544out_mem:
545 nouveau_sgdma_takedown(dev);
536 nouveau_mem_close(dev); 546 nouveau_mem_close(dev);
537out_instmem: 547out_instmem:
538 engine->instmem.takedown(dev); 548 engine->instmem.takedown(dev);
diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c
index 6b2ef4a9fce1..500ccfd3a0b8 100644
--- a/drivers/gpu/drm/nouveau/nv40_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -278,7 +278,7 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
278 default: 278 default:
279 nv_wr32(dev, 0x2230, 0); 279 nv_wr32(dev, 0x2230, 0);
280 nv_wr32(dev, NV40_PFIFO_RAMFC, 280 nv_wr32(dev, NV40_PFIFO_RAMFC,
281 ((nouveau_mem_fb_amount(dev) - 512 * 1024 + 281 ((dev_priv->vram_size - 512 * 1024 +
282 dev_priv->ramfc_offset) >> 16) | (3 << 16)); 282 dev_priv->ramfc_offset) >> 16) | (3 << 16));
283 break; 283 break;
284 } 284 }
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 53e8afe1dcd1..0616c96e4b67 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -335,6 +335,27 @@ nv40_graph_init(struct drm_device *dev)
335 nv_wr32(dev, 0x400b38, 0x2ffff800); 335 nv_wr32(dev, 0x400b38, 0x2ffff800);
336 nv_wr32(dev, 0x400b3c, 0x00006000); 336 nv_wr32(dev, 0x400b3c, 0x00006000);
337 337
338 /* Tiling related stuff. */
339 switch (dev_priv->chipset) {
340 case 0x44:
341 case 0x4a:
342 nv_wr32(dev, 0x400bc4, 0x1003d888);
343 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
344 break;
345 case 0x46:
346 nv_wr32(dev, 0x400bc4, 0x0000e024);
347 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
348 break;
349 case 0x4c:
350 case 0x4e:
351 case 0x67:
352 nv_wr32(dev, 0x400bc4, 0x1003d888);
353 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
354 break;
355 default:
356 break;
357 }
358
338 /* Turn all the tiling regions off. */ 359 /* Turn all the tiling regions off. */
339 for (i = 0; i < pfb->num_tiles; i++) 360 for (i = 0; i < pfb->num_tiles; i++)
340 nv40_graph_set_region_tiling(dev, i, 0, 0, 0); 361 nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index fac6c88a2b1f..649db4c1b690 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -143,7 +143,7 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
143 } 143 }
144 144
145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19, 145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
146 0, nouveau_mem_fb_amount(dev)); 146 0, dev_priv->vram_size);
147 if (ret) { 147 if (ret) {
148 nv50_evo_channel_del(pchan); 148 nv50_evo_channel_del(pchan);
149 return ret; 149 return ret;
@@ -231,7 +231,7 @@ nv50_display_init(struct drm_device *dev)
231 /* This used to be in crtc unblank, but seems out of place there. */ 231 /* This used to be in crtc unblank, but seems out of place there. */
232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); 232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233 /* RAM is clamped to 256 MiB. */ 233 /* RAM is clamped to 256 MiB. */
234 ram_amount = nouveau_mem_fb_amount(dev); 234 ram_amount = dev_priv->vram_size;
235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount); 235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
236 if (ram_amount > 256*1024*1024) 236 if (ram_amount > 256*1024*1024)
237 ram_amount = 256*1024*1024; 237 ram_amount = 256*1024*1024;
@@ -529,8 +529,10 @@ int nv50_display_create(struct drm_device *dev)
529 } 529 }
530 530
531 ret = nv50_display_init(dev); 531 ret = nv50_display_init(dev);
532 if (ret) 532 if (ret) {
533 nv50_display_destroy(dev);
533 return ret; 534 return ret;
535 }
534 536
535 return 0; 537 return 0;
536} 538}
@@ -885,10 +887,12 @@ nv50_display_error_handler(struct drm_device *dev)
885 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000); 887 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
886} 888}
887 889
888static void 890void
889nv50_display_irq_hotplug(struct drm_device *dev) 891nv50_display_irq_hotplug_bh(struct work_struct *work)
890{ 892{
891 struct drm_nouveau_private *dev_priv = dev->dev_private; 893 struct drm_nouveau_private *dev_priv =
894 container_of(work, struct drm_nouveau_private, hpd_work);
895 struct drm_device *dev = dev_priv->dev;
892 struct drm_connector *connector; 896 struct drm_connector *connector;
893 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 897 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
894 uint32_t unplug_mask, plug_mask, change_mask; 898 uint32_t unplug_mask, plug_mask, change_mask;
@@ -949,8 +953,10 @@ nv50_display_irq_handler(struct drm_device *dev)
949 struct drm_nouveau_private *dev_priv = dev->dev_private; 953 struct drm_nouveau_private *dev_priv = dev->dev_private;
950 uint32_t delayed = 0; 954 uint32_t delayed = 0;
951 955
952 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) 956 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
953 nv50_display_irq_hotplug(dev); 957 if (!work_pending(&dev_priv->hpd_work))
958 queue_work(dev_priv->wq, &dev_priv->hpd_work);
959 }
954 960
955 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 961 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
956 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 962 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h
index 3ae8d0725f63..581d405ac014 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.h
+++ b/drivers/gpu/drm/nouveau/nv50_display.h
@@ -37,6 +37,7 @@
37 37
38void nv50_display_irq_handler(struct drm_device *dev); 38void nv50_display_irq_handler(struct drm_device *dev);
39void nv50_display_irq_handler_bh(struct work_struct *work); 39void nv50_display_irq_handler_bh(struct work_struct *work);
40void nv50_display_irq_hotplug_bh(struct work_struct *work);
40int nv50_display_init(struct drm_device *dev); 41int nv50_display_init(struct drm_device *dev);
41int nv50_display_create(struct drm_device *dev); 42int nv50_display_create(struct drm_device *dev);
42int nv50_display_destroy(struct drm_device *dev); 43int nv50_display_destroy(struct drm_device *dev);
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 25a3cd8794f9..a8c70e7e9184 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -157,8 +157,11 @@ nv50_fbcon_accel_init(struct fb_info *info)
157 struct drm_nouveau_private *dev_priv = dev->dev_private; 157 struct drm_nouveau_private *dev_priv = dev->dev_private;
158 struct nouveau_channel *chan = dev_priv->channel; 158 struct nouveau_channel *chan = dev_priv->channel;
159 struct nouveau_gpuobj *eng2d = NULL; 159 struct nouveau_gpuobj *eng2d = NULL;
160 uint64_t fb;
160 int ret, format; 161 int ret, format;
161 162
163 fb = info->fix.smem_start - dev_priv->fb_phys + dev_priv->vm_vram_base;
164
162 switch (info->var.bits_per_pixel) { 165 switch (info->var.bits_per_pixel) {
163 case 8: 166 case 8:
164 format = 0xf3; 167 format = 0xf3;
@@ -248,9 +251,8 @@ nv50_fbcon_accel_init(struct fb_info *info)
248 OUT_RING(chan, info->fix.line_length); 251 OUT_RING(chan, info->fix.line_length);
249 OUT_RING(chan, info->var.xres_virtual); 252 OUT_RING(chan, info->var.xres_virtual);
250 OUT_RING(chan, info->var.yres_virtual); 253 OUT_RING(chan, info->var.yres_virtual);
251 OUT_RING(chan, 0); 254 OUT_RING(chan, upper_32_bits(fb));
252 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + 255 OUT_RING(chan, lower_32_bits(fb));
253 dev_priv->vm_vram_base);
254 BEGIN_RING(chan, NvSub2D, 0x0230, 2); 256 BEGIN_RING(chan, NvSub2D, 0x0230, 2);
255 OUT_RING(chan, format); 257 OUT_RING(chan, format);
256 OUT_RING(chan, 1); 258 OUT_RING(chan, 1);
@@ -258,9 +260,8 @@ nv50_fbcon_accel_init(struct fb_info *info)
258 OUT_RING(chan, info->fix.line_length); 260 OUT_RING(chan, info->fix.line_length);
259 OUT_RING(chan, info->var.xres_virtual); 261 OUT_RING(chan, info->var.xres_virtual);
260 OUT_RING(chan, info->var.yres_virtual); 262 OUT_RING(chan, info->var.yres_virtual);
261 OUT_RING(chan, 0); 263 OUT_RING(chan, upper_32_bits(fb));
262 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + 264 OUT_RING(chan, lower_32_bits(fb));
263 dev_priv->vm_vram_base);
264 265
265 return 0; 266 return 0;
266} 267}
diff --git a/drivers/gpu/drm/nouveau/nv50_gpio.c b/drivers/gpu/drm/nouveau/nv50_gpio.c
new file mode 100644
index 000000000000..c61782b314e7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_gpio.c
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_hw.h"
28
29static int
30nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
31{
32 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
33
34 if (gpio->line > 32)
35 return -EINVAL;
36
37 *reg = nv50_gpio_reg[gpio->line >> 3];
38 *shift = (gpio->line & 7) << 2;
39 return 0;
40}
41
42int
43nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
44{
45 struct dcb_gpio_entry *gpio;
46 uint32_t r, s, v;
47
48 gpio = nouveau_bios_gpio_entry(dev, tag);
49 if (!gpio)
50 return -ENOENT;
51
52 if (nv50_gpio_location(gpio, &r, &s))
53 return -EINVAL;
54
55 v = nv_rd32(dev, r) >> (s + 2);
56 return ((v & 1) == (gpio->state[1] & 1));
57}
58
59int
60nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
61{
62 struct dcb_gpio_entry *gpio;
63 uint32_t r, s, v;
64
65 gpio = nouveau_bios_gpio_entry(dev, tag);
66 if (!gpio)
67 return -ENOENT;
68
69 if (nv50_gpio_location(gpio, &r, &s))
70 return -EINVAL;
71
72 v = nv_rd32(dev, r) & ~(0x3 << s);
73 v |= (gpio->state[state] ^ 2) << s;
74 nv_wr32(dev, r, v);
75 return 0;
76}
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index c62b33a02f88..b203d06f601f 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -410,9 +410,10 @@ struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
410 { 0x5039, false, NULL }, /* m2mf */ 410 { 0x5039, false, NULL }, /* m2mf */
411 { 0x502d, false, NULL }, /* 2d */ 411 { 0x502d, false, NULL }, /* 2d */
412 { 0x50c0, false, NULL }, /* compute */ 412 { 0x50c0, false, NULL }, /* compute */
413 { 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */
413 { 0x5097, false, NULL }, /* tesla (nv50) */ 414 { 0x5097, false, NULL }, /* tesla (nv50) */
414 { 0x8297, false, NULL }, /* tesla (nv80/nv90) */ 415 { 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */
415 { 0x8397, false, NULL }, /* tesla (nva0) */ 416 { 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */
416 { 0x8597, false, NULL }, /* tesla (nva8) */ 417 { 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
417 {} 418 {}
418}; 419};
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c
index 546b31949a30..42a8fb20c1e6 100644
--- a/drivers/gpu/drm/nouveau/nv50_grctx.c
+++ b/drivers/gpu/drm/nouveau/nv50_grctx.c
@@ -55,12 +55,12 @@
55#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) 55#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5)
56#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 56#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
57#define CP_FLAG_AUTO_LOAD_PENDING 1 57#define CP_FLAG_AUTO_LOAD_PENDING 1
58#define CP_FLAG_NEWCTX ((2 * 32) + 10)
59#define CP_FLAG_NEWCTX_BUSY 0
60#define CP_FLAG_NEWCTX_DONE 1
58#define CP_FLAG_XFER ((2 * 32) + 11) 61#define CP_FLAG_XFER ((2 * 32) + 11)
59#define CP_FLAG_XFER_IDLE 0 62#define CP_FLAG_XFER_IDLE 0
60#define CP_FLAG_XFER_BUSY 1 63#define CP_FLAG_XFER_BUSY 1
61#define CP_FLAG_NEWCTX ((2 * 32) + 12)
62#define CP_FLAG_NEWCTX_BUSY 0
63#define CP_FLAG_NEWCTX_DONE 1
64#define CP_FLAG_ALWAYS ((2 * 32) + 13) 64#define CP_FLAG_ALWAYS ((2 * 32) + 13)
65#define CP_FLAG_ALWAYS_FALSE 0 65#define CP_FLAG_ALWAYS_FALSE 0
66#define CP_FLAG_ALWAYS_TRUE 1 66#define CP_FLAG_ALWAYS_TRUE 1
@@ -177,6 +177,7 @@ nv50_grctx_init(struct nouveau_grctx *ctx)
177 case 0x96: 177 case 0x96:
178 case 0x98: 178 case 0x98:
179 case 0xa0: 179 case 0xa0:
180 case 0xa3:
180 case 0xa5: 181 case 0xa5:
181 case 0xa8: 182 case 0xa8:
182 case 0xaa: 183 case 0xaa:
@@ -364,6 +365,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
364 case 0xac: 365 case 0xac:
365 gr_def(ctx, 0x401c00, 0x042500df); 366 gr_def(ctx, 0x401c00, 0x042500df);
366 break; 367 break;
368 case 0xa3:
367 case 0xa5: 369 case 0xa5:
368 case 0xa8: 370 case 0xa8:
369 gr_def(ctx, 0x401c00, 0x142500df); 371 gr_def(ctx, 0x401c00, 0x142500df);
@@ -418,6 +420,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
418 break; 420 break;
419 case 0x84: 421 case 0x84:
420 case 0xa0: 422 case 0xa0:
423 case 0xa3:
421 case 0xa5: 424 case 0xa5:
422 case 0xa8: 425 case 0xa8:
423 case 0xaa: 426 case 0xaa:
@@ -792,6 +795,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
792 case 0xa5: 795 case 0xa5:
793 gr_def(ctx, offset + 0x1c, 0x310c0000); 796 gr_def(ctx, offset + 0x1c, 0x310c0000);
794 break; 797 break;
798 case 0xa3:
795 case 0xa8: 799 case 0xa8:
796 case 0xaa: 800 case 0xaa:
797 case 0xac: 801 case 0xac:
@@ -859,6 +863,8 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
859 else 863 else
860 gr_def(ctx, offset + 0x8, 0x05010202); 864 gr_def(ctx, offset + 0x8, 0x05010202);
861 gr_def(ctx, offset + 0xc, 0x00030201); 865 gr_def(ctx, offset + 0xc, 0x00030201);
866 if (dev_priv->chipset == 0xa3)
867 cp_ctx(ctx, base + 0x36c, 1);
862 868
863 cp_ctx(ctx, base + 0x400, 2); 869 cp_ctx(ctx, base + 0x400, 2);
864 gr_def(ctx, base + 0x404, 0x00000040); 870 gr_def(ctx, base + 0x404, 0x00000040);
@@ -1159,7 +1165,9 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
1159 nv50_graph_construct_gene_unk8(ctx); 1165 nv50_graph_construct_gene_unk8(ctx);
1160 if (dev_priv->chipset == 0xa0) 1166 if (dev_priv->chipset == 0xa0)
1161 xf_emit(ctx, 0x189, 0); 1167 xf_emit(ctx, 0x189, 0);
1162 else if (dev_priv->chipset < 0xa8) 1168 else if (dev_priv->chipset == 0xa3)
1169 xf_emit(ctx, 0xd5, 0);
1170 else if (dev_priv->chipset == 0xa5)
1163 xf_emit(ctx, 0x99, 0); 1171 xf_emit(ctx, 0x99, 0);
1164 else if (dev_priv->chipset == 0xaa) 1172 else if (dev_priv->chipset == 0xaa)
1165 xf_emit(ctx, 0x65, 0); 1173 xf_emit(ctx, 0x65, 0);
@@ -1197,6 +1205,8 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
1197 ctx->ctxvals_pos = offset + 4; 1205 ctx->ctxvals_pos = offset + 4;
1198 if (dev_priv->chipset == 0xa0) 1206 if (dev_priv->chipset == 0xa0)
1199 xf_emit(ctx, 0xa80, 0); 1207 xf_emit(ctx, 0xa80, 0);
1208 else if (dev_priv->chipset == 0xa3)
1209 xf_emit(ctx, 0xa7c, 0);
1200 else 1210 else
1201 xf_emit(ctx, 0xa7a, 0); 1211 xf_emit(ctx, 0xa7a, 0);
1202 xf_emit(ctx, 1, 0x3fffff); 1212 xf_emit(ctx, 1, 0x3fffff);
@@ -1341,6 +1351,7 @@ nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx)
1341 xf_emit(ctx, 0x942, 0); 1351 xf_emit(ctx, 0x942, 0);
1342 break; 1352 break;
1343 case 0xa0: 1353 case 0xa0:
1354 case 0xa3:
1344 xf_emit(ctx, 0x2042, 0); 1355 xf_emit(ctx, 0x2042, 0);
1345 break; 1356 break;
1346 case 0xa5: 1357 case 0xa5:
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index de1f5b0062c5..5f21df31f3aa 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -63,9 +63,10 @@ nv50_instmem_init(struct drm_device *dev)
63 struct drm_nouveau_private *dev_priv = dev->dev_private; 63 struct drm_nouveau_private *dev_priv = dev->dev_private;
64 struct nouveau_channel *chan; 64 struct nouveau_channel *chan;
65 uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size; 65 uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
66 uint32_t save_nv001700;
67 uint64_t v;
66 struct nv50_instmem_priv *priv; 68 struct nv50_instmem_priv *priv;
67 int ret, i; 69 int ret, i;
68 uint32_t v, save_nv001700;
69 70
70 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 71 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
71 if (!priv) 72 if (!priv)
@@ -76,17 +77,12 @@ nv50_instmem_init(struct drm_device *dev)
76 for (i = 0x1700; i <= 0x1710; i += 4) 77 for (i = 0x1700; i <= 0x1710; i += 4)
77 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i); 78 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
78 79
79 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
80 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
81 else
82 dev_priv->vram_sys_base = 0;
83
84 /* Reserve the last MiB of VRAM, we should probably try to avoid 80 /* Reserve the last MiB of VRAM, we should probably try to avoid
85 * setting up the below tables over the top of the VBIOS image at 81 * setting up the below tables over the top of the VBIOS image at
86 * some point. 82 * some point.
87 */ 83 */
88 dev_priv->ramin_rsvd_vram = 1 << 20; 84 dev_priv->ramin_rsvd_vram = 1 << 20;
89 c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram; 85 c_offset = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
90 c_size = 128 << 10; 86 c_size = 128 << 10;
91 c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200; 87 c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
92 c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20; 88 c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
@@ -106,7 +102,7 @@ nv50_instmem_init(struct drm_device *dev)
106 dev_priv->vm_gart_size = NV50_VM_BLOCK; 102 dev_priv->vm_gart_size = NV50_VM_BLOCK;
107 103
108 dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size; 104 dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size;
109 dev_priv->vm_vram_size = nouveau_mem_fb_amount(dev); 105 dev_priv->vm_vram_size = dev_priv->vram_size;
110 if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM) 106 if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM)
111 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM; 107 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM;
112 dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK); 108 dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK);
@@ -189,8 +185,8 @@ nv50_instmem_init(struct drm_device *dev)
189 185
190 i = 0; 186 i = 0;
191 while (v < dev_priv->vram_sys_base + c_offset + c_size) { 187 while (v < dev_priv->vram_sys_base + c_offset + c_size) {
192 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v); 188 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, lower_32_bits(v));
193 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); 189 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, upper_32_bits(v));
194 v += 0x1000; 190 v += 0x1000;
195 i += 8; 191 i += 8;
196 } 192 }
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index c2fff543b06f..0c68698f23df 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -211,7 +211,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
211 mode_ctl = 0x0200; 211 mode_ctl = 0x0200;
212 break; 212 break;
213 case OUTPUT_DP: 213 case OUTPUT_DP:
214 mode_ctl |= 0x00050000; 214 mode_ctl |= (nv_encoder->dp.mc_unknown << 16);
215 if (nv_encoder->dcb->sorconf.link & 1) 215 if (nv_encoder->dcb->sorconf.link & 1)
216 mode_ctl |= 0x00000800; 216 mode_ctl |= 0x00000800;
217 else 217 else
@@ -274,6 +274,7 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
274int 274int
275nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) 275nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
276{ 276{
277 struct drm_nouveau_private *dev_priv = dev->dev_private;
277 struct nouveau_encoder *nv_encoder = NULL; 278 struct nouveau_encoder *nv_encoder = NULL;
278 struct drm_encoder *encoder; 279 struct drm_encoder *encoder;
279 bool dum; 280 bool dum;
@@ -319,5 +320,27 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
319 encoder->possible_crtcs = entry->heads; 320 encoder->possible_crtcs = entry->heads;
320 encoder->possible_clones = 0; 321 encoder->possible_clones = 0;
321 322
323 if (nv_encoder->dcb->type == OUTPUT_DP) {
324 uint32_t mc, or = nv_encoder->or;
325
326 if (dev_priv->chipset < 0x90 ||
327 dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
328 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
329 else
330 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
331
332 switch ((mc & 0x00000f00) >> 8) {
333 case 8:
334 case 9:
335 nv_encoder->dp.mc_unknown = (mc & 0x000f0000) >> 16;
336 break;
337 default:
338 break;
339 }
340
341 if (!nv_encoder->dp.mc_unknown)
342 nv_encoder->dp.mc_unknown = 5;
343 }
344
322 return 0; 345 return 0;
323} 346}
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 07b7ebf1f466..1d569830ed99 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -908,11 +908,16 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
908 uint8_t attr = U8((*ptr)++), shift; 908 uint8_t attr = U8((*ptr)++), shift;
909 uint32_t saved, dst; 909 uint32_t saved, dst;
910 int dptr = *ptr; 910 int dptr = *ptr;
911 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
911 SDEBUG(" dst: "); 912 SDEBUG(" dst: ");
912 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 913 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
914 /* op needs to full dst value */
915 dst = saved;
913 shift = atom_get_src(ctx, attr, ptr); 916 shift = atom_get_src(ctx, attr, ptr);
914 SDEBUG(" shift: %d\n", shift); 917 SDEBUG(" shift: %d\n", shift);
915 dst <<= shift; 918 dst <<= shift;
919 dst &= atom_arg_mask[dst_align];
920 dst >>= atom_arg_shift[dst_align];
916 SDEBUG(" dst: "); 921 SDEBUG(" dst: ");
917 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 922 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
918} 923}
@@ -922,11 +927,16 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
922 uint8_t attr = U8((*ptr)++), shift; 927 uint8_t attr = U8((*ptr)++), shift;
923 uint32_t saved, dst; 928 uint32_t saved, dst;
924 int dptr = *ptr; 929 int dptr = *ptr;
930 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
925 SDEBUG(" dst: "); 931 SDEBUG(" dst: ");
926 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 932 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
933 /* op needs to full dst value */
934 dst = saved;
927 shift = atom_get_src(ctx, attr, ptr); 935 shift = atom_get_src(ctx, attr, ptr);
928 SDEBUG(" shift: %d\n", shift); 936 SDEBUG(" shift: %d\n", shift);
929 dst >>= shift; 937 dst >>= shift;
938 dst &= atom_arg_mask[dst_align];
939 dst >>= atom_arg_shift[dst_align];
930 SDEBUG(" dst: "); 940 SDEBUG(" dst: ");
931 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 941 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
932} 942}
@@ -1137,6 +1147,7 @@ static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32
1137 int len, ws, ps, ptr; 1147 int len, ws, ps, ptr;
1138 unsigned char op; 1148 unsigned char op;
1139 atom_exec_context ectx; 1149 atom_exec_context ectx;
1150 int ret = 0;
1140 1151
1141 if (!base) 1152 if (!base)
1142 return -EINVAL; 1153 return -EINVAL;
@@ -1169,7 +1180,8 @@ static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32
1169 if (ectx.abort) { 1180 if (ectx.abort) {
1170 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1181 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1171 base, len, ws, ps, ptr - 1); 1182 base, len, ws, ps, ptr - 1);
1172 return -EINVAL; 1183 ret = -EINVAL;
1184 goto free;
1173 } 1185 }
1174 1186
1175 if (op < ATOM_OP_CNT && op > 0) 1187 if (op < ATOM_OP_CNT && op > 0)
@@ -1184,9 +1196,10 @@ static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32
1184 debug_depth--; 1196 debug_depth--;
1185 SDEBUG("<<\n"); 1197 SDEBUG("<<\n");
1186 1198
1199free:
1187 if (ws) 1200 if (ws)
1188 kfree(ectx.ws); 1201 kfree(ectx.ws);
1189 return 0; 1202 return ret;
1190} 1203}
1191 1204
1192int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1205int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 6732b5dd8ff4..27e2c715be11 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -2912,7 +2912,7 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2
2912 UCHAR ucTV_BootUpDefaultStandard; 2912 UCHAR ucTV_BootUpDefaultStandard;
2913 UCHAR ucExt_TV_ASIC_ID; 2913 UCHAR ucExt_TV_ASIC_ID;
2914 UCHAR ucExt_TV_ASIC_SlaveAddr; 2914 UCHAR ucExt_TV_ASIC_SlaveAddr;
2915 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; 2915 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
2916}ATOM_ANALOG_TV_INFO_V1_2; 2916}ATOM_ANALOG_TV_INFO_V1_2;
2917 2917
2918typedef struct _ATOM_DPCD_INFO 2918typedef struct _ATOM_DPCD_INFO
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index fd4ef6d18849..a87990b3ae84 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -521,6 +521,10 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
521 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 521 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
522 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 522 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
523 adjusted_clock = mode->clock * 2; 523 adjusted_clock = mode->clock * 2;
524 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
525 pll->algo = PLL_ALGO_LEGACY;
526 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
527 }
524 } else { 528 } else {
525 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 529 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
526 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 530 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index c9580497ede4..cf60c0b3ef15 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2891,7 +2891,7 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
2891{ 2891{
2892 struct radeon_bo *robj; 2892 struct radeon_bo *robj;
2893 unsigned long size; 2893 unsigned long size;
2894 unsigned u, i, w, h; 2894 unsigned u, i, w, h, d;
2895 int ret; 2895 int ret;
2896 2896
2897 for (u = 0; u < track->num_texture; u++) { 2897 for (u = 0; u < track->num_texture; u++) {
@@ -2923,20 +2923,25 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
2923 h = h / (1 << i); 2923 h = h / (1 << i);
2924 if (track->textures[u].roundup_h) 2924 if (track->textures[u].roundup_h)
2925 h = roundup_pow_of_two(h); 2925 h = roundup_pow_of_two(h);
2926 if (track->textures[u].tex_coord_type == 1) {
2927 d = (1 << track->textures[u].txdepth) / (1 << i);
2928 if (!d)
2929 d = 1;
2930 } else {
2931 d = 1;
2932 }
2926 if (track->textures[u].compress_format) { 2933 if (track->textures[u].compress_format) {
2927 2934
2928 size += r100_track_compress_size(track->textures[u].compress_format, w, h); 2935 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2929 /* compressed textures are block based */ 2936 /* compressed textures are block based */
2930 } else 2937 } else
2931 size += w * h; 2938 size += w * h * d;
2932 } 2939 }
2933 size *= track->textures[u].cpp; 2940 size *= track->textures[u].cpp;
2934 2941
2935 switch (track->textures[u].tex_coord_type) { 2942 switch (track->textures[u].tex_coord_type) {
2936 case 0: 2943 case 0:
2937 break;
2938 case 1: 2944 case 1:
2939 size *= (1 << track->textures[u].txdepth);
2940 break; 2945 break;
2941 case 2: 2946 case 2:
2942 if (track->separate_cube) { 2947 if (track->separate_cube) {
@@ -2970,7 +2975,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2970 2975
2971 for (i = 0; i < track->num_cb; i++) { 2976 for (i = 0; i < track->num_cb; i++) {
2972 if (track->cb[i].robj == NULL) { 2977 if (track->cb[i].robj == NULL) {
2973 if (!(track->fastfill || track->color_channel_mask || 2978 if (!(track->zb_cb_clear || track->color_channel_mask ||
2974 track->blend_read_enable)) { 2979 track->blend_read_enable)) {
2975 continue; 2980 continue;
2976 } 2981 }
@@ -3007,7 +3012,11 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3007 } 3012 }
3008 } 3013 }
3009 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3014 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3010 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3015 if (track->vap_vf_cntl & (1 << 14)) {
3016 nverts = track->vap_alt_nverts;
3017 } else {
3018 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3019 }
3011 switch (prim_walk) { 3020 switch (prim_walk) {
3012 case 1: 3021 case 1:
3013 for (i = 0; i < track->num_arrays; i++) { 3022 for (i = 0; i < track->num_arrays; i++) {
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index b27a6999d219..f47cdca1c004 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -64,6 +64,7 @@ struct r100_cs_track {
64 unsigned maxy; 64 unsigned maxy;
65 unsigned vtx_size; 65 unsigned vtx_size;
66 unsigned vap_vf_cntl; 66 unsigned vap_vf_cntl;
67 unsigned vap_alt_nverts;
67 unsigned immd_dwords; 68 unsigned immd_dwords;
68 unsigned num_arrays; 69 unsigned num_arrays;
69 unsigned max_indx; 70 unsigned max_indx;
@@ -74,7 +75,7 @@ struct r100_cs_track {
74 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 75 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
75 bool z_enabled; 76 bool z_enabled;
76 bool separate_cube; 77 bool separate_cube;
77 bool fastfill; 78 bool zb_cb_clear;
78 bool blend_read_enable; 79 bool blend_read_enable;
79}; 80};
80 81
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 561048a7c0a4..a5ff8076b423 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -324,12 +324,12 @@ void r300_gpu_init(struct radeon_device *rdev)
324 uint32_t gb_tile_config, tmp; 324 uint32_t gb_tile_config, tmp;
325 325
326 r100_hdp_reset(rdev); 326 r100_hdp_reset(rdev);
327 /* FIXME: rv380 one pipes ? */ 327 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
328 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { 328 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
329 /* r300,r350 */ 329 /* r300,r350 */
330 rdev->num_gb_pipes = 2; 330 rdev->num_gb_pipes = 2;
331 } else { 331 } else {
332 /* rv350,rv370,rv380 */ 332 /* rv350,rv370,rv380,r300 AD, r350 AH */
333 rdev->num_gb_pipes = 1; 333 rdev->num_gb_pipes = 1;
334 } 334 }
335 rdev->num_z_pipes = 1; 335 rdev->num_z_pipes = 1;
@@ -729,6 +729,12 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
729 /* VAP_VF_MAX_VTX_INDX */ 729 /* VAP_VF_MAX_VTX_INDX */
730 track->max_indx = idx_value & 0x00FFFFFFUL; 730 track->max_indx = idx_value & 0x00FFFFFFUL;
731 break; 731 break;
732 case 0x2088:
733 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
734 if (p->rdev->family < CHIP_RV515)
735 goto fail;
736 track->vap_alt_nverts = idx_value & 0xFFFFFF;
737 break;
732 case 0x43E4: 738 case 0x43E4:
733 /* SC_SCISSOR1 */ 739 /* SC_SCISSOR1 */
734 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 740 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
@@ -766,7 +772,6 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
766 tmp = idx_value & ~(0x7 << 16); 772 tmp = idx_value & ~(0x7 << 16);
767 tmp |= tile_flags; 773 tmp |= tile_flags;
768 ib[idx] = tmp; 774 ib[idx] = tmp;
769
770 i = (reg - 0x4E38) >> 2; 775 i = (reg - 0x4E38) >> 2;
771 track->cb[i].pitch = idx_value & 0x3FFE; 776 track->cb[i].pitch = idx_value & 0x3FFE;
772 switch (((idx_value >> 21) & 0xF)) { 777 switch (((idx_value >> 21) & 0xF)) {
@@ -1039,7 +1044,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1039 break; 1044 break;
1040 case 0x4d1c: 1045 case 0x4d1c:
1041 /* ZB_BW_CNTL */ 1046 /* ZB_BW_CNTL */
1042 track->fastfill = !!(idx_value & (1 << 2)); 1047 track->zb_cb_clear = !!(idx_value & (1 << 5));
1043 break; 1048 break;
1044 case 0x4e04: 1049 case 0x4e04:
1045 /* RB3D_BLENDCNTL */ 1050 /* RB3D_BLENDCNTL */
@@ -1051,11 +1056,13 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1051 break; 1056 break;
1052 /* fallthrough do not move */ 1057 /* fallthrough do not move */
1053 default: 1058 default:
1054 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1059 goto fail;
1055 reg, idx);
1056 return -EINVAL;
1057 } 1060 }
1058 return 0; 1061 return 0;
1062fail:
1063 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1064 reg, idx);
1065 return -EINVAL;
1059} 1066}
1060 1067
1061static int r300_packet3_check(struct radeon_cs_parser *p, 1068static int r300_packet3_check(struct radeon_cs_parser *p,
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
index ea46d558e8f3..c5c2742e4140 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
@@ -921,7 +921,7 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
921 921
922 ptr_addr = drm_buffer_read_object(cmdbuf->buffer, 922 ptr_addr = drm_buffer_read_object(cmdbuf->buffer,
923 sizeof(stack_ptr_addr), &stack_ptr_addr); 923 sizeof(stack_ptr_addr), &stack_ptr_addr);
924 ref_age_base = (u32 *)(unsigned long)*ptr_addr; 924 ref_age_base = (u32 *)(unsigned long)get_unaligned(ptr_addr);
925 925
926 for (i=0; i < header.scratch.n_bufs; i++) { 926 for (i=0; i < header.scratch.n_bufs; i++) {
927 buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); 927 buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 3dc968c9f5a4..c2bda4ad62e7 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -59,6 +59,12 @@ void r420_pipes_init(struct radeon_device *rdev)
59 /* get max number of pipes */ 59 /* get max number of pipes */
60 gb_pipe_select = RREG32(0x402C); 60 gb_pipe_select = RREG32(0x402C);
61 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 61 num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
62
63 /* SE chips have 1 pipe */
64 if ((rdev->pdev->device == 0x5e4c) ||
65 (rdev->pdev->device == 0x5e4f))
66 num_pipes = 1;
67
62 rdev->num_gb_pipes = num_pipes; 68 rdev->num_gb_pipes = num_pipes;
63 tmp = 0; 69 tmp = 0;
64 switch (num_pipes) { 70 switch (num_pipes) {
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index dac7042b797e..1d898051c631 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -35,7 +35,7 @@
35 */ 35 */
36static int r600_audio_chipset_supported(struct radeon_device *rdev) 36static int r600_audio_chipset_supported(struct radeon_device *rdev)
37{ 37{
38 return rdev->family >= CHIP_R600 38 return (rdev->family >= CHIP_R600 && rdev->family < CHIP_CEDAR)
39 || rdev->family == CHIP_RS600 39 || rdev->family == CHIP_RS600
40 || rdev->family == CHIP_RS690 40 || rdev->family == CHIP_RS690
41 || rdev->family == CHIP_RS740; 41 || rdev->family == CHIP_RS740;
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 029fa1406d1d..2616b822ba68 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -314,6 +314,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
314 struct radeon_device *rdev = dev->dev_private; 314 struct radeon_device *rdev = dev->dev_private;
315 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 315 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
316 316
317 if (ASIC_IS_DCE4(rdev))
318 return;
319
317 if (!offset) 320 if (!offset)
318 return; 321 return;
319 322
@@ -484,6 +487,9 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
484 struct radeon_device *rdev = dev->dev_private; 487 struct radeon_device *rdev = dev->dev_private;
485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
486 489
490 if (ASIC_IS_DCE4(rdev))
491 return;
492
487 if (!radeon_encoder->hdmi_offset) { 493 if (!radeon_encoder->hdmi_offset) {
488 r600_hdmi_assign_block(encoder); 494 r600_hdmi_assign_block(encoder);
489 if (!radeon_encoder->hdmi_offset) { 495 if (!radeon_encoder->hdmi_offset) {
@@ -525,6 +531,9 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
525 struct radeon_device *rdev = dev->dev_private; 531 struct radeon_device *rdev = dev->dev_private;
526 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 532 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
527 533
534 if (ASIC_IS_DCE4(rdev))
535 return;
536
528 if (!radeon_encoder->hdmi_offset) { 537 if (!radeon_encoder->hdmi_offset) {
529 dev_err(rdev->dev, "Disabling not enabled HDMI\n"); 538 dev_err(rdev->dev, "Disabling not enabled HDMI\n");
530 return; 539 return;
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index c4457791dff1..28e473f1f56f 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -134,12 +134,10 @@ int radeon_agp_init(struct radeon_device *rdev)
134 int ret; 134 int ret;
135 135
136 /* Acquire AGP. */ 136 /* Acquire AGP. */
137 if (!rdev->ddev->agp->acquired) { 137 ret = drm_agp_acquire(rdev->ddev);
138 ret = drm_agp_acquire(rdev->ddev); 138 if (ret) {
139 if (ret) { 139 DRM_ERROR("Unable to acquire AGP: %d\n", ret);
140 DRM_ERROR("Unable to acquire AGP: %d\n", ret); 140 return ret;
141 return ret;
142 }
143 } 141 }
144 142
145 ret = drm_agp_info(rdev->ddev, &info); 143 ret = drm_agp_info(rdev->ddev, &info);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 1fff95505cf5..9916d825401c 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -69,16 +69,19 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
69 struct radeon_i2c_bus_rec i2c; 69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info; 71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset; 72 uint16_t data_offset, size;
73 int i; 73 int i, num_indices;
74 74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false; 76 i2c.valid = false;
77 77
78 if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 78 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80 80
81 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { 81 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
82 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
83
84 for (i = 0; i < num_indices; i++) {
82 gpio = &i2c_info->asGPIO_Info[i]; 85 gpio = &i2c_info->asGPIO_Info[i];
83 86
84 if (gpio->sucI2cId.ucAccess == id) { 87 if (gpio->sucI2cId.ucAccess == id) {
@@ -1261,7 +1264,7 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1261 switch (crev) { 1264 switch (crev) {
1262 case 1: 1265 case 1:
1263 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1266 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1264 if (index > MAX_SUPPORTED_TV_TIMING) 1267 if (index >= MAX_SUPPORTED_TV_TIMING)
1265 return false; 1268 return false;
1266 1269
1267 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1270 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
@@ -1299,7 +1302,7 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1299 break; 1302 break;
1300 case 2: 1303 case 2:
1301 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1304 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1302 if (index > MAX_SUPPORTED_TV_TIMING_V1_2) 1305 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1303 return false; 1306 return false;
1304 1307
1305 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1308 dtd_timings = &tv_info_v1_2->aModeTimings[index];
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 2becdeda68a3..37db8adb2748 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -760,7 +760,9 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
760 dac = RBIOS8(dac_info + 0x3) & 0xf; 760 dac = RBIOS8(dac_info + 0x3) & 0xf;
761 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 761 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
762 } 762 }
763 found = 1; 763 /* if the values are all zeros, use the table */
764 if (p_dac->ps2_pdac_adj)
765 found = 1;
764 } 766 }
765 767
766 if (!found) /* fallback to defaults */ 768 if (!found) /* fallback to defaults */
@@ -895,7 +897,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
895 bg = RBIOS8(dac_info + 0x10) & 0xf; 897 bg = RBIOS8(dac_info + 0x10) & 0xf;
896 dac = RBIOS8(dac_info + 0x11) & 0xf; 898 dac = RBIOS8(dac_info + 0x11) & 0xf;
897 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 899 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
898 found = 1; 900 /* if the values are all zeros, use the table */
901 if (tv_dac->ps2_tvdac_adj)
902 found = 1;
899 } else if (rev > 1) { 903 } else if (rev > 1) {
900 bg = RBIOS8(dac_info + 0xc) & 0xf; 904 bg = RBIOS8(dac_info + 0xc) & 0xf;
901 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 905 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
@@ -908,7 +912,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
908 bg = RBIOS8(dac_info + 0xe) & 0xf; 912 bg = RBIOS8(dac_info + 0xe) & 0xf;
909 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 913 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
910 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 914 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
911 found = 1; 915 /* if the values are all zeros, use the table */
916 if (tv_dac->ps2_tvdac_adj)
917 found = 1;
912 } 918 }
913 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 919 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
914 } 920 }
@@ -925,7 +931,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
925 (bg << 16) | (dac << 20); 931 (bg << 16) | (dac << 20);
926 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 932 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
927 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 933 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
928 found = 1; 934 /* if the values are all zeros, use the table */
935 if (tv_dac->ps2_tvdac_adj)
936 found = 1;
929 } else { 937 } else {
930 bg = RBIOS8(dac_info + 0x4) & 0xf; 938 bg = RBIOS8(dac_info + 0x4) & 0xf;
931 dac = RBIOS8(dac_info + 0x5) & 0xf; 939 dac = RBIOS8(dac_info + 0x5) & 0xf;
@@ -933,7 +941,9 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
933 (bg << 16) | (dac << 20); 941 (bg << 16) | (dac << 20);
934 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 942 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
935 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 943 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
936 found = 1; 944 /* if the values are all zeros, use the table */
945 if (tv_dac->ps2_tvdac_adj)
946 found = 1;
937 } 947 }
938 } else { 948 } else {
939 DRM_INFO("No TV DAC info found in BIOS\n"); 949 DRM_INFO("No TV DAC info found in BIOS\n");
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 60d59816b94f..4559a53d5e57 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -162,12 +162,14 @@ radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
162{ 162{
163 struct drm_device *dev = connector->dev; 163 struct drm_device *dev = connector->dev;
164 struct drm_connector *conflict; 164 struct drm_connector *conflict;
165 struct radeon_connector *radeon_conflict;
165 int i; 166 int i;
166 167
167 list_for_each_entry(conflict, &dev->mode_config.connector_list, head) { 168 list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
168 if (conflict == connector) 169 if (conflict == connector)
169 continue; 170 continue;
170 171
172 radeon_conflict = to_radeon_connector(conflict);
171 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 173 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
172 if (conflict->encoder_ids[i] == 0) 174 if (conflict->encoder_ids[i] == 0)
173 break; 175 break;
@@ -177,6 +179,9 @@ radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
177 if (conflict->status != connector_status_connected) 179 if (conflict->status != connector_status_connected)
178 continue; 180 continue;
179 181
182 if (radeon_conflict->use_digital)
183 continue;
184
180 if (priority == true) { 185 if (priority == true) {
181 DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict)); 186 DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
182 DRM_INFO("in favor of %s\n", drm_get_connector_name(connector)); 187 DRM_INFO("in favor of %s\n", drm_get_connector_name(connector));
@@ -287,6 +292,7 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
287 292
288 if (property == rdev->mode_info.coherent_mode_property) { 293 if (property == rdev->mode_info.coherent_mode_property) {
289 struct radeon_encoder_atom_dig *dig; 294 struct radeon_encoder_atom_dig *dig;
295 bool new_coherent_mode;
290 296
291 /* need to find digital encoder on connector */ 297 /* need to find digital encoder on connector */
292 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 298 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
@@ -299,8 +305,11 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
299 return 0; 305 return 0;
300 306
301 dig = radeon_encoder->enc_priv; 307 dig = radeon_encoder->enc_priv;
302 dig->coherent_mode = val ? true : false; 308 new_coherent_mode = val ? true : false;
303 radeon_property_change_mode(&radeon_encoder->base); 309 if (dig->coherent_mode != new_coherent_mode) {
310 dig->coherent_mode = new_coherent_mode;
311 radeon_property_change_mode(&radeon_encoder->base);
312 }
304 } 313 }
305 314
306 if (property == rdev->mode_info.tv_std_property) { 315 if (property == rdev->mode_info.tv_std_property) {
@@ -315,7 +324,7 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
315 radeon_encoder = to_radeon_encoder(encoder); 324 radeon_encoder = to_radeon_encoder(encoder);
316 if (!radeon_encoder->enc_priv) 325 if (!radeon_encoder->enc_priv)
317 return 0; 326 return 0;
318 if (rdev->is_atom_bios) { 327 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) {
319 struct radeon_encoder_atom_dac *dac_int; 328 struct radeon_encoder_atom_dac *dac_int;
320 dac_int = radeon_encoder->enc_priv; 329 dac_int = radeon_encoder->enc_priv;
321 dac_int->tv_std = val; 330 dac_int->tv_std = val;
@@ -1307,6 +1316,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
1307 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1316 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
1308 if (!radeon_connector->ddc_bus) 1317 if (!radeon_connector->ddc_bus)
1309 goto failed; 1318 goto failed;
1319 }
1320 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1310 radeon_connector->dac_load_detect = true; 1321 radeon_connector->dac_load_detect = true;
1311 drm_connector_attach_property(&radeon_connector->base, 1322 drm_connector_attach_property(&radeon_connector->base,
1312 rdev->mode_info.load_detect_property, 1323 rdev->mode_info.load_detect_property,
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index dc6eba6b96dd..2f042a3c0e62 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -417,8 +417,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
417 return -EBUSY; 417 return -EBUSY;
418} 418}
419 419
420static void radeon_init_pipes(drm_radeon_private_t *dev_priv) 420static void radeon_init_pipes(struct drm_device *dev)
421{ 421{
422 drm_radeon_private_t *dev_priv = dev->dev_private;
422 uint32_t gb_tile_config, gb_pipe_sel = 0; 423 uint32_t gb_tile_config, gb_pipe_sel = 0;
423 424
424 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) { 425 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
@@ -434,13 +435,19 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
434 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 435 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
435 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 436 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
436 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 437 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
438 /* SE cards have 1 pipe */
439 if ((dev->pdev->device == 0x5e4c) ||
440 (dev->pdev->device == 0x5e4f))
441 dev_priv->num_gb_pipes = 1;
437 } else { 442 } else {
438 /* R3xx */ 443 /* R3xx */
439 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 444 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
440 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 445 dev->pdev->device != 0x4144) ||
446 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
447 dev->pdev->device != 0x4148)) {
441 dev_priv->num_gb_pipes = 2; 448 dev_priv->num_gb_pipes = 2;
442 } else { 449 } else {
443 /* R3Vxx */ 450 /* RV3xx/R300 AD/R350 AH */
444 dev_priv->num_gb_pipes = 1; 451 dev_priv->num_gb_pipes = 1;
445 } 452 }
446 } 453 }
@@ -736,7 +743,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
736 743
737 /* setup the raster pipes */ 744 /* setup the raster pipes */
738 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 745 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
739 radeon_init_pipes(dev_priv); 746 radeon_init_pipes(dev);
740 747
741 /* Reset the CP ring */ 748 /* Reset the CP ring */
742 radeon_do_cp_reset(dev_priv); 749 radeon_do_cp_reset(dev_priv);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index bddf17f97da8..7b629e305560 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -36,6 +36,54 @@
36#include "radeon.h" 36#include "radeon.h"
37#include "atom.h" 37#include "atom.h"
38 38
39static const char radeon_family_name[][16] = {
40 "R100",
41 "RV100",
42 "RS100",
43 "RV200",
44 "RS200",
45 "R200",
46 "RV250",
47 "RS300",
48 "RV280",
49 "R300",
50 "R350",
51 "RV350",
52 "RV380",
53 "R420",
54 "R423",
55 "RV410",
56 "RS400",
57 "RS480",
58 "RS600",
59 "RS690",
60 "RS740",
61 "RV515",
62 "R520",
63 "RV530",
64 "RV560",
65 "RV570",
66 "R580",
67 "R600",
68 "RV610",
69 "RV630",
70 "RV670",
71 "RV620",
72 "RV635",
73 "RS780",
74 "RS880",
75 "RV770",
76 "RV730",
77 "RV710",
78 "RV740",
79 "CEDAR",
80 "REDWOOD",
81 "JUNIPER",
82 "CYPRESS",
83 "HEMLOCK",
84 "LAST",
85};
86
39/* 87/*
40 * Clear GPU surface registers. 88 * Clear GPU surface registers.
41 */ 89 */
@@ -526,7 +574,6 @@ int radeon_device_init(struct radeon_device *rdev,
526 int r; 574 int r;
527 int dma_bits; 575 int dma_bits;
528 576
529 DRM_INFO("radeon: Initializing kernel modesetting.\n");
530 rdev->shutdown = false; 577 rdev->shutdown = false;
531 rdev->dev = &pdev->dev; 578 rdev->dev = &pdev->dev;
532 rdev->ddev = ddev; 579 rdev->ddev = ddev;
@@ -538,6 +585,10 @@ int radeon_device_init(struct radeon_device *rdev,
538 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 585 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
539 rdev->gpu_lockup = false; 586 rdev->gpu_lockup = false;
540 rdev->accel_working = false; 587 rdev->accel_working = false;
588
589 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
590 radeon_family_name[rdev->family], pdev->vendor, pdev->device);
591
541 /* mutex initialization are all done here so we 592 /* mutex initialization are all done here so we
542 * can recall function without having locking issues */ 593 * can recall function without having locking issues */
543 mutex_init(&rdev->cs_mutex); 594 mutex_init(&rdev->cs_mutex);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index b8d672828246..bb1c122cad21 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -86,12 +86,12 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88 88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id); 89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007); 90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91 91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0); 92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) { 93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR, 94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) | 95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) | 96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0)); 97 (radeon_crtc->lut_b[i] << 0));
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 055a51732dcb..4b05563d99e1 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -43,9 +43,10 @@
43 * - 2.0.0 - initial interface 43 * - 2.0.0 - initial interface
44 * - 2.1.0 - add square tiling interface 44 * - 2.1.0 - add square tiling interface
45 * - 2.2.0 - add r6xx/r7xx const buffer support 45 * - 2.2.0 - add r6xx/r7xx const buffer support
46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
46 */ 47 */
47#define KMS_DRIVER_MAJOR 2 48#define KMS_DRIVER_MAJOR 2
48#define KMS_DRIVER_MINOR 2 49#define KMS_DRIVER_MINOR 3
49#define KMS_DRIVER_PATCHLEVEL 0 50#define KMS_DRIVER_PATCHLEVEL 0
50int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 51int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
51int radeon_driver_unload_kms(struct drm_device *dev); 52int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 52d6f96f274b..c5ddaf58563a 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -254,6 +254,53 @@ radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
254 return dig_connector; 254 return dig_connector;
255} 255}
256 256
257void radeon_panel_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *adjusted_mode)
259{
260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
261 struct drm_device *dev = encoder->dev;
262 struct radeon_device *rdev = dev->dev_private;
263 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
264 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
265 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
266 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
267 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
268 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
269 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
270
271 adjusted_mode->clock = native_mode->clock;
272 adjusted_mode->flags = native_mode->flags;
273
274 if (ASIC_IS_AVIVO(rdev)) {
275 adjusted_mode->hdisplay = native_mode->hdisplay;
276 adjusted_mode->vdisplay = native_mode->vdisplay;
277 }
278
279 adjusted_mode->htotal = native_mode->hdisplay + hblank;
280 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
281 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
282
283 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
284 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
285 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
286
287 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
288
289 if (ASIC_IS_AVIVO(rdev)) {
290 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
291 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
292 }
293
294 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
295 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
296 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
297
298 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
299 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
300 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
301
302}
303
257static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 304static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *mode, 305 struct drm_display_mode *mode,
259 struct drm_display_mode *adjusted_mode) 306 struct drm_display_mode *adjusted_mode)
@@ -275,18 +322,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
275 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 322 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
276 323
277 /* get the native mode for LVDS */ 324 /* get the native mode for LVDS */
278 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 325 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
279 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 326 radeon_panel_mode_fixup(encoder, adjusted_mode);
280 int mode_id = adjusted_mode->base.id;
281 *adjusted_mode = *native_mode;
282 if (!ASIC_IS_AVIVO(rdev)) {
283 adjusted_mode->hdisplay = mode->hdisplay;
284 adjusted_mode->vdisplay = mode->vdisplay;
285 adjusted_mode->crtc_hdisplay = mode->hdisplay;
286 adjusted_mode->crtc_vdisplay = mode->vdisplay;
287 }
288 adjusted_mode->base.id = mode_id;
289 }
290 327
291 /* get the native mode for TV */ 328 /* get the native mode for TV */
292 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 329 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
@@ -317,12 +354,8 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
317 struct radeon_device *rdev = dev->dev_private; 354 struct radeon_device *rdev = dev->dev_private;
318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 355 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
319 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 356 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
320 int index = 0, num = 0; 357 int index = 0;
321 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 358 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
322 enum radeon_tv_std tv_std = TV_STD_NTSC;
323
324 if (dac_info->tv_std)
325 tv_std = dac_info->tv_std;
326 359
327 memset(&args, 0, sizeof(args)); 360 memset(&args, 0, sizeof(args));
328 361
@@ -330,12 +363,10 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
330 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 363 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
331 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 364 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
332 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 365 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
333 num = 1;
334 break; 366 break;
335 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 367 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
336 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 368 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
337 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 369 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
338 num = 2;
339 break; 370 break;
340 } 371 }
341 372
@@ -346,7 +377,7 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
346 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 377 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
347 args.ucDacStandard = ATOM_DAC1_CV; 378 args.ucDacStandard = ATOM_DAC1_CV;
348 else { 379 else {
349 switch (tv_std) { 380 switch (dac_info->tv_std) {
350 case TV_STD_PAL: 381 case TV_STD_PAL:
351 case TV_STD_PAL_M: 382 case TV_STD_PAL_M:
352 case TV_STD_SCART_PAL: 383 case TV_STD_SCART_PAL:
@@ -377,10 +408,6 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
377 TV_ENCODER_CONTROL_PS_ALLOCATION args; 408 TV_ENCODER_CONTROL_PS_ALLOCATION args;
378 int index = 0; 409 int index = 0;
379 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 410 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
380 enum radeon_tv_std tv_std = TV_STD_NTSC;
381
382 if (dac_info->tv_std)
383 tv_std = dac_info->tv_std;
384 411
385 memset(&args, 0, sizeof(args)); 412 memset(&args, 0, sizeof(args));
386 413
@@ -391,7 +418,7 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
391 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 418 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
392 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 419 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
393 else { 420 else {
394 switch (tv_std) { 421 switch (dac_info->tv_std) {
395 case TV_STD_NTSC: 422 case TV_STD_NTSC:
396 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 423 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
397 break; 424 break;
@@ -875,6 +902,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
875 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 902 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
876 if (dig->coherent_mode) 903 if (dig->coherent_mode)
877 args.v3.acConfig.fCoherentMode = 1; 904 args.v3.acConfig.fCoherentMode = 1;
905 if (radeon_encoder->pixel_clock > 165000)
906 args.v3.acConfig.fDualLinkConnector = 1;
878 } 907 }
879 } else if (ASIC_IS_DCE32(rdev)) { 908 } else if (ASIC_IS_DCE32(rdev)) {
880 args.v2.acConfig.ucEncoderSel = dig->dig_encoder; 909 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
@@ -898,6 +927,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
898 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 927 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
899 if (dig->coherent_mode) 928 if (dig->coherent_mode)
900 args.v2.acConfig.fCoherentMode = 1; 929 args.v2.acConfig.fCoherentMode = 1;
930 if (radeon_encoder->pixel_clock > 165000)
931 args.v2.acConfig.fDualLinkConnector = 1;
901 } 932 }
902 } else { 933 } else {
903 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 934 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
@@ -1332,7 +1363,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1332 1363
1333 radeon_encoder->pixel_clock = adjusted_mode->clock; 1364 radeon_encoder->pixel_clock = adjusted_mode->clock;
1334 1365
1335 if (ASIC_IS_AVIVO(rdev)) { 1366 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1336 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1367 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1337 atombios_yuv_setup(encoder, true); 1368 atombios_yuv_setup(encoder, true);
1338 else 1369 else
@@ -1383,8 +1414,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1383 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1414 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1384 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1415 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1385 atombios_dac_setup(encoder, ATOM_ENABLE); 1416 atombios_dac_setup(encoder, ATOM_ENABLE);
1386 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1417 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1387 atombios_tv_setup(encoder, ATOM_ENABLE); 1418 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1419 atombios_tv_setup(encoder, ATOM_ENABLE);
1420 else
1421 atombios_tv_setup(encoder, ATOM_DISABLE);
1422 }
1388 break; 1423 break;
1389 } 1424 }
1390 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1425 atombios_apply_encoder_quirks(encoder, adjusted_mode);
@@ -1558,12 +1593,14 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1558struct radeon_encoder_atom_dac * 1593struct radeon_encoder_atom_dac *
1559radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 1594radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1560{ 1595{
1596 struct drm_device *dev = radeon_encoder->base.dev;
1597 struct radeon_device *rdev = dev->dev_private;
1561 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 1598 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1562 1599
1563 if (!dac) 1600 if (!dac)
1564 return NULL; 1601 return NULL;
1565 1602
1566 dac->tv_std = TV_STD_NTSC; 1603 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1567 return dac; 1604 return dac;
1568} 1605}
1569 1606
@@ -1641,6 +1678,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1641 break; 1678 break;
1642 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1679 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1643 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 1680 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1681 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1644 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 1682 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1645 break; 1683 break;
1646 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1684 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 93c7d5d41914..e329066dcabd 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -36,7 +36,7 @@
36 * Radeon chip families 36 * Radeon chip families
37 */ 37 */
38enum radeon_family { 38enum radeon_family {
39 CHIP_R100, 39 CHIP_R100 = 0,
40 CHIP_RV100, 40 CHIP_RV100,
41 CHIP_RS100, 41 CHIP_RS100,
42 CHIP_RV200, 42 CHIP_RV200,
@@ -99,4 +99,5 @@ enum radeon_chip_flags {
99 RADEON_IS_PCI = 0x00800000UL, 99 RADEON_IS_PCI = 0x00800000UL,
100 RADEON_IS_IGPGART = 0x01000000UL, 100 RADEON_IS_IGPGART = 0x01000000UL,
101}; 101};
102
102#endif 103#endif
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index d3657dcfdd26..c633319f98ed 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -165,7 +165,7 @@ u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
165{ 165{
166 struct radeon_device *rdev = dev->dev_private; 166 struct radeon_device *rdev = dev->dev_private;
167 167
168 if (crtc < 0 || crtc > 1) { 168 if (crtc < 0 || crtc >= rdev->num_crtc) {
169 DRM_ERROR("Invalid crtc %d\n", crtc); 169 DRM_ERROR("Invalid crtc %d\n", crtc);
170 return -EINVAL; 170 return -EINVAL;
171 } 171 }
@@ -177,7 +177,7 @@ int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
177{ 177{
178 struct radeon_device *rdev = dev->dev_private; 178 struct radeon_device *rdev = dev->dev_private;
179 179
180 if (crtc < 0 || crtc > 1) { 180 if (crtc < 0 || crtc >= rdev->num_crtc) {
181 DRM_ERROR("Invalid crtc %d\n", crtc); 181 DRM_ERROR("Invalid crtc %d\n", crtc);
182 return -EINVAL; 182 return -EINVAL;
183 } 183 }
@@ -191,7 +191,7 @@ void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
191{ 191{
192 struct radeon_device *rdev = dev->dev_private; 192 struct radeon_device *rdev = dev->dev_private;
193 193
194 if (crtc < 0 || crtc > 1) { 194 if (crtc < 0 || crtc >= rdev->num_crtc) {
195 DRM_ERROR("Invalid crtc %d\n", crtc); 195 DRM_ERROR("Invalid crtc %d\n", crtc);
196 return; 196 return;
197 } 197 }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index cf389ce50a8a..0274abe17ad9 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -228,16 +228,8 @@ static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
228 drm_mode_set_crtcinfo(adjusted_mode, 0); 228 drm_mode_set_crtcinfo(adjusted_mode, 0);
229 229
230 /* get the native mode for LVDS */ 230 /* get the native mode for LVDS */
231 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 231 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
232 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 232 radeon_panel_mode_fixup(encoder, adjusted_mode);
233 int mode_id = adjusted_mode->base.id;
234 *adjusted_mode = *native_mode;
235 adjusted_mode->hdisplay = mode->hdisplay;
236 adjusted_mode->vdisplay = mode->vdisplay;
237 adjusted_mode->crtc_hdisplay = mode->hdisplay;
238 adjusted_mode->crtc_vdisplay = mode->vdisplay;
239 adjusted_mode->base.id = mode_id;
240 }
241 233
242 return true; 234 return true;
243} 235}
@@ -830,8 +822,8 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
830 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 822 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
831 823
832 if (rdev->family == CHIP_R420 || 824 if (rdev->family == CHIP_R420 ||
833 rdev->family == CHIP_R423 || 825 rdev->family == CHIP_R423 ||
834 rdev->family == CHIP_RV410) 826 rdev->family == CHIP_RV410)
835 tv_dac_cntl |= (R420_TV_DAC_RDACPD | 827 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
836 R420_TV_DAC_GDACPD | 828 R420_TV_DAC_GDACPD |
837 R420_TV_DAC_BDACPD | 829 R420_TV_DAC_BDACPD |
@@ -907,35 +899,43 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
907 if (rdev->family != CHIP_R200) { 899 if (rdev->family != CHIP_R200) {
908 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 900 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
909 if (rdev->family == CHIP_R420 || 901 if (rdev->family == CHIP_R420 ||
910 rdev->family == CHIP_R423 || 902 rdev->family == CHIP_R423 ||
911 rdev->family == CHIP_RV410) { 903 rdev->family == CHIP_RV410) {
912 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 904 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
913 RADEON_TV_DAC_BGADJ_MASK | 905 RADEON_TV_DAC_BGADJ_MASK |
914 R420_TV_DAC_DACADJ_MASK | 906 R420_TV_DAC_DACADJ_MASK |
915 R420_TV_DAC_RDACPD | 907 R420_TV_DAC_RDACPD |
916 R420_TV_DAC_GDACPD | 908 R420_TV_DAC_GDACPD |
917 R420_TV_DAC_BDACPD | 909 R420_TV_DAC_BDACPD |
918 R420_TV_DAC_TVENABLE); 910 R420_TV_DAC_TVENABLE);
919 } else { 911 } else {
920 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 912 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
921 RADEON_TV_DAC_BGADJ_MASK | 913 RADEON_TV_DAC_BGADJ_MASK |
922 RADEON_TV_DAC_DACADJ_MASK | 914 RADEON_TV_DAC_DACADJ_MASK |
923 RADEON_TV_DAC_RDACPD | 915 RADEON_TV_DAC_RDACPD |
924 RADEON_TV_DAC_GDACPD | 916 RADEON_TV_DAC_GDACPD |
925 RADEON_TV_DAC_BDACPD); 917 RADEON_TV_DAC_BDACPD);
926 } 918 }
927 919
928 /* FIXME TV */ 920 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
929 if (tv_dac) { 921
930 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 922 if (is_tv) {
931 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 923 if (tv_dac->tv_std == TV_STD_NTSC ||
932 RADEON_TV_DAC_NHOLD | 924 tv_dac->tv_std == TV_STD_NTSC_J ||
933 RADEON_TV_DAC_STD_PS2 | 925 tv_dac->tv_std == TV_STD_PAL_M ||
934 tv_dac->ps2_tvdac_adj); 926 tv_dac->tv_std == TV_STD_PAL_60)
927 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
928 else
929 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
930
931 if (tv_dac->tv_std == TV_STD_NTSC ||
932 tv_dac->tv_std == TV_STD_NTSC_J)
933 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
934 else
935 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
935 } else 936 } else
936 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 937 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
937 RADEON_TV_DAC_NHOLD | 938 tv_dac->ps2_tvdac_adj);
938 RADEON_TV_DAC_STD_PS2);
939 939
940 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 940 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
941 } 941 }
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 0b8e32776b10..5413fcd63086 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -558,6 +558,8 @@ extern int radeon_static_clocks_init(struct drm_device *dev);
558bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 558bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
559 struct drm_display_mode *mode, 559 struct drm_display_mode *mode,
560 struct drm_display_mode *adjusted_mode); 560 struct drm_display_mode *adjusted_mode);
561void radeon_panel_mode_fixup(struct drm_encoder *encoder,
562 struct drm_display_mode *adjusted_mode);
561void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 563void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
562 564
563/* legacy tv */ 565/* legacy tv */
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
index 19c4663fa9c6..1e97b2d129fd 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r300
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -125,6 +125,8 @@ r300 0x4f60
1250x4000 GB_VAP_RASTER_VTX_FMT_0 1250x4000 GB_VAP_RASTER_VTX_FMT_0
1260x4004 GB_VAP_RASTER_VTX_FMT_1 1260x4004 GB_VAP_RASTER_VTX_FMT_1
1270x4008 GB_ENABLE 1270x4008 GB_ENABLE
1280x4010 GB_MSPOS0
1290x4014 GB_MSPOS1
1280x401C GB_SELECT 1300x401C GB_SELECT
1290x4020 GB_AA_CONFIG 1310x4020 GB_AA_CONFIG
1300x4024 GB_FIFO_SIZE 1320x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
index 989f7a020832..e958980d00f1 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r420
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -125,6 +125,8 @@ r420 0x4f60
1250x4000 GB_VAP_RASTER_VTX_FMT_0 1250x4000 GB_VAP_RASTER_VTX_FMT_0
1260x4004 GB_VAP_RASTER_VTX_FMT_1 1260x4004 GB_VAP_RASTER_VTX_FMT_1
1270x4008 GB_ENABLE 1270x4008 GB_ENABLE
1280x4010 GB_MSPOS0
1290x4014 GB_MSPOS1
1280x401C GB_SELECT 1300x401C GB_SELECT
1290x4020 GB_AA_CONFIG 1310x4020 GB_AA_CONFIG
1300x4024 GB_FIFO_SIZE 1320x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 6801b865d1c4..83e8bc0c2bb2 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -125,6 +125,8 @@ rs600 0x6d40
1250x4000 GB_VAP_RASTER_VTX_FMT_0 1250x4000 GB_VAP_RASTER_VTX_FMT_0
1260x4004 GB_VAP_RASTER_VTX_FMT_1 1260x4004 GB_VAP_RASTER_VTX_FMT_1
1270x4008 GB_ENABLE 1270x4008 GB_ENABLE
1280x4010 GB_MSPOS0
1290x4014 GB_MSPOS1
1280x401C GB_SELECT 1300x401C GB_SELECT
1290x4020 GB_AA_CONFIG 1310x4020 GB_AA_CONFIG
1300x4024 GB_FIFO_SIZE 1320x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 38abf63bf2cd..1e46233985eb 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -35,6 +35,7 @@ rv515 0x6d40
350x1DA8 VAP_VPORT_ZSCALE 350x1DA8 VAP_VPORT_ZSCALE
360x1DAC VAP_VPORT_ZOFFSET 360x1DAC VAP_VPORT_ZOFFSET
370x2080 VAP_CNTL 370x2080 VAP_CNTL
380x208C VAP_INDEX_OFFSET
380x2090 VAP_OUT_VTX_FMT_0 390x2090 VAP_OUT_VTX_FMT_0
390x2094 VAP_OUT_VTX_FMT_1 400x2094 VAP_OUT_VTX_FMT_1
400x20B0 VAP_VTE_CNTL 410x20B0 VAP_VTE_CNTL
@@ -158,6 +159,8 @@ rv515 0x6d40
1580x4000 GB_VAP_RASTER_VTX_FMT_0 1590x4000 GB_VAP_RASTER_VTX_FMT_0
1590x4004 GB_VAP_RASTER_VTX_FMT_1 1600x4004 GB_VAP_RASTER_VTX_FMT_1
1600x4008 GB_ENABLE 1610x4008 GB_ENABLE
1620x4010 GB_MSPOS0
1630x4014 GB_MSPOS1
1610x401C GB_SELECT 1640x401C GB_SELECT
1620x4020 GB_AA_CONFIG 1650x4020 GB_AA_CONFIG
1630x4024 GB_FIFO_SIZE 1660x4024 GB_FIFO_SIZE
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index abf824c2123d..a81bc7a21e14 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -159,7 +159,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
159 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 159 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
160 160
161 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 161 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
162 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); 162 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
163 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 163 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
164 164
165 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 165 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
diff --git a/drivers/gpu/drm/via/via_video.c b/drivers/gpu/drm/via/via_video.c
index 6ec04ac12459..6efac8117c93 100644
--- a/drivers/gpu/drm/via/via_video.c
+++ b/drivers/gpu/drm/via/via_video.c
@@ -75,7 +75,7 @@ int via_decoder_futex(struct drm_device *dev, void *data, struct drm_file *file_
75 75
76 DRM_DEBUG("\n"); 76 DRM_DEBUG("\n");
77 77
78 if (fx->lock > VIA_NR_XVMC_LOCKS) 78 if (fx->lock >= VIA_NR_XVMC_LOCKS)
79 return -EFAULT; 79 return -EFAULT;
80 80
81 lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx->lock); 81 lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx->lock);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 19:42:37 -0500