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-rw-r--r--drivers/gpu/drm/drm_crtc.c3
-rw-r--r--drivers/gpu/drm/drm_gem.c1
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c16
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c48
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c14
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h35
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c52
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c4
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c89
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c16
-rw-r--r--drivers/gpu/drm/i915/intel_display.c308
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c118
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c12
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c59
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_perf.c5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c17
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c194
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c9
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
-rw-r--r--drivers/gpu/drm/radeon/ni.c1
-rw-r--r--drivers/gpu/drm/radeon/nid.h2
-rw-r--r--drivers/gpu/drm/radeon/r600.c19
-rw-r--r--drivers/gpu/drm/radeon/r600d.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c40
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h2
-rw-r--r--drivers/gpu/drm/radeon/rs600.c6
-rw-r--r--drivers/gpu/drm/radeon/rv770.c10
-rw-r--r--drivers/gpu/drm/ttm/ttm_tt.c5
36 files changed, 741 insertions, 401 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 21058e6ad2b8..82db18506662 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -886,9 +886,6 @@ int drm_mode_group_init(struct drm_device *dev, struct drm_mode_group *group)
886 total_objects += dev->mode_config.num_connector; 886 total_objects += dev->mode_config.num_connector;
887 total_objects += dev->mode_config.num_encoder; 887 total_objects += dev->mode_config.num_encoder;
888 888
889 if (total_objects == 0)
890 return -EINVAL;
891
892 group->id_list = kzalloc(total_objects * sizeof(uint32_t), GFP_KERNEL); 889 group->id_list = kzalloc(total_objects * sizeof(uint32_t), GFP_KERNEL);
893 if (!group->id_list) 890 if (!group->id_list)
894 return -ENOMEM; 891 return -ENOMEM;
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 74e4ff578017..4012fe423460 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -34,6 +34,7 @@
34#include <linux/module.h> 34#include <linux/module.h>
35#include <linux/mman.h> 35#include <linux/mman.h>
36#include <linux/pagemap.h> 36#include <linux/pagemap.h>
37#include <linux/shmem_fs.h>
37#include "drmP.h" 38#include "drmP.h"
38 39
39/** @file drm_gem.c 40/** @file drm_gem.c
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4d46441cbe2d..0a893f7400fa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1207,13 +1207,17 @@ static int i915_context_status(struct seq_file *m, void *unused)
1207 if (ret) 1207 if (ret)
1208 return ret; 1208 return ret;
1209 1209
1210 seq_printf(m, "power context "); 1210 if (dev_priv->pwrctx) {
1211 describe_obj(m, dev_priv->pwrctx); 1211 seq_printf(m, "power context ");
1212 seq_printf(m, "\n"); 1212 describe_obj(m, dev_priv->pwrctx);
1213 seq_printf(m, "\n");
1214 }
1213 1215
1214 seq_printf(m, "render context "); 1216 if (dev_priv->renderctx) {
1215 describe_obj(m, dev_priv->renderctx); 1217 seq_printf(m, "render context ");
1216 seq_printf(m, "\n"); 1218 describe_obj(m, dev_priv->renderctx);
1219 seq_printf(m, "\n");
1220 }
1217 1221
1218 mutex_unlock(&dev->mode_config.mutex); 1222 mutex_unlock(&dev->mode_config.mutex);
1219 1223
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0239e9974bf2..296fbd66f0e1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1266,30 +1266,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
1266 1266
1267 intel_modeset_gem_init(dev); 1267 intel_modeset_gem_init(dev);
1268 1268
1269 if (IS_IVYBRIDGE(dev)) {
1270 /* Share pre & uninstall handlers with ILK/SNB */
1271 dev->driver->irq_handler = ivybridge_irq_handler;
1272 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1273 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
1274 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1275 dev->driver->enable_vblank = ivybridge_enable_vblank;
1276 dev->driver->disable_vblank = ivybridge_disable_vblank;
1277 } else if (HAS_PCH_SPLIT(dev)) {
1278 dev->driver->irq_handler = ironlake_irq_handler;
1279 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1280 dev->driver->irq_postinstall = ironlake_irq_postinstall;
1281 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1282 dev->driver->enable_vblank = ironlake_enable_vblank;
1283 dev->driver->disable_vblank = ironlake_disable_vblank;
1284 } else {
1285 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
1286 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
1287 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
1288 dev->driver->irq_handler = i915_driver_irq_handler;
1289 dev->driver->enable_vblank = i915_enable_vblank;
1290 dev->driver->disable_vblank = i915_disable_vblank;
1291 }
1292
1293 ret = drm_irq_install(dev); 1269 ret = drm_irq_install(dev);
1294 if (ret) 1270 if (ret)
1295 goto cleanup_gem; 1271 goto cleanup_gem;
@@ -1967,7 +1943,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1967 if (!dev_priv->mm.gtt) { 1943 if (!dev_priv->mm.gtt) {
1968 DRM_ERROR("Failed to initialize GTT\n"); 1944 DRM_ERROR("Failed to initialize GTT\n");
1969 ret = -ENODEV; 1945 ret = -ENODEV;
1970 goto out_iomapfree; 1946 goto out_rmmap;
1971 } 1947 }
1972 1948
1973 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; 1949 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
@@ -2011,18 +1987,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2011 if (dev_priv->wq == NULL) { 1987 if (dev_priv->wq == NULL) {
2012 DRM_ERROR("Failed to create our workqueue.\n"); 1988 DRM_ERROR("Failed to create our workqueue.\n");
2013 ret = -ENOMEM; 1989 ret = -ENOMEM;
2014 goto out_iomapfree; 1990 goto out_mtrrfree;
2015 } 1991 }
2016 1992
2017 /* enable GEM by default */ 1993 /* enable GEM by default */
2018 dev_priv->has_gem = 1; 1994 dev_priv->has_gem = 1;
2019 1995
2020 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1996 intel_irq_init(dev);
2021 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2022 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2023 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2024 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2025 }
2026 1997
2027 /* Try to make sure MCHBAR is enabled before poking at it */ 1998 /* Try to make sure MCHBAR is enabled before poking at it */
2028 intel_setup_mchbar(dev); 1999 intel_setup_mchbar(dev);
@@ -2103,13 +2074,21 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2103 return 0; 2074 return 0;
2104 2075
2105out_gem_unload: 2076out_gem_unload:
2077 if (dev_priv->mm.inactive_shrinker.shrink)
2078 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2079
2106 if (dev->pdev->msi_enabled) 2080 if (dev->pdev->msi_enabled)
2107 pci_disable_msi(dev->pdev); 2081 pci_disable_msi(dev->pdev);
2108 2082
2109 intel_teardown_gmbus(dev); 2083 intel_teardown_gmbus(dev);
2110 intel_teardown_mchbar(dev); 2084 intel_teardown_mchbar(dev);
2111 destroy_workqueue(dev_priv->wq); 2085 destroy_workqueue(dev_priv->wq);
2112out_iomapfree: 2086out_mtrrfree:
2087 if (dev_priv->mm.gtt_mtrr >= 0) {
2088 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2089 dev->agp->agp_info.aper_size * 1024 * 1024);
2090 dev_priv->mm.gtt_mtrr = -1;
2091 }
2113 io_mapping_free(dev_priv->mm.gtt_mapping); 2092 io_mapping_free(dev_priv->mm.gtt_mapping);
2114out_rmmap: 2093out_rmmap:
2115 pci_iounmap(dev->pdev, dev_priv->regs); 2094 pci_iounmap(dev->pdev, dev_priv->regs);
@@ -2182,9 +2161,8 @@ int i915_driver_unload(struct drm_device *dev)
2182 /* Flush any outstanding unpin_work. */ 2161 /* Flush any outstanding unpin_work. */
2183 flush_workqueue(dev_priv->wq); 2162 flush_workqueue(dev_priv->wq);
2184 2163
2185 i915_gem_free_all_phys_object(dev);
2186
2187 mutex_lock(&dev->struct_mutex); 2164 mutex_lock(&dev->struct_mutex);
2165 i915_gem_free_all_phys_object(dev);
2188 i915_gem_cleanup_ringbuffer(dev); 2166 i915_gem_cleanup_ringbuffer(dev);
2189 mutex_unlock(&dev->struct_mutex); 2167 mutex_unlock(&dev->struct_mutex);
2190 if (I915_HAS_FBC(dev) && i915_powersave) 2168 if (I915_HAS_FBC(dev) && i915_powersave)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0defd4270594..eb91e2dd7914 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -52,7 +52,7 @@ module_param_named(powersave, i915_powersave, int, 0600);
52unsigned int i915_semaphores = 0; 52unsigned int i915_semaphores = 0;
53module_param_named(semaphores, i915_semaphores, int, 0600); 53module_param_named(semaphores, i915_semaphores, int, 0600);
54 54
55unsigned int i915_enable_rc6 = 1; 55unsigned int i915_enable_rc6 = 0;
56module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); 56module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
57 57
58unsigned int i915_enable_fbc = 0; 58unsigned int i915_enable_fbc = 0;
@@ -577,8 +577,12 @@ int i915_reset(struct drm_device *dev, u8 flags)
577 if (get_seconds() - dev_priv->last_gpu_reset < 5) { 577 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
578 DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); 578 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
579 } else switch (INTEL_INFO(dev)->gen) { 579 } else switch (INTEL_INFO(dev)->gen) {
580 case 7:
580 case 6: 581 case 6:
581 ret = gen6_do_reset(dev, flags); 582 ret = gen6_do_reset(dev, flags);
583 /* If reset with a user forcewake, try to restore */
584 if (atomic_read(&dev_priv->forcewake_count))
585 __gen6_gt_force_wake_get(dev_priv);
582 break; 586 break;
583 case 5: 587 case 5:
584 ret = ironlake_do_reset(dev, flags); 588 ret = ironlake_do_reset(dev, flags);
@@ -762,14 +766,6 @@ static struct drm_driver driver = {
762 .resume = i915_resume, 766 .resume = i915_resume,
763 767
764 .device_is_agp = i915_driver_device_is_agp, 768 .device_is_agp = i915_driver_device_is_agp,
765 .enable_vblank = i915_enable_vblank,
766 .disable_vblank = i915_disable_vblank,
767 .get_vblank_timestamp = i915_get_vblank_timestamp,
768 .get_scanout_position = i915_get_crtc_scanoutpos,
769 .irq_preinstall = i915_driver_irq_preinstall,
770 .irq_postinstall = i915_driver_irq_postinstall,
771 .irq_uninstall = i915_driver_irq_uninstall,
772 .irq_handler = i915_driver_irq_handler,
773 .reclaim_buffers = drm_core_reclaim_buffers, 769 .reclaim_buffers = drm_core_reclaim_buffers,
774 .master_create = i915_master_create, 770 .master_create = i915_master_create,
775 .master_destroy = i915_master_destroy, 771 .master_destroy = i915_master_destroy,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f63ee162f124..f245c588ae95 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -211,6 +211,9 @@ struct drm_i915_display_funcs {
211 void (*fdi_link_train)(struct drm_crtc *crtc); 211 void (*fdi_link_train)(struct drm_crtc *crtc);
212 void (*init_clock_gating)(struct drm_device *dev); 212 void (*init_clock_gating)(struct drm_device *dev);
213 void (*init_pch_clock_gating)(struct drm_device *dev); 213 void (*init_pch_clock_gating)(struct drm_device *dev);
214 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
215 struct drm_framebuffer *fb,
216 struct drm_i915_gem_object *obj);
214 /* clock updates for mode set */ 217 /* clock updates for mode set */
215 /* cursor updates */ 218 /* cursor updates */
216 /* render clock increase/decrease */ 219 /* render clock increase/decrease */
@@ -994,8 +997,6 @@ extern unsigned int i915_enable_fbc;
994 997
995extern int i915_suspend(struct drm_device *dev, pm_message_t state); 998extern int i915_suspend(struct drm_device *dev, pm_message_t state);
996extern int i915_resume(struct drm_device *dev); 999extern int i915_resume(struct drm_device *dev);
997extern void i915_save_display(struct drm_device *dev);
998extern void i915_restore_display(struct drm_device *dev);
999extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1000extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1000extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1001extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1001 1002
@@ -1030,33 +1031,12 @@ extern int i915_irq_emit(struct drm_device *dev, void *data,
1030extern int i915_irq_wait(struct drm_device *dev, void *data, 1031extern int i915_irq_wait(struct drm_device *dev, void *data,
1031 struct drm_file *file_priv); 1032 struct drm_file *file_priv);
1032 1033
1033extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 1034extern void intel_irq_init(struct drm_device *dev);
1034extern void i915_driver_irq_preinstall(struct drm_device * dev);
1035extern int i915_driver_irq_postinstall(struct drm_device *dev);
1036extern void i915_driver_irq_uninstall(struct drm_device * dev);
1037
1038extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
1039extern void ironlake_irq_preinstall(struct drm_device *dev);
1040extern int ironlake_irq_postinstall(struct drm_device *dev);
1041extern void ironlake_irq_uninstall(struct drm_device *dev);
1042
1043extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
1044extern void ivybridge_irq_preinstall(struct drm_device *dev);
1045extern int ivybridge_irq_postinstall(struct drm_device *dev);
1046extern void ivybridge_irq_uninstall(struct drm_device *dev);
1047 1035
1048extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1036extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv); 1037 struct drm_file *file_priv);
1050extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1038extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv); 1039 struct drm_file *file_priv);
1052extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1053extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1054extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
1055extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
1056extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
1057extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
1058extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1059extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1060extern int i915_vblank_swap(struct drm_device *dev, void *data, 1040extern int i915_vblank_swap(struct drm_device *dev, void *data,
1061 struct drm_file *file_priv); 1041 struct drm_file *file_priv);
1062 1042
@@ -1067,13 +1047,6 @@ void
1067i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1047i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1068 1048
1069void intel_enable_asle (struct drm_device *dev); 1049void intel_enable_asle (struct drm_device *dev);
1070int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1071 int *max_error,
1072 struct timeval *vblank_time,
1073 unsigned flags);
1074
1075int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1076 int *vpos, int *hpos);
1077 1050
1078#ifdef CONFIG_DEBUG_FS 1051#ifdef CONFIG_DEBUG_FS
1079extern void i915_destroy_error_state(struct drm_device *dev); 1052extern void i915_destroy_error_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 94c84d744100..5c0d1247f453 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -31,6 +31,7 @@
31#include "i915_drv.h" 31#include "i915_drv.h"
32#include "i915_trace.h" 32#include "i915_trace.h"
33#include "intel_drv.h" 33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
34#include <linux/slab.h> 35#include <linux/slab.h>
35#include <linux/swap.h> 36#include <linux/swap.h>
36#include <linux/pci.h> 37#include <linux/pci.h>
@@ -359,8 +360,7 @@ i915_gem_shmem_pread_fast(struct drm_device *dev,
359 if ((page_offset + remain) > PAGE_SIZE) 360 if ((page_offset + remain) > PAGE_SIZE)
360 page_length = PAGE_SIZE - page_offset; 361 page_length = PAGE_SIZE - page_offset;
361 362
362 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 363 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
363 GFP_HIGHUSER | __GFP_RECLAIMABLE);
364 if (IS_ERR(page)) 364 if (IS_ERR(page))
365 return PTR_ERR(page); 365 return PTR_ERR(page);
366 366
@@ -463,8 +463,7 @@ i915_gem_shmem_pread_slow(struct drm_device *dev,
463 if ((data_page_offset + page_length) > PAGE_SIZE) 463 if ((data_page_offset + page_length) > PAGE_SIZE)
464 page_length = PAGE_SIZE - data_page_offset; 464 page_length = PAGE_SIZE - data_page_offset;
465 465
466 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 466 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
467 GFP_HIGHUSER | __GFP_RECLAIMABLE);
468 if (IS_ERR(page)) { 467 if (IS_ERR(page)) {
469 ret = PTR_ERR(page); 468 ret = PTR_ERR(page);
470 goto out; 469 goto out;
@@ -797,8 +796,7 @@ i915_gem_shmem_pwrite_fast(struct drm_device *dev,
797 if ((page_offset + remain) > PAGE_SIZE) 796 if ((page_offset + remain) > PAGE_SIZE)
798 page_length = PAGE_SIZE - page_offset; 797 page_length = PAGE_SIZE - page_offset;
799 798
800 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 799 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
801 GFP_HIGHUSER | __GFP_RECLAIMABLE);
802 if (IS_ERR(page)) 800 if (IS_ERR(page))
803 return PTR_ERR(page); 801 return PTR_ERR(page);
804 802
@@ -907,8 +905,7 @@ i915_gem_shmem_pwrite_slow(struct drm_device *dev,
907 if ((data_page_offset + page_length) > PAGE_SIZE) 905 if ((data_page_offset + page_length) > PAGE_SIZE)
908 page_length = PAGE_SIZE - data_page_offset; 906 page_length = PAGE_SIZE - data_page_offset;
909 907
910 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, 908 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
911 GFP_HIGHUSER | __GFP_RECLAIMABLE);
912 if (IS_ERR(page)) { 909 if (IS_ERR(page)) {
913 ret = PTR_ERR(page); 910 ret = PTR_ERR(page);
914 goto out; 911 goto out;
@@ -1219,11 +1216,11 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1219 ret = i915_gem_object_bind_to_gtt(obj, 0, true); 1216 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1220 if (ret) 1217 if (ret)
1221 goto unlock; 1218 goto unlock;
1222 }
1223 1219
1224 ret = i915_gem_object_set_to_gtt_domain(obj, write); 1220 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1225 if (ret) 1221 if (ret)
1226 goto unlock; 1222 goto unlock;
1223 }
1227 1224
1228 if (obj->tiling_mode == I915_TILING_NONE) 1225 if (obj->tiling_mode == I915_TILING_NONE)
1229 ret = i915_gem_object_put_fence(obj); 1226 ret = i915_gem_object_put_fence(obj);
@@ -1558,12 +1555,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1558 1555
1559 inode = obj->base.filp->f_path.dentry->d_inode; 1556 inode = obj->base.filp->f_path.dentry->d_inode;
1560 mapping = inode->i_mapping; 1557 mapping = inode->i_mapping;
1558 gfpmask |= mapping_gfp_mask(mapping);
1559
1561 for (i = 0; i < page_count; i++) { 1560 for (i = 0; i < page_count; i++) {
1562 page = read_cache_page_gfp(mapping, i, 1561 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1563 GFP_HIGHUSER |
1564 __GFP_COLD |
1565 __GFP_RECLAIMABLE |
1566 gfpmask);
1567 if (IS_ERR(page)) 1562 if (IS_ERR(page))
1568 goto err_pages; 1563 goto err_pages;
1569 1564
@@ -1701,13 +1696,10 @@ i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1701 /* Our goal here is to return as much of the memory as 1696 /* Our goal here is to return as much of the memory as
1702 * is possible back to the system as we are called from OOM. 1697 * is possible back to the system as we are called from OOM.
1703 * To do this we must instruct the shmfs to drop all of its 1698 * To do this we must instruct the shmfs to drop all of its
1704 * backing pages, *now*. Here we mirror the actions taken 1699 * backing pages, *now*.
1705 * when by shmem_delete_inode() to release the backing store.
1706 */ 1700 */
1707 inode = obj->base.filp->f_path.dentry->d_inode; 1701 inode = obj->base.filp->f_path.dentry->d_inode;
1708 truncate_inode_pages(inode->i_mapping, 0); 1702 shmem_truncate_range(inode, 0, (loff_t)-1);
1709 if (inode->i_op->truncate_range)
1710 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1711 1703
1712 obj->madv = __I915_MADV_PURGED; 1704 obj->madv = __I915_MADV_PURGED;
1713} 1705}
@@ -2080,8 +2072,8 @@ i915_wait_request(struct intel_ring_buffer *ring,
2080 if (!ier) { 2072 if (!ier) {
2081 DRM_ERROR("something (likely vbetool) disabled " 2073 DRM_ERROR("something (likely vbetool) disabled "
2082 "interrupts, re-enabling\n"); 2074 "interrupts, re-enabling\n");
2083 i915_driver_irq_preinstall(ring->dev); 2075 ring->dev->driver->irq_preinstall(ring->dev);
2084 i915_driver_irq_postinstall(ring->dev); 2076 ring->dev->driver->irq_postinstall(ring->dev);
2085 } 2077 }
2086 2078
2087 trace_i915_gem_request_wait_begin(ring, seqno); 2079 trace_i915_gem_request_wait_begin(ring, seqno);
@@ -2926,8 +2918,6 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2926 */ 2918 */
2927 wmb(); 2919 wmb();
2928 2920
2929 i915_gem_release_mmap(obj);
2930
2931 old_write_domain = obj->base.write_domain; 2921 old_write_domain = obj->base.write_domain;
2932 obj->base.write_domain = 0; 2922 obj->base.write_domain = 0;
2933 2923
@@ -3567,6 +3557,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3567{ 3557{
3568 struct drm_i915_private *dev_priv = dev->dev_private; 3558 struct drm_i915_private *dev_priv = dev->dev_private;
3569 struct drm_i915_gem_object *obj; 3559 struct drm_i915_gem_object *obj;
3560 struct address_space *mapping;
3570 3561
3571 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 3562 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3572 if (obj == NULL) 3563 if (obj == NULL)
@@ -3577,6 +3568,9 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3577 return NULL; 3568 return NULL;
3578 } 3569 }
3579 3570
3571 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3572 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3573
3580 i915_gem_info_add_obj(dev_priv, size); 3574 i915_gem_info_add_obj(dev_priv, size);
3581 3575
3582 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 3576 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
@@ -3952,8 +3946,7 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
3952 3946
3953 page_count = obj->base.size / PAGE_SIZE; 3947 page_count = obj->base.size / PAGE_SIZE;
3954 for (i = 0; i < page_count; i++) { 3948 for (i = 0; i < page_count; i++) {
3955 struct page *page = read_cache_page_gfp(mapping, i, 3949 struct page *page = shmem_read_mapping_page(mapping, i);
3956 GFP_HIGHUSER | __GFP_RECLAIMABLE);
3957 if (!IS_ERR(page)) { 3950 if (!IS_ERR(page)) {
3958 char *dst = kmap_atomic(page); 3951 char *dst = kmap_atomic(page);
3959 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); 3952 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
@@ -4014,8 +4007,7 @@ i915_gem_attach_phys_object(struct drm_device *dev,
4014 struct page *page; 4007 struct page *page;
4015 char *dst, *src; 4008 char *dst, *src;
4016 4009
4017 page = read_cache_page_gfp(mapping, i, 4010 page = shmem_read_mapping_page(mapping, i);
4018 GFP_HIGHUSER | __GFP_RECLAIMABLE);
4019 if (IS_ERR(page)) 4011 if (IS_ERR(page))
4020 return PTR_ERR(page); 4012 return PTR_ERR(page);
4021 4013
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 20a4cc5b818f..4934cf84c320 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -187,10 +187,6 @@ i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
187 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) 187 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
188 i915_gem_clflush_object(obj); 188 i915_gem_clflush_object(obj);
189 189
190 /* blow away mappings if mapped through GTT */
191 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT)
192 i915_gem_release_mmap(obj);
193
194 if (obj->base.pending_write_domain) 190 if (obj->base.pending_write_domain)
195 cd->flips |= atomic_read(&obj->pending_flip); 191 cd->flips |= atomic_read(&obj->pending_flip);
196 192
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b9fafe3b045b..3b03f85ea627 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -152,7 +152,7 @@ i915_pipe_enabled(struct drm_device *dev, int pipe)
152/* Called from drm generic code, passed a 'crtc', which 152/* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index 153 * we use as a pipe index
154 */ 154 */
155u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 155static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
156{ 156{
157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
158 unsigned long high_frame; 158 unsigned long high_frame;
@@ -184,7 +184,7 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
184 return (high1 << 8) | low; 184 return (high1 << 8) | low;
185} 185}
186 186
187u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 187static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
188{ 188{
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
190 int reg = PIPE_FRMCOUNT_GM45(pipe); 190 int reg = PIPE_FRMCOUNT_GM45(pipe);
@@ -198,7 +198,7 @@ u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198 return I915_READ(reg); 198 return I915_READ(reg);
199} 199}
200 200
201int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 201static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
202 int *vpos, int *hpos) 202 int *vpos, int *hpos)
203{ 203{
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -264,7 +264,7 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
264 return ret; 264 return ret;
265} 265}
266 266
267int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 267static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
268 int *max_error, 268 int *max_error,
269 struct timeval *vblank_time, 269 struct timeval *vblank_time,
270 unsigned flags) 270 unsigned flags)
@@ -462,7 +462,7 @@ static void pch_irq_handler(struct drm_device *dev)
462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
463} 463}
464 464
465irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 465static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
466{ 466{
467 struct drm_device *dev = (struct drm_device *) arg; 467 struct drm_device *dev = (struct drm_device *) arg;
468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -550,7 +550,7 @@ done:
550 return ret; 550 return ret;
551} 551}
552 552
553irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) 553static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
554{ 554{
555 struct drm_device *dev = (struct drm_device *) arg; 555 struct drm_device *dev = (struct drm_device *) arg;
556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1209,7 +1209,7 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1209 } 1209 }
1210} 1210}
1211 1211
1212irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 1212static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1213{ 1213{
1214 struct drm_device *dev = (struct drm_device *) arg; 1214 struct drm_device *dev = (struct drm_device *) arg;
1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1454,7 +1454,7 @@ int i915_irq_wait(struct drm_device *dev, void *data,
1454/* Called from drm generic code, passed 'crtc' which 1454/* Called from drm generic code, passed 'crtc' which
1455 * we use as a pipe index 1455 * we use as a pipe index
1456 */ 1456 */
1457int i915_enable_vblank(struct drm_device *dev, int pipe) 1457static int i915_enable_vblank(struct drm_device *dev, int pipe)
1458{ 1458{
1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1460 unsigned long irqflags; 1460 unsigned long irqflags;
@@ -1478,7 +1478,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
1478 return 0; 1478 return 0;
1479} 1479}
1480 1480
1481int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1481static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1482{ 1482{
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 unsigned long irqflags; 1484 unsigned long irqflags;
@@ -1494,7 +1494,7 @@ int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1494 return 0; 1494 return 0;
1495} 1495}
1496 1496
1497int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1497static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1498{ 1498{
1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500 unsigned long irqflags; 1500 unsigned long irqflags;
@@ -1513,7 +1513,7 @@ int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1513/* Called from drm generic code, passed 'crtc' which 1513/* Called from drm generic code, passed 'crtc' which
1514 * we use as a pipe index 1514 * we use as a pipe index
1515 */ 1515 */
1516void i915_disable_vblank(struct drm_device *dev, int pipe) 1516static void i915_disable_vblank(struct drm_device *dev, int pipe)
1517{ 1517{
1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1519 unsigned long irqflags; 1519 unsigned long irqflags;
@@ -1529,7 +1529,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1530} 1530}
1531 1531
1532void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1532static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1533{ 1533{
1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1535 unsigned long irqflags; 1535 unsigned long irqflags;
@@ -1540,7 +1540,7 @@ void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1541} 1541}
1542 1542
1543void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1543static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1544{ 1544{
1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1546 unsigned long irqflags; 1546 unsigned long irqflags;
@@ -1728,7 +1728,7 @@ repeat:
1728 1728
1729/* drm_dma.h hooks 1729/* drm_dma.h hooks
1730*/ 1730*/
1731void ironlake_irq_preinstall(struct drm_device *dev) 1731static void ironlake_irq_preinstall(struct drm_device *dev)
1732{ 1732{
1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1734 1734
@@ -1740,6 +1740,17 @@ void ironlake_irq_preinstall(struct drm_device *dev)
1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1741 1741
1742 I915_WRITE(HWSTAM, 0xeffe); 1742 I915_WRITE(HWSTAM, 0xeffe);
1743 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1744 /* Workaround stalls observed on Sandy Bridge GPUs by
1745 * making the blitter command streamer generate a
1746 * write to the Hardware Status Page for
1747 * MI_USER_INTERRUPT. This appears to serialize the
1748 * previous seqno write out before the interrupt
1749 * happens.
1750 */
1751 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1752 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1753 }
1743 1754
1744 /* XXX hotplug from PCH */ 1755 /* XXX hotplug from PCH */
1745 1756
@@ -1758,7 +1769,7 @@ void ironlake_irq_preinstall(struct drm_device *dev)
1758 POSTING_READ(SDEIER); 1769 POSTING_READ(SDEIER);
1759} 1770}
1760 1771
1761int ironlake_irq_postinstall(struct drm_device *dev) 1772static int ironlake_irq_postinstall(struct drm_device *dev)
1762{ 1773{
1763 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1774 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1764 /* enable kind of interrupts always enabled */ 1775 /* enable kind of interrupts always enabled */
@@ -1830,7 +1841,7 @@ int ironlake_irq_postinstall(struct drm_device *dev)
1830 return 0; 1841 return 0;
1831} 1842}
1832 1843
1833int ivybridge_irq_postinstall(struct drm_device *dev) 1844static int ivybridge_irq_postinstall(struct drm_device *dev)
1834{ 1845{
1835 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1836 /* enable kind of interrupts always enabled */ 1847 /* enable kind of interrupts always enabled */
@@ -1880,7 +1891,7 @@ int ivybridge_irq_postinstall(struct drm_device *dev)
1880 return 0; 1891 return 0;
1881} 1892}
1882 1893
1883void i915_driver_irq_preinstall(struct drm_device * dev) 1894static void i915_driver_irq_preinstall(struct drm_device * dev)
1884{ 1895{
1885 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1896 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1886 int pipe; 1897 int pipe;
@@ -1907,7 +1918,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1907 * Must be called after intel_modeset_init or hotplug interrupts won't be 1918 * Must be called after intel_modeset_init or hotplug interrupts won't be
1908 * enabled correctly. 1919 * enabled correctly.
1909 */ 1920 */
1910int i915_driver_irq_postinstall(struct drm_device *dev) 1921static int i915_driver_irq_postinstall(struct drm_device *dev)
1911{ 1922{
1912 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1923 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1913 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 1924 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
@@ -1983,7 +1994,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1983 return 0; 1994 return 0;
1984} 1995}
1985 1996
1986void ironlake_irq_uninstall(struct drm_device *dev) 1997static void ironlake_irq_uninstall(struct drm_device *dev)
1987{ 1998{
1988 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1999 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1989 2000
@@ -2003,7 +2014,7 @@ void ironlake_irq_uninstall(struct drm_device *dev)
2003 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2014 I915_WRITE(GTIIR, I915_READ(GTIIR));
2004} 2015}
2005 2016
2006void i915_driver_irq_uninstall(struct drm_device * dev) 2017static void i915_driver_irq_uninstall(struct drm_device * dev)
2007{ 2018{
2008 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2009 int pipe; 2020 int pipe;
@@ -2029,3 +2040,41 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
2029 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2040 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2030 I915_WRITE(IIR, I915_READ(IIR)); 2041 I915_WRITE(IIR, I915_READ(IIR));
2031} 2042}
2043
2044void intel_irq_init(struct drm_device *dev)
2045{
2046 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2047 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2048 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2049 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2050 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2051 }
2052
2053
2054 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2055 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2056
2057 if (IS_IVYBRIDGE(dev)) {
2058 /* Share pre & uninstall handlers with ILK/SNB */
2059 dev->driver->irq_handler = ivybridge_irq_handler;
2060 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2061 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2062 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2063 dev->driver->enable_vblank = ivybridge_enable_vblank;
2064 dev->driver->disable_vblank = ivybridge_disable_vblank;
2065 } else if (HAS_PCH_SPLIT(dev)) {
2066 dev->driver->irq_handler = ironlake_irq_handler;
2067 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2068 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2069 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2070 dev->driver->enable_vblank = ironlake_enable_vblank;
2071 dev->driver->disable_vblank = ironlake_disable_vblank;
2072 } else {
2073 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2074 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2075 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2076 dev->driver->irq_handler = i915_driver_irq_handler;
2077 dev->driver->enable_vblank = i915_enable_vblank;
2078 dev->driver->disable_vblank = i915_disable_vblank;
2079 }
2080}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f967af8e62e..5d5def756c9e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -531,6 +531,7 @@
531#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 531#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
532#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 532#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
533 533
534#define GEN6_BSD_HWSTAM 0x12098
534#define GEN6_BSD_IMR 0x120a8 535#define GEN6_BSD_IMR 0x120a8
535#define GEN6_BSD_USER_INTERRUPT (1 << 12) 536#define GEN6_BSD_USER_INTERRUPT (1 << 12)
536 537
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 60a94d2b5264..5257cfc34c35 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -597,7 +597,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
597 return; 597 return;
598} 598}
599 599
600void i915_save_display(struct drm_device *dev) 600static void i915_save_display(struct drm_device *dev)
601{ 601{
602 struct drm_i915_private *dev_priv = dev->dev_private; 602 struct drm_i915_private *dev_priv = dev->dev_private;
603 603
@@ -689,7 +689,7 @@ void i915_save_display(struct drm_device *dev)
689 i915_save_vga(dev); 689 i915_save_vga(dev);
690} 690}
691 691
692void i915_restore_display(struct drm_device *dev) 692static void i915_restore_display(struct drm_device *dev)
693{ 693{
694 struct drm_i915_private *dev_priv = dev->dev_private; 694 struct drm_i915_private *dev_priv = dev->dev_private;
695 695
@@ -780,6 +780,7 @@ void i915_restore_display(struct drm_device *dev)
780 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 780 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
781 else 781 else
782 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 782 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
783
783 I915_WRITE(VGA0, dev_priv->saveVGA0); 784 I915_WRITE(VGA0, dev_priv->saveVGA0);
784 I915_WRITE(VGA1, dev_priv->saveVGA1); 785 I915_WRITE(VGA1, dev_priv->saveVGA1);
785 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 786 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
@@ -796,6 +797,8 @@ int i915_save_state(struct drm_device *dev)
796 797
797 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 798 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
798 799
800 mutex_lock(&dev->struct_mutex);
801
799 /* Hardware status page */ 802 /* Hardware status page */
800 dev_priv->saveHWS = I915_READ(HWS_PGA); 803 dev_priv->saveHWS = I915_READ(HWS_PGA);
801 804
@@ -835,6 +838,8 @@ int i915_save_state(struct drm_device *dev)
835 for (i = 0; i < 3; i++) 838 for (i = 0; i < 3; i++)
836 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 839 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
837 840
841 mutex_unlock(&dev->struct_mutex);
842
838 return 0; 843 return 0;
839} 844}
840 845
@@ -845,6 +850,8 @@ int i915_restore_state(struct drm_device *dev)
845 850
846 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 851 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
847 852
853 mutex_lock(&dev->struct_mutex);
854
848 /* Hardware status page */ 855 /* Hardware status page */
849 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 856 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
850 857
@@ -862,6 +869,7 @@ int i915_restore_state(struct drm_device *dev)
862 I915_WRITE(IER, dev_priv->saveIER); 869 I915_WRITE(IER, dev_priv->saveIER);
863 I915_WRITE(IMR, dev_priv->saveIMR); 870 I915_WRITE(IMR, dev_priv->saveIMR);
864 } 871 }
872 mutex_unlock(&dev->struct_mutex);
865 873
866 intel_init_clock_gating(dev); 874 intel_init_clock_gating(dev);
867 875
@@ -873,6 +881,8 @@ int i915_restore_state(struct drm_device *dev)
873 if (IS_GEN6(dev)) 881 if (IS_GEN6(dev))
874 gen6_enable_rps(dev_priv); 882 gen6_enable_rps(dev_priv);
875 883
884 mutex_lock(&dev->struct_mutex);
885
876 /* Cache mode state */ 886 /* Cache mode state */
877 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 887 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
878 888
@@ -886,6 +896,8 @@ int i915_restore_state(struct drm_device *dev)
886 for (i = 0; i < 3; i++) 896 for (i = 0; i < 3; i++)
887 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 897 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
888 898
899 mutex_unlock(&dev->struct_mutex);
900
889 intel_i2c_reset(dev); 901 intel_i2c_reset(dev);
890 902
891 return 0; 903 return 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 81a9059b6a94..21b6f93fe919 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4687,6 +4687,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4687 4687
4688 I915_WRITE(DSPCNTR(plane), dspcntr); 4688 I915_WRITE(DSPCNTR(plane), dspcntr);
4689 POSTING_READ(DSPCNTR(plane)); 4689 POSTING_READ(DSPCNTR(plane));
4690 intel_enable_plane(dev_priv, plane, pipe);
4690 4691
4691 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4692 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4692 4693
@@ -5217,8 +5218,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5217 5218
5218 I915_WRITE(DSPCNTR(plane), dspcntr); 5219 I915_WRITE(DSPCNTR(plane), dspcntr);
5219 POSTING_READ(DSPCNTR(plane)); 5220 POSTING_READ(DSPCNTR(plane));
5220 if (!HAS_PCH_SPLIT(dev))
5221 intel_enable_plane(dev_priv, plane, pipe);
5222 5221
5223 ret = intel_pipe_set_base(crtc, x, y, old_fb); 5222 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5224 5223
@@ -6262,6 +6261,197 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
6262 spin_unlock_irqrestore(&dev->event_lock, flags); 6261 spin_unlock_irqrestore(&dev->event_lock, flags);
6263} 6262}
6264 6263
6264static int intel_gen2_queue_flip(struct drm_device *dev,
6265 struct drm_crtc *crtc,
6266 struct drm_framebuffer *fb,
6267 struct drm_i915_gem_object *obj)
6268{
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6271 unsigned long offset;
6272 u32 flip_mask;
6273 int ret;
6274
6275 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6276 if (ret)
6277 goto out;
6278
6279 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6280 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6281
6282 ret = BEGIN_LP_RING(6);
6283 if (ret)
6284 goto out;
6285
6286 /* Can't queue multiple flips, so wait for the previous
6287 * one to finish before executing the next.
6288 */
6289 if (intel_crtc->plane)
6290 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6291 else
6292 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6293 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6294 OUT_RING(MI_NOOP);
6295 OUT_RING(MI_DISPLAY_FLIP |
6296 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6297 OUT_RING(fb->pitch);
6298 OUT_RING(obj->gtt_offset + offset);
6299 OUT_RING(MI_NOOP);
6300 ADVANCE_LP_RING();
6301out:
6302 return ret;
6303}
6304
6305static int intel_gen3_queue_flip(struct drm_device *dev,
6306 struct drm_crtc *crtc,
6307 struct drm_framebuffer *fb,
6308 struct drm_i915_gem_object *obj)
6309{
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 unsigned long offset;
6313 u32 flip_mask;
6314 int ret;
6315
6316 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6317 if (ret)
6318 goto out;
6319
6320 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6321 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6322
6323 ret = BEGIN_LP_RING(6);
6324 if (ret)
6325 goto out;
6326
6327 if (intel_crtc->plane)
6328 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6329 else
6330 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6331 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6332 OUT_RING(MI_NOOP);
6333 OUT_RING(MI_DISPLAY_FLIP_I915 |
6334 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6335 OUT_RING(fb->pitch);
6336 OUT_RING(obj->gtt_offset + offset);
6337 OUT_RING(MI_NOOP);
6338
6339 ADVANCE_LP_RING();
6340out:
6341 return ret;
6342}
6343
6344static int intel_gen4_queue_flip(struct drm_device *dev,
6345 struct drm_crtc *crtc,
6346 struct drm_framebuffer *fb,
6347 struct drm_i915_gem_object *obj)
6348{
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6351 uint32_t pf, pipesrc;
6352 int ret;
6353
6354 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6355 if (ret)
6356 goto out;
6357
6358 ret = BEGIN_LP_RING(4);
6359 if (ret)
6360 goto out;
6361
6362 /* i965+ uses the linear or tiled offsets from the
6363 * Display Registers (which do not change across a page-flip)
6364 * so we need only reprogram the base address.
6365 */
6366 OUT_RING(MI_DISPLAY_FLIP |
6367 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6368 OUT_RING(fb->pitch);
6369 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6370
6371 /* XXX Enabling the panel-fitter across page-flip is so far
6372 * untested on non-native modes, so ignore it for now.
6373 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6374 */
6375 pf = 0;
6376 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6377 OUT_RING(pf | pipesrc);
6378 ADVANCE_LP_RING();
6379out:
6380 return ret;
6381}
6382
6383static int intel_gen6_queue_flip(struct drm_device *dev,
6384 struct drm_crtc *crtc,
6385 struct drm_framebuffer *fb,
6386 struct drm_i915_gem_object *obj)
6387{
6388 struct drm_i915_private *dev_priv = dev->dev_private;
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 uint32_t pf, pipesrc;
6391 int ret;
6392
6393 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6394 if (ret)
6395 goto out;
6396
6397 ret = BEGIN_LP_RING(4);
6398 if (ret)
6399 goto out;
6400
6401 OUT_RING(MI_DISPLAY_FLIP |
6402 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6403 OUT_RING(fb->pitch | obj->tiling_mode);
6404 OUT_RING(obj->gtt_offset);
6405
6406 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6407 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6408 OUT_RING(pf | pipesrc);
6409 ADVANCE_LP_RING();
6410out:
6411 return ret;
6412}
6413
6414/*
6415 * On gen7 we currently use the blit ring because (in early silicon at least)
6416 * the render ring doesn't give us interrpts for page flip completion, which
6417 * means clients will hang after the first flip is queued. Fortunately the
6418 * blit ring generates interrupts properly, so use it instead.
6419 */
6420static int intel_gen7_queue_flip(struct drm_device *dev,
6421 struct drm_crtc *crtc,
6422 struct drm_framebuffer *fb,
6423 struct drm_i915_gem_object *obj)
6424{
6425 struct drm_i915_private *dev_priv = dev->dev_private;
6426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6427 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6428 int ret;
6429
6430 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6431 if (ret)
6432 goto out;
6433
6434 ret = intel_ring_begin(ring, 4);
6435 if (ret)
6436 goto out;
6437
6438 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6439 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6440 intel_ring_emit(ring, (obj->gtt_offset));
6441 intel_ring_emit(ring, (MI_NOOP));
6442 intel_ring_advance(ring);
6443out:
6444 return ret;
6445}
6446
6447static int intel_default_queue_flip(struct drm_device *dev,
6448 struct drm_crtc *crtc,
6449 struct drm_framebuffer *fb,
6450 struct drm_i915_gem_object *obj)
6451{
6452 return -ENODEV;
6453}
6454
6265static int intel_crtc_page_flip(struct drm_crtc *crtc, 6455static int intel_crtc_page_flip(struct drm_crtc *crtc,
6266 struct drm_framebuffer *fb, 6456 struct drm_framebuffer *fb,
6267 struct drm_pending_vblank_event *event) 6457 struct drm_pending_vblank_event *event)
@@ -6272,9 +6462,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6272 struct drm_i915_gem_object *obj; 6462 struct drm_i915_gem_object *obj;
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6274 struct intel_unpin_work *work; 6464 struct intel_unpin_work *work;
6275 unsigned long flags, offset; 6465 unsigned long flags;
6276 int pipe = intel_crtc->pipe;
6277 u32 pf, pipesrc;
6278 int ret; 6466 int ret;
6279 6467
6280 work = kzalloc(sizeof *work, GFP_KERNEL); 6468 work = kzalloc(sizeof *work, GFP_KERNEL);
@@ -6303,9 +6491,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6303 obj = intel_fb->obj; 6491 obj = intel_fb->obj;
6304 6492
6305 mutex_lock(&dev->struct_mutex); 6493 mutex_lock(&dev->struct_mutex);
6306 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6307 if (ret)
6308 goto cleanup_work;
6309 6494
6310 /* Reference the objects for the scheduled work. */ 6495 /* Reference the objects for the scheduled work. */
6311 drm_gem_object_reference(&work->old_fb_obj->base); 6496 drm_gem_object_reference(&work->old_fb_obj->base);
@@ -6317,91 +6502,18 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6317 if (ret) 6502 if (ret)
6318 goto cleanup_objs; 6503 goto cleanup_objs;
6319 6504
6320 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6321 u32 flip_mask;
6322
6323 /* Can't queue multiple flips, so wait for the previous
6324 * one to finish before executing the next.
6325 */
6326 ret = BEGIN_LP_RING(2);
6327 if (ret)
6328 goto cleanup_objs;
6329
6330 if (intel_crtc->plane)
6331 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6332 else
6333 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6334 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6335 OUT_RING(MI_NOOP);
6336 ADVANCE_LP_RING();
6337 }
6338
6339 work->pending_flip_obj = obj; 6505 work->pending_flip_obj = obj;
6340 6506
6341 work->enable_stall_check = true; 6507 work->enable_stall_check = true;
6342 6508
6343 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6344 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6345
6346 ret = BEGIN_LP_RING(4);
6347 if (ret)
6348 goto cleanup_objs;
6349
6350 /* Block clients from rendering to the new back buffer until 6509 /* Block clients from rendering to the new back buffer until
6351 * the flip occurs and the object is no longer visible. 6510 * the flip occurs and the object is no longer visible.
6352 */ 6511 */
6353 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 6512 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6354 6513
6355 switch (INTEL_INFO(dev)->gen) { 6514 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6356 case 2: 6515 if (ret)
6357 OUT_RING(MI_DISPLAY_FLIP | 6516 goto cleanup_pending;
6358 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6359 OUT_RING(fb->pitch);
6360 OUT_RING(obj->gtt_offset + offset);
6361 OUT_RING(MI_NOOP);
6362 break;
6363
6364 case 3:
6365 OUT_RING(MI_DISPLAY_FLIP_I915 |
6366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6367 OUT_RING(fb->pitch);
6368 OUT_RING(obj->gtt_offset + offset);
6369 OUT_RING(MI_NOOP);
6370 break;
6371
6372 case 4:
6373 case 5:
6374 /* i965+ uses the linear or tiled offsets from the
6375 * Display Registers (which do not change across a page-flip)
6376 * so we need only reprogram the base address.
6377 */
6378 OUT_RING(MI_DISPLAY_FLIP |
6379 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6380 OUT_RING(fb->pitch);
6381 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6382
6383 /* XXX Enabling the panel-fitter across page-flip is so far
6384 * untested on non-native modes, so ignore it for now.
6385 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6386 */
6387 pf = 0;
6388 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6389 OUT_RING(pf | pipesrc);
6390 break;
6391
6392 case 6:
6393 case 7:
6394 OUT_RING(MI_DISPLAY_FLIP |
6395 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6396 OUT_RING(fb->pitch | obj->tiling_mode);
6397 OUT_RING(obj->gtt_offset);
6398
6399 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6400 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6401 OUT_RING(pf | pipesrc);
6402 break;
6403 }
6404 ADVANCE_LP_RING();
6405 6517
6406 mutex_unlock(&dev->struct_mutex); 6518 mutex_unlock(&dev->struct_mutex);
6407 6519
@@ -6409,10 +6521,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6409 6521
6410 return 0; 6522 return 0;
6411 6523
6524cleanup_pending:
6525 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6412cleanup_objs: 6526cleanup_objs:
6413 drm_gem_object_unreference(&work->old_fb_obj->base); 6527 drm_gem_object_unreference(&work->old_fb_obj->base);
6414 drm_gem_object_unreference(&obj->base); 6528 drm_gem_object_unreference(&obj->base);
6415cleanup_work:
6416 mutex_unlock(&dev->struct_mutex); 6529 mutex_unlock(&dev->struct_mutex);
6417 6530
6418 spin_lock_irqsave(&dev->event_lock, flags); 6531 spin_lock_irqsave(&dev->event_lock, flags);
@@ -7657,6 +7770,31 @@ static void intel_init_display(struct drm_device *dev)
7657 else 7770 else
7658 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7771 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7659 } 7772 }
7773
7774 /* Default just returns -ENODEV to indicate unsupported */
7775 dev_priv->display.queue_flip = intel_default_queue_flip;
7776
7777 switch (INTEL_INFO(dev)->gen) {
7778 case 2:
7779 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7780 break;
7781
7782 case 3:
7783 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7784 break;
7785
7786 case 4:
7787 case 5:
7788 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7789 break;
7790
7791 case 6:
7792 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7793 break;
7794 case 7:
7795 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7796 break;
7797 }
7660} 7798}
7661 7799
7662/* 7800/*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 391b55f1cc74..e2aced6eec4c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -50,7 +50,6 @@ struct intel_dp {
50 bool has_audio; 50 bool has_audio;
51 int force_audio; 51 int force_audio;
52 uint32_t color_range; 52 uint32_t color_range;
53 int dpms_mode;
54 uint8_t link_bw; 53 uint8_t link_bw;
55 uint8_t lane_count; 54 uint8_t lane_count;
56 uint8_t dpcd[4]; 55 uint8_t dpcd[4];
@@ -138,8 +137,8 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
138{ 137{
139 int max_lane_count = 4; 138 int max_lane_count = 4;
140 139
141 if (intel_dp->dpcd[0] >= 0x11) { 140 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
142 max_lane_count = intel_dp->dpcd[2] & 0x1f; 141 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) { 142 switch (max_lane_count) {
144 case 1: case 2: case 4: 143 case 1: case 2: case 4:
145 break; 144 break;
@@ -153,7 +152,7 @@ intel_dp_max_lane_count(struct intel_dp *intel_dp)
153static int 152static int
154intel_dp_max_link_bw(struct intel_dp *intel_dp) 153intel_dp_max_link_bw(struct intel_dp *intel_dp)
155{ 154{
156 int max_link_bw = intel_dp->dpcd[1]; 155 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
157 156
158 switch (max_link_bw) { 157 switch (max_link_bw) {
159 case DP_LINK_BW_1_62: 158 case DP_LINK_BW_1_62:
@@ -774,7 +773,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
774 /* 773 /*
775 * Check for DPCD version > 1.1 and enhanced framing support 774 * Check for DPCD version > 1.1 and enhanced framing support
776 */ 775 */
777 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 776 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
777 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
779 intel_dp->DP |= DP_ENHANCED_FRAMING; 779 intel_dp->DP |= DP_ENHANCED_FRAMING;
780 } 780 }
@@ -942,11 +942,44 @@ static void ironlake_edp_pll_off(struct drm_encoder *encoder)
942 udelay(200); 942 udelay(200);
943} 943}
944 944
945/* If the sink supports it, try to set the power state appropriately */
946static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
947{
948 int ret, i;
949
950 /* Should have a valid DPCD by this point */
951 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
952 return;
953
954 if (mode != DRM_MODE_DPMS_ON) {
955 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
956 DP_SET_POWER_D3);
957 if (ret != 1)
958 DRM_DEBUG_DRIVER("failed to write sink power state\n");
959 } else {
960 /*
961 * When turning on, we need to retry for 1ms to give the sink
962 * time to wake up.
963 */
964 for (i = 0; i < 3; i++) {
965 ret = intel_dp_aux_native_write_1(intel_dp,
966 DP_SET_POWER,
967 DP_SET_POWER_D0);
968 if (ret == 1)
969 break;
970 msleep(1);
971 }
972 }
973}
974
945static void intel_dp_prepare(struct drm_encoder *encoder) 975static void intel_dp_prepare(struct drm_encoder *encoder)
946{ 976{
947 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 977 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
948 struct drm_device *dev = encoder->dev; 978 struct drm_device *dev = encoder->dev;
949 979
980 /* Wake up the sink first */
981 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
982
950 if (is_edp(intel_dp)) { 983 if (is_edp(intel_dp)) {
951 ironlake_edp_backlight_off(dev); 984 ironlake_edp_backlight_off(dev);
952 ironlake_edp_panel_off(dev); 985 ironlake_edp_panel_off(dev);
@@ -990,6 +1023,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
990 if (mode != DRM_MODE_DPMS_ON) { 1023 if (mode != DRM_MODE_DPMS_ON) {
991 if (is_edp(intel_dp)) 1024 if (is_edp(intel_dp))
992 ironlake_edp_backlight_off(dev); 1025 ironlake_edp_backlight_off(dev);
1026 intel_dp_sink_dpms(intel_dp, mode);
993 intel_dp_link_down(intel_dp); 1027 intel_dp_link_down(intel_dp);
994 if (is_edp(intel_dp)) 1028 if (is_edp(intel_dp))
995 ironlake_edp_panel_off(dev); 1029 ironlake_edp_panel_off(dev);
@@ -998,6 +1032,7 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
998 } else { 1032 } else {
999 if (is_edp(intel_dp)) 1033 if (is_edp(intel_dp))
1000 ironlake_edp_panel_vdd_on(intel_dp); 1034 ironlake_edp_panel_vdd_on(intel_dp);
1035 intel_dp_sink_dpms(intel_dp, mode);
1001 if (!(dp_reg & DP_PORT_EN)) { 1036 if (!(dp_reg & DP_PORT_EN)) {
1002 intel_dp_start_link_train(intel_dp); 1037 intel_dp_start_link_train(intel_dp);
1003 if (is_edp(intel_dp)) { 1038 if (is_edp(intel_dp)) {
@@ -1009,7 +1044,31 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
1009 if (is_edp(intel_dp)) 1044 if (is_edp(intel_dp))
1010 ironlake_edp_backlight_on(dev); 1045 ironlake_edp_backlight_on(dev);
1011 } 1046 }
1012 intel_dp->dpms_mode = mode; 1047}
1048
1049/*
1050 * Native read with retry for link status and receiver capability reads for
1051 * cases where the sink may still be asleep.
1052 */
1053static bool
1054intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1055 uint8_t *recv, int recv_bytes)
1056{
1057 int ret, i;
1058
1059 /*
1060 * Sinks are *supposed* to come up within 1ms from an off state,
1061 * but we're also supposed to retry 3 times per the spec.
1062 */
1063 for (i = 0; i < 3; i++) {
1064 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1065 recv_bytes);
1066 if (ret == recv_bytes)
1067 return true;
1068 msleep(1);
1069 }
1070
1071 return false;
1013} 1072}
1014 1073
1015/* 1074/*
@@ -1019,14 +1078,10 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
1019static bool 1078static bool
1020intel_dp_get_link_status(struct intel_dp *intel_dp) 1079intel_dp_get_link_status(struct intel_dp *intel_dp)
1021{ 1080{
1022 int ret; 1081 return intel_dp_aux_native_read_retry(intel_dp,
1023 1082 DP_LANE0_1_STATUS,
1024 ret = intel_dp_aux_native_read(intel_dp, 1083 intel_dp->link_status,
1025 DP_LANE0_1_STATUS, 1084 DP_LINK_STATUS_SIZE);
1026 intel_dp->link_status, DP_LINK_STATUS_SIZE);
1027 if (ret != DP_LINK_STATUS_SIZE)
1028 return false;
1029 return true;
1030} 1085}
1031 1086
1032static uint8_t 1087static uint8_t
@@ -1515,6 +1570,8 @@ intel_dp_link_down(struct intel_dp *intel_dp)
1515static void 1570static void
1516intel_dp_check_link_status(struct intel_dp *intel_dp) 1571intel_dp_check_link_status(struct intel_dp *intel_dp)
1517{ 1572{
1573 int ret;
1574
1518 if (!intel_dp->base.base.crtc) 1575 if (!intel_dp->base.base.crtc)
1519 return; 1576 return;
1520 1577
@@ -1523,6 +1580,15 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
1523 return; 1580 return;
1524 } 1581 }
1525 1582
1583 /* Try to read receiver status if the link appears to be up */
1584 ret = intel_dp_aux_native_read(intel_dp,
1585 0x000, intel_dp->dpcd,
1586 sizeof (intel_dp->dpcd));
1587 if (ret != sizeof(intel_dp->dpcd)) {
1588 intel_dp_link_down(intel_dp);
1589 return;
1590 }
1591
1526 if (!intel_channel_eq_ok(intel_dp)) { 1592 if (!intel_channel_eq_ok(intel_dp)) {
1527 intel_dp_start_link_train(intel_dp); 1593 intel_dp_start_link_train(intel_dp);
1528 intel_dp_complete_link_train(intel_dp); 1594 intel_dp_complete_link_train(intel_dp);
@@ -1533,6 +1599,7 @@ static enum drm_connector_status
1533ironlake_dp_detect(struct intel_dp *intel_dp) 1599ironlake_dp_detect(struct intel_dp *intel_dp)
1534{ 1600{
1535 enum drm_connector_status status; 1601 enum drm_connector_status status;
1602 bool ret;
1536 1603
1537 /* Can't disconnect eDP, but you can close the lid... */ 1604 /* Can't disconnect eDP, but you can close the lid... */
1538 if (is_edp(intel_dp)) { 1605 if (is_edp(intel_dp)) {
@@ -1543,13 +1610,11 @@ ironlake_dp_detect(struct intel_dp *intel_dp)
1543 } 1610 }
1544 1611
1545 status = connector_status_disconnected; 1612 status = connector_status_disconnected;
1546 if (intel_dp_aux_native_read(intel_dp, 1613 ret = intel_dp_aux_native_read_retry(intel_dp,
1547 0x000, intel_dp->dpcd, 1614 0x000, intel_dp->dpcd,
1548 sizeof (intel_dp->dpcd)) 1615 sizeof (intel_dp->dpcd));
1549 == sizeof(intel_dp->dpcd)) { 1616 if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
1550 if (intel_dp->dpcd[0] != 0) 1617 status = connector_status_connected;
1551 status = connector_status_connected;
1552 }
1553 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1618 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1554 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1619 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1555 return status; 1620 return status;
@@ -1586,7 +1651,7 @@ g4x_dp_detect(struct intel_dp *intel_dp)
1586 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, 1651 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1587 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1652 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1588 { 1653 {
1589 if (intel_dp->dpcd[0] != 0) 1654 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1590 status = connector_status_connected; 1655 status = connector_status_connected;
1591 } 1656 }
1592 1657
@@ -1790,8 +1855,7 @@ intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1790{ 1855{
1791 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1856 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1792 1857
1793 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1858 intel_dp_check_link_status(intel_dp);
1794 intel_dp_check_link_status(intel_dp);
1795} 1859}
1796 1860
1797/* Return which DP Port should be selected for Transcoder DP control */ 1861/* Return which DP Port should be selected for Transcoder DP control */
@@ -1859,7 +1923,6 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1859 return; 1923 return;
1860 1924
1861 intel_dp->output_reg = output_reg; 1925 intel_dp->output_reg = output_reg;
1862 intel_dp->dpms_mode = -1;
1863 1926
1864 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1927 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1865 if (!intel_connector) { 1928 if (!intel_connector) {
@@ -1954,8 +2017,9 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1954 sizeof(intel_dp->dpcd)); 2017 sizeof(intel_dp->dpcd));
1955 ironlake_edp_panel_vdd_off(intel_dp); 2018 ironlake_edp_panel_vdd_off(intel_dp);
1956 if (ret == sizeof(intel_dp->dpcd)) { 2019 if (ret == sizeof(intel_dp->dpcd)) {
1957 if (intel_dp->dpcd[0] >= 0x11) 2020 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
1958 dev_priv->no_aux_handshake = intel_dp->dpcd[3] & 2021 dev_priv->no_aux_handshake =
2022 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
1959 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2023 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1960 } else { 2024 } else {
1961 /* if this fails, presume the device is a ghost */ 2025 /* if this fails, presume the device is a ghost */
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index a670c006982e..9e2959bc91cd 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1409,6 +1409,11 @@ void intel_setup_overlay(struct drm_device *dev)
1409 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL); 1409 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1410 if (!overlay) 1410 if (!overlay)
1411 return; 1411 return;
1412
1413 mutex_lock(&dev->struct_mutex);
1414 if (WARN_ON(dev_priv->overlay))
1415 goto out_free;
1416
1412 overlay->dev = dev; 1417 overlay->dev = dev;
1413 1418
1414 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE); 1419 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
@@ -1448,7 +1453,7 @@ void intel_setup_overlay(struct drm_device *dev)
1448 1453
1449 regs = intel_overlay_map_regs(overlay); 1454 regs = intel_overlay_map_regs(overlay);
1450 if (!regs) 1455 if (!regs)
1451 goto out_free_bo; 1456 goto out_unpin_bo;
1452 1457
1453 memset(regs, 0, sizeof(struct overlay_registers)); 1458 memset(regs, 0, sizeof(struct overlay_registers));
1454 update_polyphase_filter(regs); 1459 update_polyphase_filter(regs);
@@ -1457,14 +1462,17 @@ void intel_setup_overlay(struct drm_device *dev)
1457 intel_overlay_unmap_regs(overlay, regs); 1462 intel_overlay_unmap_regs(overlay, regs);
1458 1463
1459 dev_priv->overlay = overlay; 1464 dev_priv->overlay = overlay;
1465 mutex_unlock(&dev->struct_mutex);
1460 DRM_INFO("initialized overlay support\n"); 1466 DRM_INFO("initialized overlay support\n");
1461 return; 1467 return;
1462 1468
1463out_unpin_bo: 1469out_unpin_bo:
1464 i915_gem_object_unpin(reg_bo); 1470 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1471 i915_gem_object_unpin(reg_bo);
1465out_free_bo: 1472out_free_bo:
1466 drm_gem_object_unreference(&reg_bo->base); 1473 drm_gem_object_unreference(&reg_bo->base);
1467out_free: 1474out_free:
1475 mutex_unlock(&dev->struct_mutex);
1468 kfree(overlay); 1476 kfree(overlay);
1469 return; 1477 return;
1470} 1478}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c0e0ee63fbf4..39ac2b634ae5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -165,7 +165,7 @@ void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
165int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 165int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
166static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) 166static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
167{ 167{
168 return intel_wait_ring_buffer(ring, ring->space - 8); 168 return intel_wait_ring_buffer(ring, ring->size - 8);
169} 169}
170 170
171int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 171int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index f0d459bb46e4..525744d593c1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -262,7 +262,6 @@ static bool nouveau_dsm_detect(void)
262 vga_count++; 262 vga_count++;
263 263
264 retval = nouveau_dsm_pci_probe(pdev); 264 retval = nouveau_dsm_pci_probe(pdev);
265 printk("ret val is %d\n", retval);
266 if (retval & NOUVEAU_DSM_HAS_MUX) 265 if (retval & NOUVEAU_DSM_HAS_MUX)
267 has_dsm |= 1; 266 has_dsm |= 1;
268 if (retval & NOUVEAU_DSM_HAS_OPT) 267 if (retval & NOUVEAU_DSM_HAS_OPT)
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 4b9f4493c9f9..7347075ca5b8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -339,11 +339,12 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
339 int ret; 339 int ret;
340 340
341 if (dev_priv->chipset < 0x84) { 341 if (dev_priv->chipset < 0x84) {
342 ret = RING_SPACE(chan, 3); 342 ret = RING_SPACE(chan, 4);
343 if (ret) 343 if (ret)
344 return ret; 344 return ret;
345 345
346 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 2); 346 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 3);
347 OUT_RING (chan, NvSema);
347 OUT_RING (chan, sema->mem->start); 348 OUT_RING (chan, sema->mem->start);
348 OUT_RING (chan, 1); 349 OUT_RING (chan, 1);
349 } else 350 } else
@@ -351,10 +352,12 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
351 struct nouveau_vma *vma = &dev_priv->fence.bo->vma; 352 struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
352 u64 offset = vma->offset + sema->mem->start; 353 u64 offset = vma->offset + sema->mem->start;
353 354
354 ret = RING_SPACE(chan, 5); 355 ret = RING_SPACE(chan, 7);
355 if (ret) 356 if (ret)
356 return ret; 357 return ret;
357 358
359 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
360 OUT_RING (chan, chan->vram_handle);
358 BEGIN_RING(chan, NvSubSw, 0x0010, 4); 361 BEGIN_RING(chan, NvSubSw, 0x0010, 4);
359 OUT_RING (chan, upper_32_bits(offset)); 362 OUT_RING (chan, upper_32_bits(offset));
360 OUT_RING (chan, lower_32_bits(offset)); 363 OUT_RING (chan, lower_32_bits(offset));
@@ -394,11 +397,12 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
394 int ret; 397 int ret;
395 398
396 if (dev_priv->chipset < 0x84) { 399 if (dev_priv->chipset < 0x84) {
397 ret = RING_SPACE(chan, 4); 400 ret = RING_SPACE(chan, 5);
398 if (ret) 401 if (ret)
399 return ret; 402 return ret;
400 403
401 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_OFFSET, 1); 404 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 2);
405 OUT_RING (chan, NvSema);
402 OUT_RING (chan, sema->mem->start); 406 OUT_RING (chan, sema->mem->start);
403 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1); 407 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1);
404 OUT_RING (chan, 1); 408 OUT_RING (chan, 1);
@@ -407,10 +411,12 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
407 struct nouveau_vma *vma = &dev_priv->fence.bo->vma; 411 struct nouveau_vma *vma = &dev_priv->fence.bo->vma;
408 u64 offset = vma->offset + sema->mem->start; 412 u64 offset = vma->offset + sema->mem->start;
409 413
410 ret = RING_SPACE(chan, 5); 414 ret = RING_SPACE(chan, 7);
411 if (ret) 415 if (ret)
412 return ret; 416 return ret;
413 417
418 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
419 OUT_RING (chan, chan->vram_handle);
414 BEGIN_RING(chan, NvSubSw, 0x0010, 4); 420 BEGIN_RING(chan, NvSubSw, 0x0010, 4);
415 OUT_RING (chan, upper_32_bits(offset)); 421 OUT_RING (chan, upper_32_bits(offset));
416 OUT_RING (chan, lower_32_bits(offset)); 422 OUT_RING (chan, lower_32_bits(offset));
@@ -504,22 +510,22 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
504 struct nouveau_gpuobj *obj = NULL; 510 struct nouveau_gpuobj *obj = NULL;
505 int ret; 511 int ret;
506 512
507 if (dev_priv->card_type >= NV_C0) 513 if (dev_priv->card_type < NV_C0) {
508 goto out_initialised; 514 /* Create an NV_SW object for various sync purposes */
515 ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
516 if (ret)
517 return ret;
509 518
510 /* Create an NV_SW object for various sync purposes */ 519 ret = RING_SPACE(chan, 2);
511 ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW); 520 if (ret)
512 if (ret) 521 return ret;
513 return ret;
514 522
515 /* we leave subchannel empty for nvc0 */ 523 BEGIN_RING(chan, NvSubSw, 0, 1);
516 ret = RING_SPACE(chan, 2); 524 OUT_RING (chan, NvSw);
517 if (ret) 525 FIRE_RING (chan);
518 return ret; 526 }
519 BEGIN_RING(chan, NvSubSw, 0, 1);
520 OUT_RING(chan, NvSw);
521 527
522 /* Create a DMA object for the shared cross-channel sync area. */ 528 /* Setup area of memory shared between all channels for x-chan sync */
523 if (USE_SEMA(dev) && dev_priv->chipset < 0x84) { 529 if (USE_SEMA(dev) && dev_priv->chipset < 0x84) {
524 struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem; 530 struct ttm_mem_reg *mem = &dev_priv->fence.bo->bo.mem;
525 531
@@ -534,23 +540,8 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
534 nouveau_gpuobj_ref(NULL, &obj); 540 nouveau_gpuobj_ref(NULL, &obj);
535 if (ret) 541 if (ret)
536 return ret; 542 return ret;
537
538 ret = RING_SPACE(chan, 2);
539 if (ret)
540 return ret;
541 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
542 OUT_RING(chan, NvSema);
543 } else {
544 ret = RING_SPACE(chan, 2);
545 if (ret)
546 return ret;
547 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
548 OUT_RING (chan, chan->vram_handle); /* whole VM */
549 } 543 }
550 544
551 FIRE_RING(chan);
552
553out_initialised:
554 INIT_LIST_HEAD(&chan->fence.pending); 545 INIT_LIST_HEAD(&chan->fence.pending);
555 spin_lock_init(&chan->fence.lock); 546 spin_lock_init(&chan->fence.lock);
556 atomic_set(&chan->fence.last_sequence_irq, 0); 547 atomic_set(&chan->fence.last_sequence_irq, 0);
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index 922fb6b664ed..ef9dec0e6f8b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -182,6 +182,11 @@ nouveau_perf_init(struct drm_device *dev)
182 entries = perf[2]; 182 entries = perf[2];
183 } 183 }
184 184
185 if (entries > NOUVEAU_PM_MAX_LEVEL) {
186 NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n");
187 entries = NOUVEAU_PM_MAX_LEVEL;
188 }
189
185 entry = perf + headerlen; 190 entry = perf + headerlen;
186 for (i = 0; i < entries; i++) { 191 for (i = 0; i < entries; i++) {
187 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl]; 192 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 80218887e0a0..731acea865b5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -371,7 +371,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
371 engine->vram.flags_valid = nv50_vram_flags_valid; 371 engine->vram.flags_valid = nv50_vram_flags_valid;
372 break; 372 break;
373 case 0xC0: 373 case 0xC0:
374 case 0xD0:
375 engine->instmem.init = nvc0_instmem_init; 374 engine->instmem.init = nvc0_instmem_init;
376 engine->instmem.takedown = nvc0_instmem_takedown; 375 engine->instmem.takedown = nvc0_instmem_takedown;
377 engine->instmem.suspend = nvc0_instmem_suspend; 376 engine->instmem.suspend = nvc0_instmem_suspend;
@@ -881,8 +880,8 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
881 880
882#ifdef __BIG_ENDIAN 881#ifdef __BIG_ENDIAN
883 /* Put the card in BE mode if it's not */ 882 /* Put the card in BE mode if it's not */
884 if (nv_rd32(dev, NV03_PMC_BOOT_1)) 883 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
885 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001); 884 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
886 885
887 DRM_MEMORYBARRIER(); 886 DRM_MEMORYBARRIER();
888#endif 887#endif
@@ -923,7 +922,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
923 dev_priv->card_type = NV_50; 922 dev_priv->card_type = NV_50;
924 break; 923 break;
925 case 0xc0: 924 case 0xc0:
926 case 0xd0:
927 dev_priv->card_type = NV_C0; 925 dev_priv->card_type = NV_C0;
928 break; 926 break;
929 default: 927 default:
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 74a3f6872701..08da478ba544 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -409,7 +409,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
409 struct nouveau_channel *evo = dispc->sync; 409 struct nouveau_channel *evo = dispc->sync;
410 int ret; 410 int ret;
411 411
412 ret = RING_SPACE(evo, 24); 412 ret = RING_SPACE(evo, chan ? 25 : 27);
413 if (unlikely(ret)) 413 if (unlikely(ret))
414 return ret; 414 return ret;
415 415
@@ -458,8 +458,19 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
458 /* queue the flip on the crtc's "display sync" channel */ 458 /* queue the flip on the crtc's "display sync" channel */
459 BEGIN_RING(evo, 0, 0x0100, 1); 459 BEGIN_RING(evo, 0, 0x0100, 1);
460 OUT_RING (evo, 0xfffe0000); 460 OUT_RING (evo, 0xfffe0000);
461 BEGIN_RING(evo, 0, 0x0084, 5); 461 if (chan) {
462 OUT_RING (evo, chan ? 0x00000100 : 0x00000010); 462 BEGIN_RING(evo, 0, 0x0084, 1);
463 OUT_RING (evo, 0x00000100);
464 } else {
465 BEGIN_RING(evo, 0, 0x0084, 1);
466 OUT_RING (evo, 0x00000010);
467 /* allows gamma somehow, PDISP will bitch at you if
468 * you don't wait for vblank before changing this..
469 */
470 BEGIN_RING(evo, 0, 0x00e0, 1);
471 OUT_RING (evo, 0x40000000);
472 }
473 BEGIN_RING(evo, 0, 0x0088, 4);
463 OUT_RING (evo, dispc->sem.offset); 474 OUT_RING (evo, dispc->sem.offset);
464 OUT_RING (evo, 0xf00d0000 | dispc->sem.value); 475 OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
465 OUT_RING (evo, 0x74b1e000); 476 OUT_RING (evo, 0x74b1e000);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 7e3d96e7ac04..15bd0477a3e8 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -140,11 +140,17 @@ void evergreen_pm_misc(struct radeon_device *rdev)
140 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 140 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
141 141
142 if (voltage->type == VOLTAGE_SW) { 142 if (voltage->type == VOLTAGE_SW) {
143 /* 0xff01 is a flag rather then an actual voltage */
144 if (voltage->voltage == 0xff01)
145 return;
143 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { 146 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
144 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 147 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
145 rdev->pm.current_vddc = voltage->voltage; 148 rdev->pm.current_vddc = voltage->voltage;
146 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); 149 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
147 } 150 }
151 /* 0xff01 is a flag rather then an actual voltage */
152 if (voltage->vddci == 0xff01)
153 return;
148 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { 154 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
149 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); 155 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
150 rdev->pm.current_vddci = voltage->vddci; 156 rdev->pm.current_vddci = voltage->vddci;
@@ -979,17 +985,19 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
979{ 985{
980 save->vga_control[0] = RREG32(D1VGA_CONTROL); 986 save->vga_control[0] = RREG32(D1VGA_CONTROL);
981 save->vga_control[1] = RREG32(D2VGA_CONTROL); 987 save->vga_control[1] = RREG32(D2VGA_CONTROL);
982 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
983 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
984 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
985 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
986 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 988 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
987 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 989 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
988 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 990 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
989 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 991 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
990 if (!(rdev->flags & RADEON_IS_IGP)) { 992 if (rdev->num_crtc >= 4) {
993 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
994 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
991 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 995 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
992 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 996 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
997 }
998 if (rdev->num_crtc >= 6) {
999 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1000 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
993 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 1001 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
994 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 1002 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
995 } 1003 }
@@ -998,35 +1006,45 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
998 WREG32(VGA_RENDER_CONTROL, 0); 1006 WREG32(VGA_RENDER_CONTROL, 0);
999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1000 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1001 if (!(rdev->flags & RADEON_IS_IGP)) { 1009 if (rdev->num_crtc >= 4) {
1002 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1003 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1012 }
1013 if (rdev->num_crtc >= 6) {
1004 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1005 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1006 } 1016 }
1007 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1008 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1009 if (!(rdev->flags & RADEON_IS_IGP)) { 1019 if (rdev->num_crtc >= 4) {
1010 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1020 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1011 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1021 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1022 }
1023 if (rdev->num_crtc >= 6) {
1012 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1024 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1013 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1025 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1014 } 1026 }
1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1016 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1017 if (!(rdev->flags & RADEON_IS_IGP)) { 1029 if (rdev->num_crtc >= 4) {
1018 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1030 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1019 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1031 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1032 }
1033 if (rdev->num_crtc >= 6) {
1020 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1034 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1021 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1035 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1022 } 1036 }
1023 1037
1024 WREG32(D1VGA_CONTROL, 0); 1038 WREG32(D1VGA_CONTROL, 0);
1025 WREG32(D2VGA_CONTROL, 0); 1039 WREG32(D2VGA_CONTROL, 0);
1026 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1040 if (rdev->num_crtc >= 4) {
1027 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1041 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1028 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1042 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1029 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1043 }
1044 if (rdev->num_crtc >= 6) {
1045 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1046 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1047 }
1030} 1048}
1031 1049
1032void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1050void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1049,7 +1067,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1049 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1050 (u32)rdev->mc.vram_start); 1068 (u32)rdev->mc.vram_start);
1051 1069
1052 if (!(rdev->flags & RADEON_IS_IGP)) { 1070 if (rdev->num_crtc >= 4) {
1053 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1071 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1054 upper_32_bits(rdev->mc.vram_start)); 1072 upper_32_bits(rdev->mc.vram_start));
1055 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1073 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
@@ -1067,7 +1085,8 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1067 (u32)rdev->mc.vram_start); 1085 (u32)rdev->mc.vram_start);
1068 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1086 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1069 (u32)rdev->mc.vram_start); 1087 (u32)rdev->mc.vram_start);
1070 1088 }
1089 if (rdev->num_crtc >= 6) {
1071 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1072 upper_32_bits(rdev->mc.vram_start)); 1091 upper_32_bits(rdev->mc.vram_start));
1073 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
@@ -1095,31 +1114,41 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1095 /* Restore video state */ 1114 /* Restore video state */
1096 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1115 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1097 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1116 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1098 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1117 if (rdev->num_crtc >= 4) {
1099 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1118 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1100 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1119 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1101 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1120 }
1121 if (rdev->num_crtc >= 6) {
1122 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1123 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1124 }
1102 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1103 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1126 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1104 if (!(rdev->flags & RADEON_IS_IGP)) { 1127 if (rdev->num_crtc >= 4) {
1105 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1106 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1130 }
1131 if (rdev->num_crtc >= 6) {
1107 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1108 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1109 } 1134 }
1110 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1135 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1111 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1136 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1112 if (!(rdev->flags & RADEON_IS_IGP)) { 1137 if (rdev->num_crtc >= 4) {
1113 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1138 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1114 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1139 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1140 }
1141 if (rdev->num_crtc >= 6) {
1115 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1142 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1116 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1143 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1117 } 1144 }
1118 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1119 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1146 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1120 if (!(rdev->flags & RADEON_IS_IGP)) { 1147 if (rdev->num_crtc >= 4) {
1121 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1122 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1150 }
1151 if (rdev->num_crtc >= 6) {
1123 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1152 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1124 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1125 } 1154 }
@@ -1971,7 +2000,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1971 gb_backend_map = 0x66442200; 2000 gb_backend_map = 0x66442200;
1972 break; 2001 break;
1973 case CHIP_JUNIPER: 2002 case CHIP_JUNIPER:
1974 gb_backend_map = 0x00006420; 2003 gb_backend_map = 0x00002200;
1975 break; 2004 break;
1976 default: 2005 default:
1977 gb_backend_map = 2006 gb_backend_map =
@@ -2007,9 +2036,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2007 rdev->config.evergreen.tile_config |= (3 << 0); 2036 rdev->config.evergreen.tile_config |= (3 << 0);
2008 break; 2037 break;
2009 } 2038 }
2010 /* num banks is 8 on all fusion asics */ 2039 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2011 if (rdev->flags & RADEON_IS_IGP) 2040 if (rdev->flags & RADEON_IS_IGP)
2012 rdev->config.evergreen.tile_config |= 8 << 4; 2041 rdev->config.evergreen.tile_config |= 1 << 4;
2013 else 2042 else
2014 rdev->config.evergreen.tile_config |= 2043 rdev->config.evergreen.tile_config |=
2015 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 2044 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
@@ -2242,7 +2271,10 @@ int evergreen_mc_init(struct radeon_device *rdev)
2242 2271
2243 /* Get VRAM informations */ 2272 /* Get VRAM informations */
2244 rdev->mc.vram_is_ddr = true; 2273 rdev->mc.vram_is_ddr = true;
2245 tmp = RREG32(MC_ARB_RAMCFG); 2274 if (rdev->flags & RADEON_IS_IGP)
2275 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2276 else
2277 tmp = RREG32(MC_ARB_RAMCFG);
2246 if (tmp & CHANSIZE_OVERRIDE) { 2278 if (tmp & CHANSIZE_OVERRIDE) {
2247 chansize = 16; 2279 chansize = 16;
2248 } else if (tmp & CHANSIZE_MASK) { 2280 } else if (tmp & CHANSIZE_MASK) {
@@ -2408,18 +2440,22 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2408 WREG32(GRBM_INT_CNTL, 0); 2440 WREG32(GRBM_INT_CNTL, 0);
2409 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2441 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2410 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2442 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2411 if (!(rdev->flags & RADEON_IS_IGP)) { 2443 if (rdev->num_crtc >= 4) {
2412 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2444 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2413 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2445 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2446 }
2447 if (rdev->num_crtc >= 6) {
2414 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2448 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2415 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2449 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2416 } 2450 }
2417 2451
2418 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2452 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2419 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2453 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2420 if (!(rdev->flags & RADEON_IS_IGP)) { 2454 if (rdev->num_crtc >= 4) {
2421 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2455 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2422 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2456 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2457 }
2458 if (rdev->num_crtc >= 6) {
2423 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2459 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2424 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2460 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2425 } 2461 }
@@ -2538,19 +2574,25 @@ int evergreen_irq_set(struct radeon_device *rdev)
2538 2574
2539 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2575 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2540 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2576 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2541 if (!(rdev->flags & RADEON_IS_IGP)) { 2577 if (rdev->num_crtc >= 4) {
2542 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2578 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2543 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2579 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2580 }
2581 if (rdev->num_crtc >= 6) {
2544 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2582 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2545 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2583 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2546 } 2584 }
2547 2585
2548 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2586 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2549 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2587 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2550 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2588 if (rdev->num_crtc >= 4) {
2551 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2589 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2552 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2590 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2553 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2591 }
2592 if (rdev->num_crtc >= 6) {
2593 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2594 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2595 }
2554 2596
2555 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2597 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2556 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2598 WREG32(DC_HPD2_INT_CONTROL, hpd2);
@@ -2574,53 +2616,57 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
2574 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2616 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2575 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2617 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2576 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2618 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2577 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2619 if (rdev->num_crtc >= 4) {
2578 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2620 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2579 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2621 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2580 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2622 }
2623 if (rdev->num_crtc >= 6) {
2624 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2625 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2626 }
2581 2627
2582 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2628 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2583 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2584 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2630 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2585 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2631 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2586 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2587 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2588 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2589 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2590 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2591 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2592 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2593 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2594
2595 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2632 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2596 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2597 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2634 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2598 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2635 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2599
2600 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2601 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2637 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2602 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2603 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2639 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2604 2640
2605 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2641 if (rdev->num_crtc >= 4) {
2606 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2642 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2607 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2643 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2608 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2644 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2609 2645 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2610 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2646 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2611 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2647 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2612 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2648 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2613 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2649 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2614 2650 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2615 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2651 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2616 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2652 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2617 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2653 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2618 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2654 }
2619 2655
2620 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2656 if (rdev->num_crtc >= 6) {
2621 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2657 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2622 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2658 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2623 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2659 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2660 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2661 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2662 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2663 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2664 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2665 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2666 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2667 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2668 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2669 }
2624 2670
2625 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2671 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2626 tmp = RREG32(DC_HPD1_INT_CONTROL); 2672 tmp = RREG32(DC_HPD1_INT_CONTROL);
@@ -2695,28 +2741,25 @@ static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2695 2741
2696int evergreen_irq_process(struct radeon_device *rdev) 2742int evergreen_irq_process(struct radeon_device *rdev)
2697{ 2743{
2698 u32 wptr = evergreen_get_ih_wptr(rdev); 2744 u32 wptr;
2699 u32 rptr = rdev->ih.rptr; 2745 u32 rptr;
2700 u32 src_id, src_data; 2746 u32 src_id, src_data;
2701 u32 ring_index; 2747 u32 ring_index;
2702 unsigned long flags; 2748 unsigned long flags;
2703 bool queue_hotplug = false; 2749 bool queue_hotplug = false;
2704 2750
2705 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2751 if (!rdev->ih.enabled || rdev->shutdown)
2706 if (!rdev->ih.enabled)
2707 return IRQ_NONE; 2752 return IRQ_NONE;
2708 2753
2709 spin_lock_irqsave(&rdev->ih.lock, flags); 2754 wptr = evergreen_get_ih_wptr(rdev);
2755 rptr = rdev->ih.rptr;
2756 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2710 2757
2758 spin_lock_irqsave(&rdev->ih.lock, flags);
2711 if (rptr == wptr) { 2759 if (rptr == wptr) {
2712 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2760 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2713 return IRQ_NONE; 2761 return IRQ_NONE;
2714 } 2762 }
2715 if (rdev->shutdown) {
2716 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2717 return IRQ_NONE;
2718 }
2719
2720restart_ih: 2763restart_ih:
2721 /* display interrupts */ 2764 /* display interrupts */
2722 evergreen_irq_ack(rdev); 2765 evergreen_irq_ack(rdev);
@@ -3231,6 +3274,7 @@ void evergreen_fini(struct radeon_device *rdev)
3231 r700_cp_fini(rdev); 3274 r700_cp_fini(rdev);
3232 r600_irq_fini(rdev); 3275 r600_irq_fini(rdev);
3233 radeon_wb_fini(rdev); 3276 radeon_wb_fini(rdev);
3277 radeon_ib_pool_fini(rdev);
3234 radeon_irq_kms_fini(rdev); 3278 radeon_irq_kms_fini(rdev);
3235 evergreen_pcie_gart_fini(rdev); 3279 evergreen_pcie_gart_fini(rdev);
3236 radeon_gem_fini(rdev); 3280 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 57f3bc17b87e..2eb251858e72 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -252,7 +252,7 @@ draw_auto(struct radeon_device *rdev)
252 252
253} 253}
254 254
255/* emits 36 */ 255/* emits 39 */
256static void 256static void
257set_default_state(struct radeon_device *rdev) 257set_default_state(struct radeon_device *rdev)
258{ 258{
@@ -531,6 +531,11 @@ set_default_state(struct radeon_device *rdev)
531 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); 531 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
532 radeon_ring_write(rdev, 0); 532 radeon_ring_write(rdev, 0);
533 533
534 /* setup LDS */
535 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
536 radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
537 radeon_ring_write(rdev, 0x10001000);
538
534 /* SQ config */ 539 /* SQ config */
535 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); 540 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
536 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); 541 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
@@ -773,7 +778,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
773 /* calculate number of loops correctly */ 778 /* calculate number of loops correctly */
774 ring_size = num_loops * dwords_per_loop; 779 ring_size = num_loops * dwords_per_loop;
775 /* set default + shaders */ 780 /* set default + shaders */
776 ring_size += 52; /* shaders + def state */ 781 ring_size += 55; /* shaders + def state */
777 ring_size += 10; /* fence emit for VB IB */ 782 ring_size += 10; /* fence emit for VB IB */
778 ring_size += 5; /* done copy */ 783 ring_size += 5; /* done copy */
779 ring_size += 10; /* fence emit for done copy */ 784 ring_size += 10; /* fence emit for done copy */
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 1636e3449825..b7b2714f0b32 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -466,7 +466,7 @@
466#define IH_RB_WPTR_ADDR_LO 0x3e14 466#define IH_RB_WPTR_ADDR_LO 0x3e14
467#define IH_CNTL 0x3e18 467#define IH_CNTL 0x3e18
468# define ENABLE_INTR (1 << 0) 468# define ENABLE_INTR (1 << 0)
469# define IH_MC_SWAP(x) ((x) << 2) 469# define IH_MC_SWAP(x) ((x) << 1)
470# define IH_MC_SWAP_NONE 0 470# define IH_MC_SWAP_NONE 0
471# define IH_MC_SWAP_16BIT 1 471# define IH_MC_SWAP_16BIT 1
472# define IH_MC_SWAP_32BIT 2 472# define IH_MC_SWAP_32BIT 2
@@ -547,7 +547,7 @@
547# define LB_D5_VBLANK_INTERRUPT (1 << 3) 547# define LB_D5_VBLANK_INTERRUPT (1 << 3)
548# define DC_HPD5_INTERRUPT (1 << 17) 548# define DC_HPD5_INTERRUPT (1 << 17)
549# define DC_HPD5_RX_INTERRUPT (1 << 18) 549# define DC_HPD5_RX_INTERRUPT (1 << 18)
550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 550#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
551# define LB_D6_VLINE_INTERRUPT (1 << 2) 551# define LB_D6_VLINE_INTERRUPT (1 << 2)
552# define LB_D6_VBLANK_INTERRUPT (1 << 3) 552# define LB_D6_VBLANK_INTERRUPT (1 << 3)
553# define DC_HPD6_INTERRUPT (1 << 17) 553# define DC_HPD6_INTERRUPT (1 << 17)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 16caafeadf5e..559dbd412906 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1581,6 +1581,7 @@ void cayman_fini(struct radeon_device *rdev)
1581 cayman_cp_fini(rdev); 1581 cayman_cp_fini(rdev);
1582 r600_irq_fini(rdev); 1582 r600_irq_fini(rdev);
1583 radeon_wb_fini(rdev); 1583 radeon_wb_fini(rdev);
1584 radeon_ib_pool_fini(rdev);
1584 radeon_irq_kms_fini(rdev); 1585 radeon_irq_kms_fini(rdev);
1585 cayman_pcie_gart_fini(rdev); 1586 cayman_pcie_gart_fini(rdev);
1586 radeon_gem_fini(rdev); 1587 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 9736746da2d6..4672869cdb26 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -320,7 +320,7 @@
320#define CGTS_USER_TCC_DISABLE 0x914C 320#define CGTS_USER_TCC_DISABLE 0x914C
321#define TCC_DISABLE_MASK 0xFFFF0000 321#define TCC_DISABLE_MASK 0xFFFF0000
322#define TCC_DISABLE_SHIFT 16 322#define TCC_DISABLE_SHIFT 16
323#define CGTS_SM_CTRL_REG 0x915C 323#define CGTS_SM_CTRL_REG 0x9150
324#define OVERRIDE (1 << 21) 324#define OVERRIDE (1 << 21)
325 325
326#define TA_CNTL_AUX 0x9508 326#define TA_CNTL_AUX 0x9508
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 7dd45ca64e29..bc54b26cb32f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -590,6 +590,9 @@ void r600_pm_misc(struct radeon_device *rdev)
590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
591 591
592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
593 /* 0xff01 is a flag rather then an actual voltage */
594 if (voltage->voltage == 0xff01)
595 return;
593 if (voltage->voltage != rdev->pm.current_vddc) { 596 if (voltage->voltage != rdev->pm.current_vddc) {
594 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 597 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
595 rdev->pm.current_vddc = voltage->voltage; 598 rdev->pm.current_vddc = voltage->voltage;
@@ -2625,6 +2628,7 @@ void r600_fini(struct radeon_device *rdev)
2625 r600_cp_fini(rdev); 2628 r600_cp_fini(rdev);
2626 r600_irq_fini(rdev); 2629 r600_irq_fini(rdev);
2627 radeon_wb_fini(rdev); 2630 radeon_wb_fini(rdev);
2631 radeon_ib_pool_fini(rdev);
2628 radeon_irq_kms_fini(rdev); 2632 radeon_irq_kms_fini(rdev);
2629 r600_pcie_gart_fini(rdev); 2633 r600_pcie_gart_fini(rdev);
2630 radeon_agp_fini(rdev); 2634 radeon_agp_fini(rdev);
@@ -3294,27 +3298,26 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3294 3298
3295int r600_irq_process(struct radeon_device *rdev) 3299int r600_irq_process(struct radeon_device *rdev)
3296{ 3300{
3297 u32 wptr = r600_get_ih_wptr(rdev); 3301 u32 wptr;
3298 u32 rptr = rdev->ih.rptr; 3302 u32 rptr;
3299 u32 src_id, src_data; 3303 u32 src_id, src_data;
3300 u32 ring_index; 3304 u32 ring_index;
3301 unsigned long flags; 3305 unsigned long flags;
3302 bool queue_hotplug = false; 3306 bool queue_hotplug = false;
3303 3307
3304 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3308 if (!rdev->ih.enabled || rdev->shutdown)
3305 if (!rdev->ih.enabled)
3306 return IRQ_NONE; 3309 return IRQ_NONE;
3307 3310
3311 wptr = r600_get_ih_wptr(rdev);
3312 rptr = rdev->ih.rptr;
3313 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3314
3308 spin_lock_irqsave(&rdev->ih.lock, flags); 3315 spin_lock_irqsave(&rdev->ih.lock, flags);
3309 3316
3310 if (rptr == wptr) { 3317 if (rptr == wptr) {
3311 spin_unlock_irqrestore(&rdev->ih.lock, flags); 3318 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3312 return IRQ_NONE; 3319 return IRQ_NONE;
3313 } 3320 }
3314 if (rdev->shutdown) {
3315 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3316 return IRQ_NONE;
3317 }
3318 3321
3319restart_ih: 3322restart_ih:
3320 /* display interrupts */ 3323 /* display interrupts */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index f140a0d5cb54..0245ae6c204e 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -536,7 +536,7 @@
536#define IH_RB_WPTR_ADDR_LO 0x3e14 536#define IH_RB_WPTR_ADDR_LO 0x3e14
537#define IH_CNTL 0x3e18 537#define IH_CNTL 0x3e18
538# define ENABLE_INTR (1 << 0) 538# define ENABLE_INTR (1 << 0)
539# define IH_MC_SWAP(x) ((x) << 2) 539# define IH_MC_SWAP(x) ((x) << 1)
540# define IH_MC_SWAP_NONE 0 540# define IH_MC_SWAP_NONE 0
541# define IH_MC_SWAP_16BIT 1 541# define IH_MC_SWAP_16BIT 1
542# define IH_MC_SWAP_32BIT 2 542# define IH_MC_SWAP_32BIT 2
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 27f45579e64b..ef0e0e016914 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -179,6 +179,7 @@ void radeon_pm_resume(struct radeon_device *rdev);
179void radeon_combios_get_power_modes(struct radeon_device *rdev); 179void radeon_combios_get_power_modes(struct radeon_device *rdev);
180void radeon_atombios_get_power_modes(struct radeon_device *rdev); 180void radeon_atombios_get_power_modes(struct radeon_device *rdev);
181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
182int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
182void rs690_pm_info(struct radeon_device *rdev); 183void rs690_pm_info(struct radeon_device *rdev);
183extern int rv6xx_get_temp(struct radeon_device *rdev); 184extern int rv6xx_get_temp(struct radeon_device *rdev);
184extern int rv770_get_temp(struct radeon_device *rdev); 185extern int rv770_get_temp(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index fa62a503ae70..bf2b61584cdb 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2320,6 +2320,14 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2320 le16_to_cpu(clock_info->r600.usVDDC); 2320 le16_to_cpu(clock_info->r600.usVDDC);
2321 } 2321 }
2322 2322
2323 /* patch up vddc if necessary */
2324 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2325 u16 vddc;
2326
2327 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2328 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2329 }
2330
2323 if (rdev->flags & RADEON_IS_IGP) { 2331 if (rdev->flags & RADEON_IS_IGP) {
2324 /* skip invalid modes */ 2332 /* skip invalid modes */
2325 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2333 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
@@ -2607,6 +2615,10 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v
2607 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2615 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2608 return; 2616 return;
2609 2617
2618 /* 0xff01 is a flag rather then an actual voltage */
2619 if (voltage_level == 0xff01)
2620 return;
2621
2610 switch (crev) { 2622 switch (crev) {
2611 case 1: 2623 case 1:
2612 args.v1.ucVoltageType = voltage_type; 2624 args.v1.ucVoltageType = voltage_type;
@@ -2626,7 +2638,35 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v
2626 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2627} 2639}
2628 2640
2641int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2642 u16 *voltage)
2643{
2644 union set_voltage args;
2645 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2646 u8 frev, crev;
2647
2648 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2649 return -EINVAL;
2650
2651 switch (crev) {
2652 case 1:
2653 return -EINVAL;
2654 case 2:
2655 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2656 args.v2.ucVoltageMode = 0;
2657 args.v2.usVoltageLevel = 0;
2658
2659 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2629 2660
2661 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2662 break;
2663 default:
2664 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2665 return -EINVAL;
2666 }
2667
2668 return 0;
2669}
2630 2670
2631void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 2671void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2632{ 2672{
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 1aba85cad1a8..229a20f10e2b 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -104,7 +104,7 @@ static bool radeon_read_bios(struct radeon_device *rdev)
104static bool radeon_atrm_get_bios(struct radeon_device *rdev) 104static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{ 105{
106 int ret; 106 int ret;
107 int size = 64 * 1024; 107 int size = 256 * 1024;
108 int i; 108 int i;
109 109
110 if (!radeon_atrm_supported(rdev->pdev)) 110 if (!radeon_atrm_supported(rdev->pdev))
@@ -331,7 +331,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
331 331
332 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 332 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
333 viph_control = RREG32(RADEON_VIPH_CONTROL); 333 viph_control = RREG32(RADEON_VIPH_CONTROL);
334 bus_cntl = RREG32(RADEON_BUS_CNTL); 334 bus_cntl = RREG32(RV370_BUS_CNTL);
335 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 335 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
336 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 336 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
337 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 337 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -350,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
351 351
352 /* enable the rom */ 352 /* enable the rom */
353 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 353 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
354 354
355 /* Disable VGA mode */ 355 /* Disable VGA mode */
356 WREG32(AVIVO_D1VGA_CONTROL, 356 WREG32(AVIVO_D1VGA_CONTROL,
@@ -367,7 +367,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
367 /* restore regs */ 367 /* restore regs */
368 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 368 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
369 WREG32(RADEON_VIPH_CONTROL, viph_control); 369 WREG32(RADEON_VIPH_CONTROL, viph_control);
370 WREG32(RADEON_BUS_CNTL, bus_cntl); 370 WREG32(RV370_BUS_CNTL, bus_cntl);
371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -390,7 +390,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
390 390
391 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 391 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
392 viph_control = RREG32(RADEON_VIPH_CONTROL); 392 viph_control = RREG32(RADEON_VIPH_CONTROL);
393 bus_cntl = RREG32(RADEON_BUS_CNTL); 393 if (rdev->flags & RADEON_IS_PCIE)
394 bus_cntl = RREG32(RV370_BUS_CNTL);
395 else
396 bus_cntl = RREG32(RADEON_BUS_CNTL);
394 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 397 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
395 crtc2_gen_cntl = 0; 398 crtc2_gen_cntl = 0;
396 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 399 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
@@ -412,7 +415,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
412 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 415 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
413 416
414 /* enable the rom */ 417 /* enable the rom */
415 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 418 if (rdev->flags & RADEON_IS_PCIE)
419 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
420 else
421 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
416 422
417 /* Turn off mem requests and CRTC for both controllers */ 423 /* Turn off mem requests and CRTC for both controllers */
418 WREG32(RADEON_CRTC_GEN_CNTL, 424 WREG32(RADEON_CRTC_GEN_CNTL,
@@ -439,7 +445,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
439 /* restore regs */ 445 /* restore regs */
440 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 446 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
441 WREG32(RADEON_VIPH_CONTROL, viph_control); 447 WREG32(RADEON_VIPH_CONTROL, viph_control);
442 WREG32(RADEON_BUS_CNTL, bus_cntl); 448 if (rdev->flags & RADEON_IS_PCIE)
449 WREG32(RV370_BUS_CNTL, bus_cntl);
450 else
451 WREG32(RADEON_BUS_CNTL, bus_cntl);
443 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 452 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
444 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 453 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
445 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 454 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index cbfca3a24fdf..9792d4ffdc86 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -52,6 +52,12 @@ void radeon_connector_hotplug(struct drm_connector *connector)
52 struct radeon_device *rdev = dev->dev_private; 52 struct radeon_device *rdev = dev->dev_private;
53 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 53 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
54 54
55 /* bail if the connector does not have hpd pin, e.g.,
56 * VGA, TV, etc.
57 */
58 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE)
59 return;
60
55 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 61 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
56 62
57 /* powering up/down the eDP panel generates hpd events which 63 /* powering up/down the eDP panel generates hpd events which
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index f55b64cb59d1..b293487e5aa3 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1090,9 +1090,10 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1090 break; 1090 break;
1091 } 1091 }
1092 1092
1093 if (is_dp) 1093 if (is_dp) {
1094 args.v2.acConfig.fCoherentMode = 1; 1094 args.v2.acConfig.fCoherentMode = 1;
1095 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1095 args.v2.acConfig.fDPConnector = 1;
1096 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1096 if (dig->coherent_mode) 1097 if (dig->coherent_mode)
1097 args.v2.acConfig.fCoherentMode = 1; 1098 args.v2.acConfig.fCoherentMode = 1;
1098 if (radeon_encoder->pixel_clock > 165000) 1099 if (radeon_encoder->pixel_clock > 165000)
@@ -1431,7 +1432,11 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1431 if (is_dig) { 1432 if (is_dig) {
1432 switch (mode) { 1433 switch (mode) {
1433 case DRM_MODE_DPMS_ON: 1434 case DRM_MODE_DPMS_ON:
1434 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1435 /* some early dce3.2 boards have a bug in their transmitter control table */
1436 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1437 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1438 else
1439 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1435 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1440 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1436 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1441 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1437 1442
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index ec93a75369e6..bc44a3d35ec6 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -300,6 +300,8 @@
300# define RADEON_BUS_READ_BURST (1 << 30) 300# define RADEON_BUS_READ_BURST (1 << 30)
301#define RADEON_BUS_CNTL1 0x0034 301#define RADEON_BUS_CNTL1 0x0034
302# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) 302# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
303#define RV370_BUS_CNTL 0x004c
304# define RV370_BUS_BIOS_DIS_ROM (1 << 2)
303/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 305/* rv370/rv380, rv410, r423/r430/r480, r5xx */
304#define RADEON_MSI_REARM_EN 0x0160 306#define RADEON_MSI_REARM_EN 0x0160
305# define RV370_MSI_REARM_EN (1 << 0) 307# define RV370_MSI_REARM_EN (1 << 0)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 6e3b11e5abbe..1f5850e473cc 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -426,7 +426,7 @@ int rs600_gart_init(struct radeon_device *rdev)
426 return radeon_gart_table_vram_alloc(rdev); 426 return radeon_gart_table_vram_alloc(rdev);
427} 427}
428 428
429int rs600_gart_enable(struct radeon_device *rdev) 429static int rs600_gart_enable(struct radeon_device *rdev)
430{ 430{
431 u32 tmp; 431 u32 tmp;
432 int r, i; 432 int r, i;
@@ -440,8 +440,8 @@ int rs600_gart_enable(struct radeon_device *rdev)
440 return r; 440 return r;
441 radeon_gart_restore(rdev); 441 radeon_gart_restore(rdev);
442 /* Enable bus master */ 442 /* Enable bus master */
443 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; 443 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
444 WREG32(R_00004C_BUS_CNTL, tmp); 444 WREG32(RADEON_BUS_CNTL, tmp);
445 /* FIXME: setup default page */ 445 /* FIXME: setup default page */
446 WREG32_MC(R_000100_MC_PT0_CNTL, 446 WREG32_MC(R_000100_MC_PT0_CNTL,
447 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 447 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index ef8a5babe9f7..4de51891aa6d 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -105,6 +105,9 @@ void rv770_pm_misc(struct radeon_device *rdev)
105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
106 106
107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
108 /* 0xff01 is a flag rather then an actual voltage */
109 if (voltage->voltage == 0xff01)
110 return;
108 if (voltage->voltage != rdev->pm.current_vddc) { 111 if (voltage->voltage != rdev->pm.current_vddc) {
109 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 112 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
110 rdev->pm.current_vddc = voltage->voltage; 113 rdev->pm.current_vddc = voltage->voltage;
@@ -572,6 +575,12 @@ static void rv770_program_channel_remap(struct radeon_device *rdev)
572 else 575 else
573 tcp_chan_steer = 0x00fac688; 576 tcp_chan_steer = 0x00fac688;
574 577
578 /* RV770 CE has special chremap setup */
579 if (rdev->pdev->device == 0x944e) {
580 tcp_chan_steer = 0x00b08b08;
581 mc_shared_chremap = 0x00b08b08;
582 }
583
575 WREG32(TCP_CHAN_STEER, tcp_chan_steer); 584 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
576 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 585 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
577} 586}
@@ -1359,6 +1368,7 @@ void rv770_fini(struct radeon_device *rdev)
1359 r700_cp_fini(rdev); 1368 r700_cp_fini(rdev);
1360 r600_irq_fini(rdev); 1369 r600_irq_fini(rdev);
1361 radeon_wb_fini(rdev); 1370 radeon_wb_fini(rdev);
1371 radeon_ib_pool_fini(rdev);
1362 radeon_irq_kms_fini(rdev); 1372 radeon_irq_kms_fini(rdev);
1363 rv770_pcie_gart_fini(rdev); 1373 rv770_pcie_gart_fini(rdev);
1364 rv770_vram_scratch_fini(rdev); 1374 rv770_vram_scratch_fini(rdev);
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 90e23e0bfadb..58c271ebc0f7 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -31,6 +31,7 @@
31#include <linux/sched.h> 31#include <linux/sched.h>
32#include <linux/highmem.h> 32#include <linux/highmem.h>
33#include <linux/pagemap.h> 33#include <linux/pagemap.h>
34#include <linux/shmem_fs.h>
34#include <linux/file.h> 35#include <linux/file.h>
35#include <linux/swap.h> 36#include <linux/swap.h>
36#include <linux/slab.h> 37#include <linux/slab.h>
@@ -484,7 +485,7 @@ static int ttm_tt_swapin(struct ttm_tt *ttm)
484 swap_space = swap_storage->f_path.dentry->d_inode->i_mapping; 485 swap_space = swap_storage->f_path.dentry->d_inode->i_mapping;
485 486
486 for (i = 0; i < ttm->num_pages; ++i) { 487 for (i = 0; i < ttm->num_pages; ++i) {
487 from_page = read_mapping_page(swap_space, i, NULL); 488 from_page = shmem_read_mapping_page(swap_space, i);
488 if (IS_ERR(from_page)) { 489 if (IS_ERR(from_page)) {
489 ret = PTR_ERR(from_page); 490 ret = PTR_ERR(from_page);
490 goto out_err; 491 goto out_err;
@@ -557,7 +558,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage)
557 from_page = ttm->pages[i]; 558 from_page = ttm->pages[i];
558 if (unlikely(from_page == NULL)) 559 if (unlikely(from_page == NULL))
559 continue; 560 continue;
560 to_page = read_mapping_page(swap_space, i, NULL); 561 to_page = shmem_read_mapping_page(swap_space, i);
561 if (unlikely(IS_ERR(to_page))) { 562 if (unlikely(IS_ERR(to_page))) {
562 ret = PTR_ERR(to_page); 563 ret = PTR_ERR(to_page);
563 goto out_err; 564 goto out_err;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 10:13:46 -0500