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path: root/drivers/gpu/drm/tegra/gr3d.c
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Diffstat (limited to 'drivers/gpu/drm/tegra/gr3d.c')
-rw-r--r--drivers/gpu/drm/tegra/gr3d.c338
1 files changed, 338 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
new file mode 100644
index 000000000000..4cec8f526af7
--- /dev/null
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -0,0 +1,338 @@
1/*
2 * Copyright (C) 2013 Avionic Design GmbH
3 * Copyright (C) 2013 NVIDIA Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/host1x.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/tegra-powergate.h>
15
16#include "drm.h"
17#include "gem.h"
18#include "gr3d.h"
19
20struct gr3d {
21 struct tegra_drm_client client;
22 struct host1x_channel *channel;
23 struct clk *clk_secondary;
24 struct clk *clk;
25
26 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
27};
28
29static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
30{
31 return container_of(client, struct gr3d, client);
32}
33
34static int gr3d_init(struct host1x_client *client)
35{
36 struct tegra_drm_client *drm = host1x_to_drm_client(client);
37 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
38 unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
39 struct gr3d *gr3d = to_gr3d(drm);
40
41 gr3d->channel = host1x_channel_request(client->dev);
42 if (!gr3d->channel)
43 return -ENOMEM;
44
45 client->syncpts[0] = host1x_syncpt_request(client->dev, flags);
46 if (!client->syncpts[0]) {
47 host1x_channel_free(gr3d->channel);
48 return -ENOMEM;
49 }
50
51 return tegra_drm_register_client(tegra, drm);
52}
53
54static int gr3d_exit(struct host1x_client *client)
55{
56 struct tegra_drm_client *drm = host1x_to_drm_client(client);
57 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
58 struct gr3d *gr3d = to_gr3d(drm);
59 int err;
60
61 err = tegra_drm_unregister_client(tegra, drm);
62 if (err < 0)
63 return err;
64
65 host1x_syncpt_free(client->syncpts[0]);
66 host1x_channel_free(gr3d->channel);
67
68 return 0;
69}
70
71static const struct host1x_client_ops gr3d_client_ops = {
72 .init = gr3d_init,
73 .exit = gr3d_exit,
74};
75
76static int gr3d_open_channel(struct tegra_drm_client *client,
77 struct tegra_drm_context *context)
78{
79 struct gr3d *gr3d = to_gr3d(client);
80
81 context->channel = host1x_channel_get(gr3d->channel);
82 if (!context->channel)
83 return -ENOMEM;
84
85 return 0;
86}
87
88static void gr3d_close_channel(struct tegra_drm_context *context)
89{
90 host1x_channel_put(context->channel);
91}
92
93static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
94{
95 struct gr3d *gr3d = dev_get_drvdata(dev);
96
97 switch (class) {
98 case HOST1X_CLASS_HOST1X:
99 if (offset == 0x2b)
100 return 1;
101
102 break;
103
104 case HOST1X_CLASS_GR3D:
105 if (offset >= GR3D_NUM_REGS)
106 break;
107
108 if (test_bit(offset, gr3d->addr_regs))
109 return 1;
110
111 break;
112 }
113
114 return 0;
115}
116
117static const struct tegra_drm_client_ops gr3d_ops = {
118 .open_channel = gr3d_open_channel,
119 .close_channel = gr3d_close_channel,
120 .is_addr_reg = gr3d_is_addr_reg,
121 .submit = tegra_drm_submit,
122};
123
124static const struct of_device_id tegra_gr3d_match[] = {
125 { .compatible = "nvidia,tegra114-gr3d" },
126 { .compatible = "nvidia,tegra30-gr3d" },
127 { .compatible = "nvidia,tegra20-gr3d" },
128 { }
129};
130
131static const u32 gr3d_addr_regs[] = {
132 GR3D_IDX_ATTRIBUTE( 0),
133 GR3D_IDX_ATTRIBUTE( 1),
134 GR3D_IDX_ATTRIBUTE( 2),
135 GR3D_IDX_ATTRIBUTE( 3),
136 GR3D_IDX_ATTRIBUTE( 4),
137 GR3D_IDX_ATTRIBUTE( 5),
138 GR3D_IDX_ATTRIBUTE( 6),
139 GR3D_IDX_ATTRIBUTE( 7),
140 GR3D_IDX_ATTRIBUTE( 8),
141 GR3D_IDX_ATTRIBUTE( 9),
142 GR3D_IDX_ATTRIBUTE(10),
143 GR3D_IDX_ATTRIBUTE(11),
144 GR3D_IDX_ATTRIBUTE(12),
145 GR3D_IDX_ATTRIBUTE(13),
146 GR3D_IDX_ATTRIBUTE(14),
147 GR3D_IDX_ATTRIBUTE(15),
148 GR3D_IDX_INDEX_BASE,
149 GR3D_QR_ZTAG_ADDR,
150 GR3D_QR_CTAG_ADDR,
151 GR3D_QR_CZ_ADDR,
152 GR3D_TEX_TEX_ADDR( 0),
153 GR3D_TEX_TEX_ADDR( 1),
154 GR3D_TEX_TEX_ADDR( 2),
155 GR3D_TEX_TEX_ADDR( 3),
156 GR3D_TEX_TEX_ADDR( 4),
157 GR3D_TEX_TEX_ADDR( 5),
158 GR3D_TEX_TEX_ADDR( 6),
159 GR3D_TEX_TEX_ADDR( 7),
160 GR3D_TEX_TEX_ADDR( 8),
161 GR3D_TEX_TEX_ADDR( 9),
162 GR3D_TEX_TEX_ADDR(10),
163 GR3D_TEX_TEX_ADDR(11),
164 GR3D_TEX_TEX_ADDR(12),
165 GR3D_TEX_TEX_ADDR(13),
166 GR3D_TEX_TEX_ADDR(14),
167 GR3D_TEX_TEX_ADDR(15),
168 GR3D_DW_MEMORY_OUTPUT_ADDRESS,
169 GR3D_GLOBAL_SURFADDR( 0),
170 GR3D_GLOBAL_SURFADDR( 1),
171 GR3D_GLOBAL_SURFADDR( 2),
172 GR3D_GLOBAL_SURFADDR( 3),
173 GR3D_GLOBAL_SURFADDR( 4),
174 GR3D_GLOBAL_SURFADDR( 5),
175 GR3D_GLOBAL_SURFADDR( 6),
176 GR3D_GLOBAL_SURFADDR( 7),
177 GR3D_GLOBAL_SURFADDR( 8),
178 GR3D_GLOBAL_SURFADDR( 9),
179 GR3D_GLOBAL_SURFADDR(10),
180 GR3D_GLOBAL_SURFADDR(11),
181 GR3D_GLOBAL_SURFADDR(12),
182 GR3D_GLOBAL_SURFADDR(13),
183 GR3D_GLOBAL_SURFADDR(14),
184 GR3D_GLOBAL_SURFADDR(15),
185 GR3D_GLOBAL_SPILLSURFADDR,
186 GR3D_GLOBAL_SURFOVERADDR( 0),
187 GR3D_GLOBAL_SURFOVERADDR( 1),
188 GR3D_GLOBAL_SURFOVERADDR( 2),
189 GR3D_GLOBAL_SURFOVERADDR( 3),
190 GR3D_GLOBAL_SURFOVERADDR( 4),
191 GR3D_GLOBAL_SURFOVERADDR( 5),
192 GR3D_GLOBAL_SURFOVERADDR( 6),
193 GR3D_GLOBAL_SURFOVERADDR( 7),
194 GR3D_GLOBAL_SURFOVERADDR( 8),
195 GR3D_GLOBAL_SURFOVERADDR( 9),
196 GR3D_GLOBAL_SURFOVERADDR(10),
197 GR3D_GLOBAL_SURFOVERADDR(11),
198 GR3D_GLOBAL_SURFOVERADDR(12),
199 GR3D_GLOBAL_SURFOVERADDR(13),
200 GR3D_GLOBAL_SURFOVERADDR(14),
201 GR3D_GLOBAL_SURFOVERADDR(15),
202 GR3D_GLOBAL_SAMP01SURFADDR( 0),
203 GR3D_GLOBAL_SAMP01SURFADDR( 1),
204 GR3D_GLOBAL_SAMP01SURFADDR( 2),
205 GR3D_GLOBAL_SAMP01SURFADDR( 3),
206 GR3D_GLOBAL_SAMP01SURFADDR( 4),
207 GR3D_GLOBAL_SAMP01SURFADDR( 5),
208 GR3D_GLOBAL_SAMP01SURFADDR( 6),
209 GR3D_GLOBAL_SAMP01SURFADDR( 7),
210 GR3D_GLOBAL_SAMP01SURFADDR( 8),
211 GR3D_GLOBAL_SAMP01SURFADDR( 9),
212 GR3D_GLOBAL_SAMP01SURFADDR(10),
213 GR3D_GLOBAL_SAMP01SURFADDR(11),
214 GR3D_GLOBAL_SAMP01SURFADDR(12),
215 GR3D_GLOBAL_SAMP01SURFADDR(13),
216 GR3D_GLOBAL_SAMP01SURFADDR(14),
217 GR3D_GLOBAL_SAMP01SURFADDR(15),
218 GR3D_GLOBAL_SAMP23SURFADDR( 0),
219 GR3D_GLOBAL_SAMP23SURFADDR( 1),
220 GR3D_GLOBAL_SAMP23SURFADDR( 2),
221 GR3D_GLOBAL_SAMP23SURFADDR( 3),
222 GR3D_GLOBAL_SAMP23SURFADDR( 4),
223 GR3D_GLOBAL_SAMP23SURFADDR( 5),
224 GR3D_GLOBAL_SAMP23SURFADDR( 6),
225 GR3D_GLOBAL_SAMP23SURFADDR( 7),
226 GR3D_GLOBAL_SAMP23SURFADDR( 8),
227 GR3D_GLOBAL_SAMP23SURFADDR( 9),
228 GR3D_GLOBAL_SAMP23SURFADDR(10),
229 GR3D_GLOBAL_SAMP23SURFADDR(11),
230 GR3D_GLOBAL_SAMP23SURFADDR(12),
231 GR3D_GLOBAL_SAMP23SURFADDR(13),
232 GR3D_GLOBAL_SAMP23SURFADDR(14),
233 GR3D_GLOBAL_SAMP23SURFADDR(15),
234};
235
236static int gr3d_probe(struct platform_device *pdev)
237{
238 struct device_node *np = pdev->dev.of_node;
239 struct host1x_syncpt **syncpts;
240 struct gr3d *gr3d;
241 unsigned int i;
242 int err;
243
244 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
245 if (!gr3d)
246 return -ENOMEM;
247
248 syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
249 if (!syncpts)
250 return -ENOMEM;
251
252 gr3d->clk = devm_clk_get(&pdev->dev, NULL);
253 if (IS_ERR(gr3d->clk)) {
254 dev_err(&pdev->dev, "cannot get clock\n");
255 return PTR_ERR(gr3d->clk);
256 }
257
258 if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
259 gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
260 if (IS_ERR(gr3d->clk)) {
261 dev_err(&pdev->dev, "cannot get secondary clock\n");
262 return PTR_ERR(gr3d->clk);
263 }
264 }
265
266 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
267 if (err < 0) {
268 dev_err(&pdev->dev, "failed to power up 3D unit\n");
269 return err;
270 }
271
272 if (gr3d->clk_secondary) {
273 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
274 gr3d->clk_secondary);
275 if (err < 0) {
276 dev_err(&pdev->dev,
277 "failed to power up secondary 3D unit\n");
278 return err;
279 }
280 }
281
282 INIT_LIST_HEAD(&gr3d->client.base.list);
283 gr3d->client.base.ops = &gr3d_client_ops;
284 gr3d->client.base.dev = &pdev->dev;
285 gr3d->client.base.class = HOST1X_CLASS_GR3D;
286 gr3d->client.base.syncpts = syncpts;
287 gr3d->client.base.num_syncpts = 1;
288
289 INIT_LIST_HEAD(&gr3d->client.list);
290 gr3d->client.ops = &gr3d_ops;
291
292 err = host1x_client_register(&gr3d->client.base);
293 if (err < 0) {
294 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
295 err);
296 return err;
297 }
298
299 /* initialize address register map */
300 for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
301 set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
302
303 platform_set_drvdata(pdev, gr3d);
304
305 return 0;
306}
307
308static int gr3d_remove(struct platform_device *pdev)
309{
310 struct gr3d *gr3d = platform_get_drvdata(pdev);
311 int err;
312
313 err = host1x_client_unregister(&gr3d->client.base);
314 if (err < 0) {
315 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
316 err);
317 return err;
318 }
319
320 if (gr3d->clk_secondary) {
321 tegra_powergate_power_off(TEGRA_POWERGATE_3D1);
322 clk_disable_unprepare(gr3d->clk_secondary);
323 }
324
325 tegra_powergate_power_off(TEGRA_POWERGATE_3D);
326 clk_disable_unprepare(gr3d->clk);
327
328 return 0;
329}
330
331struct platform_driver tegra_gr3d_driver = {
332 .driver = {
333 .name = "tegra-gr3d",
334 .of_match_table = tegra_gr3d_match,
335 },
336 .probe = gr3d_probe,
337 .remove = gr3d_remove,
338};
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