diff options
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.c')
-rw-r--r-- | drivers/gpu/drm/tegra/dc.c | 48 |
1 files changed, 36 insertions, 12 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 3367960286a6..978993fa3a36 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c | |||
@@ -168,7 +168,7 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |||
168 | const struct tegra_dc_window *window) | 168 | const struct tegra_dc_window *window) |
169 | { | 169 | { |
170 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; | 170 | unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; |
171 | unsigned long value; | 171 | unsigned long value, flags; |
172 | bool yuv, planar; | 172 | bool yuv, planar; |
173 | 173 | ||
174 | /* | 174 | /* |
@@ -181,6 +181,8 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |||
181 | else | 181 | else |
182 | bpp = planar ? 1 : 2; | 182 | bpp = planar ? 1 : 2; |
183 | 183 | ||
184 | spin_lock_irqsave(&dc->lock, flags); | ||
185 | |||
184 | value = WINDOW_A_SELECT << index; | 186 | value = WINDOW_A_SELECT << index; |
185 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | 187 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); |
186 | 188 | ||
@@ -273,6 +275,7 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |||
273 | 275 | ||
274 | case TEGRA_BO_TILING_MODE_BLOCK: | 276 | case TEGRA_BO_TILING_MODE_BLOCK: |
275 | DRM_ERROR("hardware doesn't support block linear mode\n"); | 277 | DRM_ERROR("hardware doesn't support block linear mode\n"); |
278 | spin_unlock_irqrestore(&dc->lock, flags); | ||
276 | return -EINVAL; | 279 | return -EINVAL; |
277 | } | 280 | } |
278 | 281 | ||
@@ -331,6 +334,8 @@ static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, | |||
331 | 334 | ||
332 | tegra_dc_window_commit(dc, index); | 335 | tegra_dc_window_commit(dc, index); |
333 | 336 | ||
337 | spin_unlock_irqrestore(&dc->lock, flags); | ||
338 | |||
334 | return 0; | 339 | return 0; |
335 | } | 340 | } |
336 | 341 | ||
@@ -338,11 +343,14 @@ static int tegra_window_plane_disable(struct drm_plane *plane) | |||
338 | { | 343 | { |
339 | struct tegra_dc *dc = to_tegra_dc(plane->crtc); | 344 | struct tegra_dc *dc = to_tegra_dc(plane->crtc); |
340 | struct tegra_plane *p = to_tegra_plane(plane); | 345 | struct tegra_plane *p = to_tegra_plane(plane); |
346 | unsigned long flags; | ||
341 | u32 value; | 347 | u32 value; |
342 | 348 | ||
343 | if (!plane->crtc) | 349 | if (!plane->crtc) |
344 | return 0; | 350 | return 0; |
345 | 351 | ||
352 | spin_lock_irqsave(&dc->lock, flags); | ||
353 | |||
346 | value = WINDOW_A_SELECT << p->index; | 354 | value = WINDOW_A_SELECT << p->index; |
347 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); | 355 | tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); |
348 | 356 | ||
@@ -352,6 +360,8 @@ static int tegra_window_plane_disable(struct drm_plane *plane) | |||
352 | 360 | ||
353 | tegra_dc_window_commit(dc, p->index); | 361 | tegra_dc_window_commit(dc, p->index); |
354 | 362 | ||
363 | spin_unlock_irqrestore(&dc->lock, flags); | ||
364 | |||
355 | return 0; | 365 | return 0; |
356 | } | 366 | } |
357 | 367 | ||
@@ -699,14 +709,16 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, | |||
699 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); | 709 | struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); |
700 | unsigned int h_offset = 0, v_offset = 0; | 710 | unsigned int h_offset = 0, v_offset = 0; |
701 | struct tegra_bo_tiling tiling; | 711 | struct tegra_bo_tiling tiling; |
712 | unsigned long value, flags; | ||
702 | unsigned int format, swap; | 713 | unsigned int format, swap; |
703 | unsigned long value; | ||
704 | int err; | 714 | int err; |
705 | 715 | ||
706 | err = tegra_fb_get_tiling(fb, &tiling); | 716 | err = tegra_fb_get_tiling(fb, &tiling); |
707 | if (err < 0) | 717 | if (err < 0) |
708 | return err; | 718 | return err; |
709 | 719 | ||
720 | spin_lock_irqsave(&dc->lock, flags); | ||
721 | |||
710 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); | 722 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); |
711 | 723 | ||
712 | value = fb->offsets[0] + y * fb->pitches[0] + | 724 | value = fb->offsets[0] + y * fb->pitches[0] + |
@@ -752,6 +764,7 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, | |||
752 | 764 | ||
753 | case TEGRA_BO_TILING_MODE_BLOCK: | 765 | case TEGRA_BO_TILING_MODE_BLOCK: |
754 | DRM_ERROR("hardware doesn't support block linear mode\n"); | 766 | DRM_ERROR("hardware doesn't support block linear mode\n"); |
767 | spin_unlock_irqrestore(&dc->lock, flags); | ||
755 | return -EINVAL; | 768 | return -EINVAL; |
756 | } | 769 | } |
757 | 770 | ||
@@ -778,6 +791,8 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, | |||
778 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); | 791 | tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL); |
779 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); | 792 | tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); |
780 | 793 | ||
794 | spin_unlock_irqrestore(&dc->lock, flags); | ||
795 | |||
781 | return 0; | 796 | return 0; |
782 | } | 797 | } |
783 | 798 | ||
@@ -814,23 +829,32 @@ static void tegra_dc_finish_page_flip(struct tegra_dc *dc) | |||
814 | unsigned long flags, base; | 829 | unsigned long flags, base; |
815 | struct tegra_bo *bo; | 830 | struct tegra_bo *bo; |
816 | 831 | ||
817 | if (!dc->event) | 832 | spin_lock_irqsave(&drm->event_lock, flags); |
833 | |||
834 | if (!dc->event) { | ||
835 | spin_unlock_irqrestore(&drm->event_lock, flags); | ||
818 | return; | 836 | return; |
837 | } | ||
819 | 838 | ||
820 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); | 839 | bo = tegra_fb_get_plane(crtc->primary->fb, 0); |
821 | 840 | ||
841 | spin_lock_irqsave(&dc->lock, flags); | ||
842 | |||
822 | /* check if new start address has been latched */ | 843 | /* check if new start address has been latched */ |
844 | tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); | ||
823 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); | 845 | tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); |
824 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); | 846 | base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); |
825 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); | 847 | tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); |
826 | 848 | ||
849 | spin_unlock_irqrestore(&dc->lock, flags); | ||
850 | |||
827 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { | 851 | if (base == bo->paddr + crtc->primary->fb->offsets[0]) { |
828 | spin_lock_irqsave(&drm->event_lock, flags); | 852 | drm_crtc_send_vblank_event(crtc, dc->event); |
829 | drm_send_vblank_event(drm, dc->pipe, dc->event); | 853 | drm_crtc_vblank_put(crtc); |
830 | drm_vblank_put(drm, dc->pipe); | ||
831 | dc->event = NULL; | 854 | dc->event = NULL; |
832 | spin_unlock_irqrestore(&drm->event_lock, flags); | ||
833 | } | 855 | } |
856 | |||
857 | spin_unlock_irqrestore(&drm->event_lock, flags); | ||
834 | } | 858 | } |
835 | 859 | ||
836 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | 860 | void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) |
@@ -843,7 +867,7 @@ void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | |||
843 | 867 | ||
844 | if (dc->event && dc->event->base.file_priv == file) { | 868 | if (dc->event && dc->event->base.file_priv == file) { |
845 | dc->event->base.destroy(&dc->event->base); | 869 | dc->event->base.destroy(&dc->event->base); |
846 | drm_vblank_put(drm, dc->pipe); | 870 | drm_crtc_vblank_put(crtc); |
847 | dc->event = NULL; | 871 | dc->event = NULL; |
848 | } | 872 | } |
849 | 873 | ||
@@ -853,16 +877,16 @@ void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) | |||
853 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | 877 | static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
854 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) | 878 | struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
855 | { | 879 | { |
880 | unsigned int pipe = drm_crtc_index(crtc); | ||
856 | struct tegra_dc *dc = to_tegra_dc(crtc); | 881 | struct tegra_dc *dc = to_tegra_dc(crtc); |
857 | struct drm_device *drm = crtc->dev; | ||
858 | 882 | ||
859 | if (dc->event) | 883 | if (dc->event) |
860 | return -EBUSY; | 884 | return -EBUSY; |
861 | 885 | ||
862 | if (event) { | 886 | if (event) { |
863 | event->pipe = dc->pipe; | 887 | event->pipe = pipe; |
864 | dc->event = event; | 888 | dc->event = event; |
865 | drm_vblank_get(drm, dc->pipe); | 889 | drm_crtc_vblank_get(crtc); |
866 | } | 890 | } |
867 | 891 | ||
868 | tegra_dc_set_base(dc, 0, 0, fb); | 892 | tegra_dc_set_base(dc, 0, 0, fb); |
@@ -1127,7 +1151,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data) | |||
1127 | /* | 1151 | /* |
1128 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); | 1152 | dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); |
1129 | */ | 1153 | */ |
1130 | drm_handle_vblank(dc->base.dev, dc->pipe); | 1154 | drm_crtc_handle_vblank(&dc->base); |
1131 | tegra_dc_finish_page_flip(dc); | 1155 | tegra_dc_finish_page_flip(dc); |
1132 | } | 1156 | } |
1133 | 1157 | ||