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path: root/drivers/gpu/drm/radeon
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-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c35
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c149
-rw-r--r--drivers/gpu/drm/radeon/evergreen_reg.h29
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h31
-rw-r--r--drivers/gpu/drm/radeon/r100.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_acpi.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c7
-rw-r--r--drivers/gpu/drm/radeon/rs600.c7
-rw-r--r--drivers/gpu/drm/radeon/rv770.c7
10 files changed, 249 insertions, 41 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 87631fede1f8..2b97262e3ab1 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1107,9 +1107,40 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1107 return -EINVAL; 1107 return -EINVAL;
1108 } 1108 }
1109 1109
1110 if (tiling_flags & RADEON_TILING_MACRO) 1110 if (tiling_flags & RADEON_TILING_MACRO) {
1111 if (rdev->family >= CHIP_CAYMAN)
1112 tmp = rdev->config.cayman.tile_config;
1113 else
1114 tmp = rdev->config.evergreen.tile_config;
1115
1116 switch ((tmp & 0xf0) >> 4) {
1117 case 0: /* 4 banks */
1118 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1119 break;
1120 case 1: /* 8 banks */
1121 default:
1122 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1123 break;
1124 case 2: /* 16 banks */
1125 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1126 break;
1127 }
1128
1129 switch ((tmp & 0xf000) >> 12) {
1130 case 0: /* 1KB rows */
1131 default:
1132 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB);
1133 break;
1134 case 1: /* 2KB rows */
1135 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB);
1136 break;
1137 case 2: /* 4KB rows */
1138 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB);
1139 break;
1140 }
1141
1111 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1142 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1112 else if (tiling_flags & RADEON_TILING_MICRO) 1143 } else if (tiling_flags & RADEON_TILING_MICRO)
1113 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1144 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1114 1145
1115 switch (radeon_crtc->crtc_id) { 1146 switch (radeon_crtc->crtc_id) {
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 1d603a3335db..5e00d1670aa9 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -82,6 +82,7 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
82{ 82{
83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
84 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); 84 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
85 int i;
85 86
86 /* Lock the graphics update lock */ 87 /* Lock the graphics update lock */
87 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; 88 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
@@ -99,7 +100,11 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
99 (u32)crtc_base); 100 (u32)crtc_base);
100 101
101 /* Wait for update_pending to go high. */ 102 /* Wait for update_pending to go high. */
102 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)); 103 for (i = 0; i < rdev->usec_timeout; i++) {
104 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
105 break;
106 udelay(1);
107 }
103 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 108 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
104 109
105 /* Unlock the lock, so double-buffering can take place inside vblank */ 110 /* Unlock the lock, so double-buffering can take place inside vblank */
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 38e1bda73d33..cd4590aae154 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -38,6 +38,7 @@ struct evergreen_cs_track {
38 u32 group_size; 38 u32 group_size;
39 u32 nbanks; 39 u32 nbanks;
40 u32 npipes; 40 u32 npipes;
41 u32 row_size;
41 /* value we track */ 42 /* value we track */
42 u32 nsamples; 43 u32 nsamples;
43 u32 cb_color_base_last[12]; 44 u32 cb_color_base_last[12];
@@ -77,6 +78,44 @@ struct evergreen_cs_track {
77 struct radeon_bo *db_s_write_bo; 78 struct radeon_bo *db_s_write_bo;
78}; 79};
79 80
81static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
82{
83 if (tiling_flags & RADEON_TILING_MACRO)
84 return ARRAY_2D_TILED_THIN1;
85 else if (tiling_flags & RADEON_TILING_MICRO)
86 return ARRAY_1D_TILED_THIN1;
87 else
88 return ARRAY_LINEAR_GENERAL;
89}
90
91static u32 evergreen_cs_get_num_banks(u32 nbanks)
92{
93 switch (nbanks) {
94 case 2:
95 return ADDR_SURF_2_BANK;
96 case 4:
97 return ADDR_SURF_4_BANK;
98 case 8:
99 default:
100 return ADDR_SURF_8_BANK;
101 case 16:
102 return ADDR_SURF_16_BANK;
103 }
104}
105
106static u32 evergreen_cs_get_tile_split(u32 row_size)
107{
108 switch (row_size) {
109 case 1:
110 default:
111 return ADDR_SURF_TILE_SPLIT_1KB;
112 case 2:
113 return ADDR_SURF_TILE_SPLIT_2KB;
114 case 4:
115 return ADDR_SURF_TILE_SPLIT_4KB;
116 }
117}
118
80static void evergreen_cs_track_init(struct evergreen_cs_track *track) 119static void evergreen_cs_track_init(struct evergreen_cs_track *track)
81{ 120{
82 int i; 121 int i;
@@ -490,12 +529,11 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
490 } 529 }
491 ib[idx] &= ~Z_ARRAY_MODE(0xf); 530 ib[idx] &= ~Z_ARRAY_MODE(0xf);
492 track->db_z_info &= ~Z_ARRAY_MODE(0xf); 531 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
532 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
533 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
493 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 534 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
494 ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1); 535 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
495 track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1); 536 ib[idx] |= DB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
496 } else {
497 ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
498 track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
499 } 537 }
500 } 538 }
501 break; 539 break;
@@ -618,13 +656,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
618 "0x%04X\n", reg); 656 "0x%04X\n", reg);
619 return -EINVAL; 657 return -EINVAL;
620 } 658 }
621 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 659 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
622 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1); 660 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
623 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
624 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
625 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
626 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
627 }
628 } 661 }
629 break; 662 break;
630 case CB_COLOR8_INFO: 663 case CB_COLOR8_INFO:
@@ -640,13 +673,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
640 "0x%04X\n", reg); 673 "0x%04X\n", reg);
641 return -EINVAL; 674 return -EINVAL;
642 } 675 }
643 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 676 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
644 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1); 677 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
645 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
646 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
647 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
648 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
649 }
650 } 678 }
651 break; 679 break;
652 case CB_COLOR0_PITCH: 680 case CB_COLOR0_PITCH:
@@ -701,6 +729,16 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
701 case CB_COLOR9_ATTRIB: 729 case CB_COLOR9_ATTRIB:
702 case CB_COLOR10_ATTRIB: 730 case CB_COLOR10_ATTRIB:
703 case CB_COLOR11_ATTRIB: 731 case CB_COLOR11_ATTRIB:
732 r = evergreen_cs_packet_next_reloc(p, &reloc);
733 if (r) {
734 dev_warn(p->dev, "bad SET_CONTEXT_REG "
735 "0x%04X\n", reg);
736 return -EINVAL;
737 }
738 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
739 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
740 ib[idx] |= CB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
741 }
704 break; 742 break;
705 case CB_COLOR0_DIM: 743 case CB_COLOR0_DIM:
706 case CB_COLOR1_DIM: 744 case CB_COLOR1_DIM:
@@ -1318,10 +1356,14 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
1318 } 1356 }
1319 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1357 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1320 if (!p->keep_tiling_flags) { 1358 if (!p->keep_tiling_flags) {
1321 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1359 ib[idx+1+(i*8)+1] |=
1322 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1); 1360 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1323 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1361 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1324 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1); 1362 ib[idx+1+(i*8)+6] |=
1363 TEX_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
1364 ib[idx+1+(i*8)+7] |=
1365 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1366 }
1325 } 1367 }
1326 texture = reloc->robj; 1368 texture = reloc->robj;
1327 /* tex mip base */ 1369 /* tex mip base */
@@ -1422,6 +1464,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
1422{ 1464{
1423 struct radeon_cs_packet pkt; 1465 struct radeon_cs_packet pkt;
1424 struct evergreen_cs_track *track; 1466 struct evergreen_cs_track *track;
1467 u32 tmp;
1425 int r; 1468 int r;
1426 1469
1427 if (p->track == NULL) { 1470 if (p->track == NULL) {
@@ -1430,9 +1473,63 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
1430 if (track == NULL) 1473 if (track == NULL)
1431 return -ENOMEM; 1474 return -ENOMEM;
1432 evergreen_cs_track_init(track); 1475 evergreen_cs_track_init(track);
1433 track->npipes = p->rdev->config.evergreen.tiling_npipes; 1476 if (p->rdev->family >= CHIP_CAYMAN)
1434 track->nbanks = p->rdev->config.evergreen.tiling_nbanks; 1477 tmp = p->rdev->config.cayman.tile_config;
1435 track->group_size = p->rdev->config.evergreen.tiling_group_size; 1478 else
1479 tmp = p->rdev->config.evergreen.tile_config;
1480
1481 switch (tmp & 0xf) {
1482 case 0:
1483 track->npipes = 1;
1484 break;
1485 case 1:
1486 default:
1487 track->npipes = 2;
1488 break;
1489 case 2:
1490 track->npipes = 4;
1491 break;
1492 case 3:
1493 track->npipes = 8;
1494 break;
1495 }
1496
1497 switch ((tmp & 0xf0) >> 4) {
1498 case 0:
1499 track->nbanks = 4;
1500 break;
1501 case 1:
1502 default:
1503 track->nbanks = 8;
1504 break;
1505 case 2:
1506 track->nbanks = 16;
1507 break;
1508 }
1509
1510 switch ((tmp & 0xf00) >> 8) {
1511 case 0:
1512 track->group_size = 256;
1513 break;
1514 case 1:
1515 default:
1516 track->group_size = 512;
1517 break;
1518 }
1519
1520 switch ((tmp & 0xf000) >> 12) {
1521 case 0:
1522 track->row_size = 1;
1523 break;
1524 case 1:
1525 default:
1526 track->row_size = 2;
1527 break;
1528 case 2:
1529 track->row_size = 4;
1530 break;
1531 }
1532
1436 p->track = track; 1533 p->track = track;
1437 } 1534 }
1438 do { 1535 do {
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index c781c92c3451..7d7f2155e34c 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -42,6 +42,17 @@
42# define EVERGREEN_GRPH_DEPTH_8BPP 0 42# define EVERGREEN_GRPH_DEPTH_8BPP 0
43# define EVERGREEN_GRPH_DEPTH_16BPP 1 43# define EVERGREEN_GRPH_DEPTH_16BPP 1
44# define EVERGREEN_GRPH_DEPTH_32BPP 2 44# define EVERGREEN_GRPH_DEPTH_32BPP 2
45# define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
46# define EVERGREEN_ADDR_SURF_2_BANK 0
47# define EVERGREEN_ADDR_SURF_4_BANK 1
48# define EVERGREEN_ADDR_SURF_8_BANK 2
49# define EVERGREEN_ADDR_SURF_16_BANK 3
50# define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4)
51# define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
52# define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0
53# define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1
54# define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2
55# define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 3
45# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) 56# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)
46/* 8 BPP */ 57/* 8 BPP */
47# define EVERGREEN_GRPH_FORMAT_INDEXED 0 58# define EVERGREEN_GRPH_FORMAT_INDEXED 0
@@ -61,6 +72,24 @@
61# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 72# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
62# define EVERGREEN_GRPH_FORMAT_RGB111110 6 73# define EVERGREEN_GRPH_FORMAT_RGB111110 6
63# define EVERGREEN_GRPH_FORMAT_BGR101111 7 74# define EVERGREEN_GRPH_FORMAT_BGR101111 7
75# define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
76# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0
77# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1
78# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2
79# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 3
80# define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
81# define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0
82# define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1
83# define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2
84# define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 3
85# define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 4
86# define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 5
87# define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 6
88# define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
89# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0
90# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
91# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2
92# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3
64# define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 93# define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
65# define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0 94# define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0
66# define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 95# define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index b937c49054d9..e00039e59a75 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -899,6 +899,10 @@
899#define DB_HTILE_DATA_BASE 0x28014 899#define DB_HTILE_DATA_BASE 0x28014
900#define DB_Z_INFO 0x28040 900#define DB_Z_INFO 0x28040
901# define Z_ARRAY_MODE(x) ((x) << 4) 901# define Z_ARRAY_MODE(x) ((x) << 4)
902# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
903# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
904# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
905# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
902#define DB_STENCIL_INFO 0x28044 906#define DB_STENCIL_INFO 0x28044
903#define DB_Z_READ_BASE 0x28048 907#define DB_Z_READ_BASE 0x28048
904#define DB_STENCIL_READ_BASE 0x2804c 908#define DB_STENCIL_READ_BASE 0x2804c
@@ -951,6 +955,29 @@
951# define CB_SF_EXPORT_FULL 0 955# define CB_SF_EXPORT_FULL 0
952# define CB_SF_EXPORT_NORM 1 956# define CB_SF_EXPORT_NORM 1
953#define CB_COLOR0_ATTRIB 0x28c74 957#define CB_COLOR0_ATTRIB 0x28c74
958# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
959# define ADDR_SURF_TILE_SPLIT_64B 0
960# define ADDR_SURF_TILE_SPLIT_128B 1
961# define ADDR_SURF_TILE_SPLIT_256B 2
962# define ADDR_SURF_TILE_SPLIT_512B 3
963# define ADDR_SURF_TILE_SPLIT_1KB 4
964# define ADDR_SURF_TILE_SPLIT_2KB 5
965# define ADDR_SURF_TILE_SPLIT_4KB 6
966# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
967# define ADDR_SURF_2_BANK 0
968# define ADDR_SURF_4_BANK 1
969# define ADDR_SURF_8_BANK 2
970# define ADDR_SURF_16_BANK 3
971# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
972# define ADDR_SURF_BANK_WIDTH_1 0
973# define ADDR_SURF_BANK_WIDTH_2 1
974# define ADDR_SURF_BANK_WIDTH_4 2
975# define ADDR_SURF_BANK_WIDTH_8 3
976# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
977# define ADDR_SURF_BANK_HEIGHT_1 0
978# define ADDR_SURF_BANK_HEIGHT_2 1
979# define ADDR_SURF_BANK_HEIGHT_4 2
980# define ADDR_SURF_BANK_HEIGHT_8 3
954#define CB_COLOR0_DIM 0x28c78 981#define CB_COLOR0_DIM 0x28c78
955/* only CB0-7 blocks have these regs */ 982/* only CB0-7 blocks have these regs */
956#define CB_COLOR0_CMASK 0x28c7c 983#define CB_COLOR0_CMASK 0x28c7c
@@ -1137,7 +1164,11 @@
1137# define SQ_SEL_1 5 1164# define SQ_SEL_1 5
1138#define SQ_TEX_RESOURCE_WORD5_0 0x30014 1165#define SQ_TEX_RESOURCE_WORD5_0 0x30014
1139#define SQ_TEX_RESOURCE_WORD6_0 0x30018 1166#define SQ_TEX_RESOURCE_WORD6_0 0x30018
1167# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
1140#define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1168#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1169# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
1170# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1171# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
1141 1172
1142#define SQ_VTX_CONSTANT_WORD0_0 0x30000 1173#define SQ_VTX_CONSTANT_WORD0_0 0x30000
1143#define SQ_VTX_CONSTANT_WORD1_0 0x30004 1174#define SQ_VTX_CONSTANT_WORD1_0 0x30004
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index ad158ea49901..bfc08f6320f8 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -187,13 +187,18 @@ u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
187{ 187{
188 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 188 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
189 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 189 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
190 int i;
190 191
191 /* Lock the graphics update lock */ 192 /* Lock the graphics update lock */
192 /* update the scanout addresses */ 193 /* update the scanout addresses */
193 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 194 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
194 195
195 /* Wait for update_pending to go high. */ 196 /* Wait for update_pending to go high. */
196 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)); 197 for (i = 0; i < rdev->usec_timeout; i++) {
198 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
199 break;
200 udelay(1);
201 }
197 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 202 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
198 203
199 /* Unlock the lock, so double-buffering can take place inside vblank */ 204 /* Unlock the lock, so double-buffering can take place inside vblank */
diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c
index 3f6636bb2d7f..3516a6081dcf 100644
--- a/drivers/gpu/drm/radeon/radeon_acpi.c
+++ b/drivers/gpu/drm/radeon/radeon_acpi.c
@@ -35,7 +35,8 @@ static int radeon_atif_call(acpi_handle handle)
35 35
36 /* Fail only if calling the method fails and ATIF is supported */ 36 /* Fail only if calling the method fails and ATIF is supported */
37 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 37 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
38 printk(KERN_DEBUG "failed to evaluate ATIF got %s\n", acpi_format_exception(status)); 38 DRM_DEBUG_DRIVER("failed to evaluate ATIF got %s\n",
39 acpi_format_exception(status));
39 kfree(buffer.pointer); 40 kfree(buffer.pointer);
40 return 1; 41 return 1;
41 } 42 }
@@ -50,13 +51,13 @@ int radeon_acpi_init(struct radeon_device *rdev)
50 acpi_handle handle; 51 acpi_handle handle;
51 int ret; 52 int ret;
52 53
53 /* No need to proceed if we're sure that ATIF is not supported */
54 if (!ASIC_IS_AVIVO(rdev) || !rdev->bios)
55 return 0;
56
57 /* Get the device handle */ 54 /* Get the device handle */
58 handle = DEVICE_ACPI_HANDLE(&rdev->pdev->dev); 55 handle = DEVICE_ACPI_HANDLE(&rdev->pdev->dev);
59 56
57 /* No need to proceed if we're sure that ATIF is not supported */
58 if (!ASIC_IS_AVIVO(rdev) || !rdev->bios || !handle)
59 return 0;
60
60 /* Call the ATIF method */ 61 /* Call the ATIF method */
61 ret = radeon_atif_call(handle); 62 ret = radeon_atif_call(handle);
62 if (ret) 63 if (ret)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 06e413e6a920..4b27efa4405b 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -233,13 +233,12 @@ u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
233 switch (radeon_encoder->encoder_id) { 233 switch (radeon_encoder->encoder_id) {
234 case ENCODER_OBJECT_ID_TRAVIS: 234 case ENCODER_OBJECT_ID_TRAVIS:
235 case ENCODER_OBJECT_ID_NUTMEG: 235 case ENCODER_OBJECT_ID_NUTMEG:
236 return true; 236 return radeon_encoder->encoder_id;
237 default: 237 default:
238 return false; 238 return ENCODER_OBJECT_ID_NONE;
239 } 239 }
240 } 240 }
241 241 return ENCODER_OBJECT_ID_NONE;
242 return false;
243} 242}
244 243
245void radeon_panel_mode_fixup(struct drm_encoder *encoder, 244void radeon_panel_mode_fixup(struct drm_encoder *encoder,
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 481b99e89f65..b1053d640423 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -62,6 +62,7 @@ u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
62{ 62{
63 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 63 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
64 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 64 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
65 int i;
65 66
66 /* Lock the graphics update lock */ 67 /* Lock the graphics update lock */
67 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 68 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
@@ -74,7 +75,11 @@ u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
74 (u32)crtc_base); 75 (u32)crtc_base);
75 76
76 /* Wait for update_pending to go high. */ 77 /* Wait for update_pending to go high. */
77 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)); 78 for (i = 0; i < rdev->usec_timeout; i++) {
79 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
80 break;
81 udelay(1);
82 }
78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 83 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
79 84
80 /* Unlock the lock, so double-buffering can take place inside vblank */ 85 /* Unlock the lock, so double-buffering can take place inside vblank */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index a983f410ab89..23ae1c60ab3d 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -47,6 +47,7 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47{ 47{
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50 int i;
50 51
51 /* Lock the graphics update lock */ 52 /* Lock the graphics update lock */
52 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 53 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
@@ -66,7 +67,11 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
66 (u32)crtc_base); 67 (u32)crtc_base);
67 68
68 /* Wait for update_pending to go high. */ 69 /* Wait for update_pending to go high. */
69 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)); 70 for (i = 0; i < rdev->usec_timeout; i++) {
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
72 break;
73 udelay(1);
74 }
70 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 75 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
71 76
72 /* Unlock the lock, so double-buffering can take place inside vblank */ 77 /* Unlock the lock, so double-buffering can take place inside vblank */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 09:20:32 -0400