diff options
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r300_cmdbuf.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r420.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_cp.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_display.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_encoders.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_kms.c | 6 |
7 files changed, 24 insertions, 14 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index bd75f99bd65e..eaf1f6bc44f1 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -324,13 +324,12 @@ void r300_gpu_init(struct radeon_device *rdev) | |||
324 | uint32_t gb_tile_config, tmp; | 324 | uint32_t gb_tile_config, tmp; |
325 | 325 | ||
326 | r100_hdp_reset(rdev); | 326 | r100_hdp_reset(rdev); |
327 | /* FIXME: rv380 one pipes ? */ | ||
328 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || | 327 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || |
329 | (rdev->family == CHIP_R350)) { | 328 | (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { |
330 | /* r300,r350 */ | 329 | /* r300,r350 */ |
331 | rdev->num_gb_pipes = 2; | 330 | rdev->num_gb_pipes = 2; |
332 | } else { | 331 | } else { |
333 | /* rv350,rv370,rv380,r300 AD */ | 332 | /* rv350,rv370,rv380,r300 AD, r350 AH */ |
334 | rdev->num_gb_pipes = 1; | 333 | rdev->num_gb_pipes = 1; |
335 | } | 334 | } |
336 | rdev->num_z_pipes = 1; | 335 | rdev->num_z_pipes = 1; |
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c index ea46d558e8f3..c5c2742e4140 100644 --- a/drivers/gpu/drm/radeon/r300_cmdbuf.c +++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c | |||
@@ -921,7 +921,7 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, | |||
921 | 921 | ||
922 | ptr_addr = drm_buffer_read_object(cmdbuf->buffer, | 922 | ptr_addr = drm_buffer_read_object(cmdbuf->buffer, |
923 | sizeof(stack_ptr_addr), &stack_ptr_addr); | 923 | sizeof(stack_ptr_addr), &stack_ptr_addr); |
924 | ref_age_base = (u32 *)(unsigned long)*ptr_addr; | 924 | ref_age_base = (u32 *)(unsigned long)get_unaligned(ptr_addr); |
925 | 925 | ||
926 | for (i=0; i < header.scratch.n_bufs; i++) { | 926 | for (i=0; i < header.scratch.n_bufs; i++) { |
927 | buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); | 927 | buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 3dc968c9f5a4..c2bda4ad62e7 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
@@ -59,6 +59,12 @@ void r420_pipes_init(struct radeon_device *rdev) | |||
59 | /* get max number of pipes */ | 59 | /* get max number of pipes */ |
60 | gb_pipe_select = RREG32(0x402C); | 60 | gb_pipe_select = RREG32(0x402C); |
61 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; | 61 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
62 | |||
63 | /* SE chips have 1 pipe */ | ||
64 | if ((rdev->pdev->device == 0x5e4c) || | ||
65 | (rdev->pdev->device == 0x5e4f)) | ||
66 | num_pipes = 1; | ||
67 | |||
62 | rdev->num_gb_pipes = num_pipes; | 68 | rdev->num_gb_pipes = num_pipes; |
63 | tmp = 0; | 69 | tmp = 0; |
64 | switch (num_pipes) { | 70 | switch (num_pipes) { |
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 419630dd2075..2f042a3c0e62 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c | |||
@@ -435,14 +435,19 @@ static void radeon_init_pipes(struct drm_device *dev) | |||
435 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { | 435 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { |
436 | gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); | 436 | gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); |
437 | dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; | 437 | dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
438 | /* SE cards have 1 pipe */ | ||
439 | if ((dev->pdev->device == 0x5e4c) || | ||
440 | (dev->pdev->device == 0x5e4f)) | ||
441 | dev_priv->num_gb_pipes = 1; | ||
438 | } else { | 442 | } else { |
439 | /* R3xx */ | 443 | /* R3xx */ |
440 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 && | 444 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 && |
441 | dev->pdev->device != 0x4144) || | 445 | dev->pdev->device != 0x4144) || |
442 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { | 446 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 && |
447 | dev->pdev->device != 0x4148)) { | ||
443 | dev_priv->num_gb_pipes = 2; | 448 | dev_priv->num_gb_pipes = 2; |
444 | } else { | 449 | } else { |
445 | /* RV3xx/R300 AD */ | 450 | /* RV3xx/R300 AD/R350 AH */ |
446 | dev_priv->num_gb_pipes = 1; | 451 | dev_priv->num_gb_pipes = 1; |
447 | } | 452 | } |
448 | } | 453 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index b8d672828246..bb1c122cad21 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c | |||
@@ -86,12 +86,12 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc) | |||
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); | 86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); | 87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
88 | 88 | ||
89 | WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id); | 89 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007); | 90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
91 | 91 | ||
92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0); | 92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
93 | for (i = 0; i < 256; i++) { | 93 | for (i = 0; i < 256; i++) { |
94 | WREG32(EVERGREEN_DC_LUT_30_COLOR, | 94 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
95 | (radeon_crtc->lut_r[i] << 20) | | 95 | (radeon_crtc->lut_r[i] << 20) | |
96 | (radeon_crtc->lut_g[i] << 10) | | 96 | (radeon_crtc->lut_g[i] << 10) | |
97 | (radeon_crtc->lut_b[i] << 0)); | 97 | (radeon_crtc->lut_b[i] << 0)); |
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 30293bec0801..fed7b8084779 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -1326,7 +1326,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |||
1326 | 1326 | ||
1327 | radeon_encoder->pixel_clock = adjusted_mode->clock; | 1327 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1328 | 1328 | ||
1329 | if (ASIC_IS_AVIVO(rdev)) { | 1329 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
1330 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) | 1330 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
1331 | atombios_yuv_setup(encoder, true); | 1331 | atombios_yuv_setup(encoder, true); |
1332 | else | 1332 | else |
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index d3657dcfdd26..c633319f98ed 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c | |||
@@ -165,7 +165,7 @@ u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) | |||
165 | { | 165 | { |
166 | struct radeon_device *rdev = dev->dev_private; | 166 | struct radeon_device *rdev = dev->dev_private; |
167 | 167 | ||
168 | if (crtc < 0 || crtc > 1) { | 168 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
169 | DRM_ERROR("Invalid crtc %d\n", crtc); | 169 | DRM_ERROR("Invalid crtc %d\n", crtc); |
170 | return -EINVAL; | 170 | return -EINVAL; |
171 | } | 171 | } |
@@ -177,7 +177,7 @@ int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) | |||
177 | { | 177 | { |
178 | struct radeon_device *rdev = dev->dev_private; | 178 | struct radeon_device *rdev = dev->dev_private; |
179 | 179 | ||
180 | if (crtc < 0 || crtc > 1) { | 180 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
181 | DRM_ERROR("Invalid crtc %d\n", crtc); | 181 | DRM_ERROR("Invalid crtc %d\n", crtc); |
182 | return -EINVAL; | 182 | return -EINVAL; |
183 | } | 183 | } |
@@ -191,7 +191,7 @@ void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) | |||
191 | { | 191 | { |
192 | struct radeon_device *rdev = dev->dev_private; | 192 | struct radeon_device *rdev = dev->dev_private; |
193 | 193 | ||
194 | if (crtc < 0 || crtc > 1) { | 194 | if (crtc < 0 || crtc >= rdev->num_crtc) { |
195 | DRM_ERROR("Invalid crtc %d\n", crtc); | 195 | DRM_ERROR("Invalid crtc %d\n", crtc); |
196 | return; | 196 | return; |
197 | } | 197 | } |