6 files changed, 28 insertions, 46 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 8f9e2d31b255..8546e3b333b4 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4999,8 +4999,7 @@ void evergreen_fini(struct radeon_device *rdev)
 
 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
 {
-        u32 link_width_cntl, speed_cntl, mask;
-        int ret;
+        u32 link_width_cntl, speed_cntl;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -5015,11 +5014,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
         if (ASIC_IS_X2(rdev))
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1a08008c978b..b45e64848677 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -4631,8 +4631,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
 {
         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
         u16 link_cntl2;
-        u32 mask;
-        int ret;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -4651,11 +4649,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
         if (rdev->family <= CHIP_R600)
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index c2c59fb1ea01..189973836cff 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -467,23 +467,27 @@ bool radeon_card_posted(struct radeon_device *rdev)
 {
         uint32_t reg;
 
+        /* required for EFI mode on macbook2,1 which uses an r5xx asic */
         if (efi_enabled(EFI_BOOT) &&
-            rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
+            (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
+            (rdev->family < CHIP_R600))
                 return false;
 
+        if (ASIC_IS_NODCE(rdev))
+                goto check_memsize;
+
         /* first check CRTCs */
-        if (ASIC_IS_DCE41(rdev)) {
+        if (ASIC_IS_DCE4(rdev)) {
                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
-                if (reg & EVERGREEN_CRTC_MASTER_EN)
-                        return true;
-        } else if (ASIC_IS_DCE4(rdev)) {
-                reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+                        if (rdev->num_crtc >= 4) {
+                                reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+                                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+                        }
+                        if (rdev->num_crtc >= 6) {
+                                reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+                                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+                        }
                 if (reg & EVERGREEN_CRTC_MASTER_EN)
                         return true;
         } else if (ASIC_IS_AVIVO(rdev)) {
@@ -500,6 +504,7 @@ bool radeon_card_posted(struct radeon_device *rdev)
                 }
         }
 
+check_memsize:
         /* then check MEM_SIZE, in case the crtcs are off */
         if (rdev->family >= CHIP_R600)
                 reg = RREG32(R600_CONFIG_MEMSIZE);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index e38fd559f1ab..eb18bb7af1cc 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -271,8 +271,6 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 {
         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
         struct radeon_unpin_work *work;
-        struct drm_pending_vblank_event *e;
-        struct timeval now;
         unsigned long flags;
         u32 update_pending;
         int vpos, hpos;
@@ -328,14 +326,9 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
         radeon_crtc->unpin_work = NULL;
 
         /* wakeup userspace */
-        if (work->event) {
-                e = work->event;
-                e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-                list_add_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-        }
+        if (work->event)
+                drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
+
         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 
         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 83f612a9500b..08aef24afe40 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -862,10 +862,8 @@ int rv770_uvd_resume(struct radeon_device *rdev)
                 chip_id = 0x0100000b;
                 break;
         case CHIP_SUMO:
-                chip_id = 0x0100000c;
-                break;
         case CHIP_SUMO2:
-                chip_id = 0x0100000d;
+                chip_id = 0x0100000c;
                 break;
         case CHIP_PALM:
                 chip_id = 0x0100000e;
@@ -2113,8 +2111,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
 {
         u32 link_width_cntl, lanes, speed_cntl, tmp;
         u16 link_cntl2;
-        u32 mask;
-        int ret;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -2129,11 +2125,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
         if (ASIC_IS_X2(rdev))
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 5ffade69af25..d1ba9d88f311 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2616,7 +2616,7 @@ static void si_gpu_init(struct radeon_device *rdev)
         default:
                 rdev->config.si.max_shader_engines = 1;
                 rdev->config.si.max_tile_pipes = 4;
-                rdev->config.si.max_cu_per_sh = 2;
+                rdev->config.si.max_cu_per_sh = 5;
                 rdev->config.si.max_sh_per_se = 2;
                 rdev->config.si.max_backends_per_se = 4;
                 rdev->config.si.max_texture_channel_caches = 4;