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Diffstat (limited to 'drivers/gpu/drm/radeon/trinityd.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/trinityd.h | 228 |
1 files changed, 228 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/trinityd.h b/drivers/gpu/drm/radeon/trinityd.h new file mode 100644 index 000000000000..fd32e2771755 --- /dev/null +++ b/drivers/gpu/drm/radeon/trinityd.h | |||
| @@ -0,0 +1,228 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Alex Deucher | ||
| 23 | */ | ||
| 24 | #ifndef _TRINITYD_H_ | ||
| 25 | #define _TRINITYD_H_ | ||
| 26 | |||
| 27 | /* pm registers */ | ||
| 28 | |||
| 29 | /* cg */ | ||
| 30 | #define CG_CGTT_LOCAL_0 0x0 | ||
| 31 | #define CG_CGTT_LOCAL_1 0x1 | ||
| 32 | |||
| 33 | /* smc */ | ||
| 34 | #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 | ||
| 35 | # define STATE_VALID(x) ((x) << 0) | ||
| 36 | # define STATE_VALID_MASK (0xff << 0) | ||
| 37 | # define STATE_VALID_SHIFT 0 | ||
| 38 | # define CLK_DIVIDER(x) ((x) << 8) | ||
| 39 | # define CLK_DIVIDER_MASK (0xff << 8) | ||
| 40 | # define CLK_DIVIDER_SHIFT 8 | ||
| 41 | # define VID(x) ((x) << 16) | ||
| 42 | # define VID_MASK (0xff << 16) | ||
| 43 | # define VID_SHIFT 16 | ||
| 44 | # define LVRT(x) ((x) << 24) | ||
| 45 | # define LVRT_MASK (0xff << 24) | ||
| 46 | # define LVRT_SHIFT 24 | ||
| 47 | #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 | ||
| 48 | # define DS_DIV(x) ((x) << 0) | ||
| 49 | # define DS_DIV_MASK (0xff << 0) | ||
| 50 | # define DS_DIV_SHIFT 0 | ||
| 51 | # define DS_SH_DIV(x) ((x) << 8) | ||
| 52 | # define DS_SH_DIV_MASK (0xff << 8) | ||
| 53 | # define DS_SH_DIV_SHIFT 8 | ||
| 54 | # define DISPLAY_WM(x) ((x) << 16) | ||
| 55 | # define DISPLAY_WM_MASK (0xff << 16) | ||
| 56 | # define DISPLAY_WM_SHIFT 16 | ||
| 57 | # define VCE_WM(x) ((x) << 24) | ||
| 58 | # define VCE_WM_MASK (0xff << 24) | ||
| 59 | # define VCE_WM_SHIFT 24 | ||
| 60 | |||
| 61 | #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c | ||
| 62 | # define GNB_SLOW(x) ((x) << 0) | ||
| 63 | # define GNB_SLOW_MASK (0xff << 0) | ||
| 64 | # define GNB_SLOW_SHIFT 0 | ||
| 65 | # define FORCE_NBPS1(x) ((x) << 8) | ||
| 66 | # define FORCE_NBPS1_MASK (0xff << 8) | ||
| 67 | # define FORCE_NBPS1_SHIFT 8 | ||
| 68 | #define SMU_SCLK_DPM_STATE_0_AT 0x1f010 | ||
| 69 | # define AT(x) ((x) << 0) | ||
| 70 | # define AT_MASK (0xff << 0) | ||
| 71 | # define AT_SHIFT 0 | ||
| 72 | |||
| 73 | #define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014 | ||
| 74 | # define PD_SCLK_DIVIDER(x) ((x) << 16) | ||
| 75 | # define PD_SCLK_DIVIDER_MASK (0xff << 16) | ||
| 76 | # define PD_SCLK_DIVIDER_SHIFT 16 | ||
| 77 | |||
| 78 | #define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020 | ||
| 79 | |||
| 80 | #define SMU_SCLK_DPM_CNTL 0x1f100 | ||
| 81 | # define SCLK_DPM_EN(x) ((x) << 0) | ||
| 82 | # define SCLK_DPM_EN_MASK (0xff << 0) | ||
| 83 | # define SCLK_DPM_EN_SHIFT 0 | ||
| 84 | # define SCLK_DPM_BOOT_STATE(x) ((x) << 16) | ||
| 85 | # define SCLK_DPM_BOOT_STATE_MASK (0xff << 16) | ||
| 86 | # define SCLK_DPM_BOOT_STATE_SHIFT 16 | ||
| 87 | # define VOLTAGE_CHG_EN(x) ((x) << 24) | ||
| 88 | # define VOLTAGE_CHG_EN_MASK (0xff << 24) | ||
| 89 | # define VOLTAGE_CHG_EN_SHIFT 24 | ||
| 90 | |||
| 91 | #define SMU_SCLK_DPM_TT_CNTL 0x1f108 | ||
| 92 | # define SCLK_TT_EN(x) ((x) << 0) | ||
| 93 | # define SCLK_TT_EN_MASK (0xff << 0) | ||
| 94 | # define SCLK_TT_EN_SHIFT 0 | ||
| 95 | #define SMU_SCLK_DPM_TTT 0x1f10c | ||
| 96 | # define LT(x) ((x) << 0) | ||
| 97 | # define LT_MASK (0xffff << 0) | ||
| 98 | # define LT_SHIFT 0 | ||
| 99 | # define HT(x) ((x) << 16) | ||
| 100 | # define HT_MASK (0xffff << 16) | ||
| 101 | # define HT_SHIFT 16 | ||
| 102 | |||
| 103 | #define SMU_UVD_DPM_STATES 0x1f1a0 | ||
| 104 | #define SMU_UVD_DPM_CNTL 0x1f1a4 | ||
| 105 | |||
| 106 | #define SMU_S_PG_CNTL 0x1f118 | ||
| 107 | # define DS_PG_EN(x) ((x) << 16) | ||
| 108 | # define DS_PG_EN_MASK (0xff << 16) | ||
| 109 | # define DS_PG_EN_SHIFT 16 | ||
| 110 | |||
| 111 | #define GFX_POWER_GATING_CNTL 0x1f38c | ||
| 112 | # define PDS_DIV(x) ((x) << 0) | ||
| 113 | # define PDS_DIV_MASK (0xff << 0) | ||
| 114 | # define PDS_DIV_SHIFT 0 | ||
| 115 | # define SSSD(x) ((x) << 8) | ||
| 116 | # define SSSD_MASK (0xff << 8) | ||
| 117 | # define SSSD_SHIFT 8 | ||
| 118 | |||
| 119 | #define PM_CONFIG 0x1f428 | ||
| 120 | # define SVI_Mode (1 << 29) | ||
| 121 | |||
| 122 | #define PM_I_CNTL_1 0x1f464 | ||
| 123 | # define SCLK_DPM(x) ((x) << 0) | ||
| 124 | # define SCLK_DPM_MASK (0xff << 0) | ||
| 125 | # define SCLK_DPM_SHIFT 0 | ||
| 126 | # define DS_PG_CNTL(x) ((x) << 16) | ||
| 127 | # define DS_PG_CNTL_MASK (0xff << 16) | ||
| 128 | # define DS_PG_CNTL_SHIFT 16 | ||
| 129 | #define PM_TP 0x1f468 | ||
| 130 | |||
| 131 | #define NB_PSTATE_CONFIG 0x1f5f8 | ||
| 132 | # define Dpm0PgNbPsLo(x) ((x) << 0) | ||
| 133 | # define Dpm0PgNbPsLo_MASK (3 << 0) | ||
| 134 | # define Dpm0PgNbPsLo_SHIFT 0 | ||
| 135 | # define Dpm0PgNbPsHi(x) ((x) << 2) | ||
| 136 | # define Dpm0PgNbPsHi_MASK (3 << 2) | ||
| 137 | # define Dpm0PgNbPsHi_SHIFT 2 | ||
| 138 | # define DpmXNbPsLo(x) ((x) << 4) | ||
| 139 | # define DpmXNbPsLo_MASK (3 << 4) | ||
| 140 | # define DpmXNbPsLo_SHIFT 4 | ||
| 141 | # define DpmXNbPsHi(x) ((x) << 6) | ||
| 142 | # define DpmXNbPsHi_MASK (3 << 6) | ||
| 143 | # define DpmXNbPsHi_SHIFT 6 | ||
| 144 | |||
| 145 | #define DC_CAC_VALUE 0x1f908 | ||
| 146 | |||
| 147 | #define GPU_CAC_AVRG_CNTL 0x1f920 | ||
| 148 | # define WINDOW_SIZE(x) ((x) << 0) | ||
| 149 | # define WINDOW_SIZE_MASK (0xff << 0) | ||
| 150 | # define WINDOW_SIZE_SHIFT 0 | ||
| 151 | |||
| 152 | #define CC_SMU_MISC_FUSES 0xe0001004 | ||
| 153 | # define MinSClkDid(x) ((x) << 2) | ||
| 154 | # define MinSClkDid_MASK (0x7f << 2) | ||
| 155 | # define MinSClkDid_SHIFT 2 | ||
| 156 | |||
| 157 | #define CC_SMU_TST_EFUSE1_MISC 0xe000101c | ||
| 158 | # define RB_BACKEND_DISABLE(x) ((x) << 16) | ||
| 159 | # define RB_BACKEND_DISABLE_MASK (3 << 16) | ||
| 160 | # define RB_BACKEND_DISABLE_SHIFT 16 | ||
| 161 | |||
| 162 | #define SMU_SCRATCH_A 0xe0003024 | ||
| 163 | |||
| 164 | #define SMU_SCRATCH0 0xe0003040 | ||
| 165 | |||
| 166 | /* mmio */ | ||
| 167 | #define SMC_INT_REQ 0x220 | ||
| 168 | |||
| 169 | #define SMC_MESSAGE_0 0x22c | ||
| 170 | #define SMC_RESP_0 0x230 | ||
| 171 | |||
| 172 | #define GENERAL_PWRMGT 0x670 | ||
| 173 | # define GLOBAL_PWRMGT_EN (1 << 0) | ||
| 174 | |||
| 175 | #define SCLK_PWRMGT_CNTL 0x678 | ||
| 176 | # define DYN_PWR_DOWN_EN (1 << 2) | ||
| 177 | # define RESET_BUSY_CNT (1 << 4) | ||
| 178 | # define RESET_SCLK_CNT (1 << 5) | ||
| 179 | # define DYN_GFX_CLK_OFF_EN (1 << 7) | ||
| 180 | # define GFX_CLK_FORCE_ON (1 << 8) | ||
| 181 | # define DYNAMIC_PM_EN (1 << 21) | ||
| 182 | |||
| 183 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x684 | ||
| 184 | # define TARGET_STATE(x) ((x) << 0) | ||
| 185 | # define TARGET_STATE_MASK (0xf << 0) | ||
| 186 | # define TARGET_STATE_SHIFT 0 | ||
| 187 | # define CURRENT_STATE(x) ((x) << 4) | ||
| 188 | # define CURRENT_STATE_MASK (0xf << 4) | ||
| 189 | # define CURRENT_STATE_SHIFT 4 | ||
| 190 | |||
| 191 | #define CG_GIPOTS 0x6d8 | ||
| 192 | # define CG_GIPOT(x) ((x) << 16) | ||
| 193 | # define CG_GIPOT_MASK (0xffff << 16) | ||
| 194 | # define CG_GIPOT_SHIFT 16 | ||
| 195 | |||
| 196 | #define CG_PG_CTRL 0x6e0 | ||
| 197 | # define SP(x) ((x) << 0) | ||
| 198 | # define SP_MASK (0xffff << 0) | ||
| 199 | # define SP_SHIFT 0 | ||
| 200 | # define SU(x) ((x) << 16) | ||
| 201 | # define SU_MASK (0xffff << 16) | ||
| 202 | # define SU_SHIFT 16 | ||
| 203 | |||
| 204 | #define CG_MISC_REG 0x708 | ||
| 205 | |||
| 206 | #define CG_THERMAL_INT_CTRL 0x738 | ||
| 207 | # define DIG_THERM_INTH(x) ((x) << 0) | ||
| 208 | # define DIG_THERM_INTH_MASK (0xff << 0) | ||
| 209 | # define DIG_THERM_INTH_SHIFT 0 | ||
| 210 | # define DIG_THERM_INTL(x) ((x) << 8) | ||
| 211 | # define DIG_THERM_INTL_MASK (0xff << 8) | ||
| 212 | # define DIG_THERM_INTL_SHIFT 8 | ||
| 213 | # define THERM_INTH_MASK (1 << 24) | ||
| 214 | # define THERM_INTL_MASK (1 << 25) | ||
| 215 | |||
| 216 | #define CG_CG_VOLTAGE_CNTL 0x770 | ||
| 217 | # define EN (1 << 9) | ||
| 218 | |||
| 219 | #define HW_REV 0x5564 | ||
| 220 | # define ATI_REV_ID_MASK (0xf << 28) | ||
| 221 | # define ATI_REV_ID_SHIFT 28 | ||
| 222 | /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ | ||
| 223 | |||
| 224 | #define CGTS_SM_CTRL_REG 0x9150 | ||
| 225 | |||
| 226 | #define GB_ADDR_CONFIG 0x98f8 | ||
| 227 | |||
| 228 | #endif | ||