diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index cf06dcc9ba96..4c6ff1c8b5ed 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
| @@ -52,6 +52,8 @@ | |||
| 52 | 52 | ||
| 53 | #define DMIF_ADDR_CONFIG 0xBD4 | 53 | #define DMIF_ADDR_CONFIG 0xBD4 |
| 54 | 54 | ||
| 55 | #define SRBM_STATUS 0xE50 | ||
| 56 | |||
| 55 | #define CC_SYS_RB_BACKEND_DISABLE 0xe80 | 57 | #define CC_SYS_RB_BACKEND_DISABLE 0xe80 |
| 56 | #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 | 58 | #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 |
| 57 | 59 | ||
| @@ -102,6 +104,74 @@ | |||
| 102 | #define GRBM_CNTL 0x8000 | 104 | #define GRBM_CNTL 0x8000 |
| 103 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | 105 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 104 | 106 | ||
| 107 | #define GRBM_STATUS2 0x8008 | ||
| 108 | #define RLC_RQ_PENDING (1 << 0) | ||
| 109 | #define RLC_BUSY (1 << 8) | ||
| 110 | #define TC_BUSY (1 << 9) | ||
| 111 | |||
| 112 | #define GRBM_STATUS 0x8010 | ||
| 113 | #define CMDFIFO_AVAIL_MASK 0x0000000F | ||
| 114 | #define RING2_RQ_PENDING (1 << 4) | ||
| 115 | #define SRBM_RQ_PENDING (1 << 5) | ||
| 116 | #define RING1_RQ_PENDING (1 << 6) | ||
| 117 | #define CF_RQ_PENDING (1 << 7) | ||
| 118 | #define PF_RQ_PENDING (1 << 8) | ||
| 119 | #define GDS_DMA_RQ_PENDING (1 << 9) | ||
| 120 | #define GRBM_EE_BUSY (1 << 10) | ||
| 121 | #define DB_CLEAN (1 << 12) | ||
| 122 | #define CB_CLEAN (1 << 13) | ||
| 123 | #define TA_BUSY (1 << 14) | ||
| 124 | #define GDS_BUSY (1 << 15) | ||
| 125 | #define VGT_BUSY (1 << 17) | ||
| 126 | #define IA_BUSY_NO_DMA (1 << 18) | ||
| 127 | #define IA_BUSY (1 << 19) | ||
| 128 | #define SX_BUSY (1 << 20) | ||
| 129 | #define SPI_BUSY (1 << 22) | ||
| 130 | #define BCI_BUSY (1 << 23) | ||
| 131 | #define SC_BUSY (1 << 24) | ||
| 132 | #define PA_BUSY (1 << 25) | ||
| 133 | #define DB_BUSY (1 << 26) | ||
| 134 | #define CP_COHERENCY_BUSY (1 << 28) | ||
| 135 | #define CP_BUSY (1 << 29) | ||
| 136 | #define CB_BUSY (1 << 30) | ||
| 137 | #define GUI_ACTIVE (1 << 31) | ||
| 138 | #define GRBM_STATUS_SE0 0x8014 | ||
| 139 | #define GRBM_STATUS_SE1 0x8018 | ||
| 140 | #define SE_DB_CLEAN (1 << 1) | ||
| 141 | #define SE_CB_CLEAN (1 << 2) | ||
| 142 | #define SE_BCI_BUSY (1 << 22) | ||
| 143 | #define SE_VGT_BUSY (1 << 23) | ||
| 144 | #define SE_PA_BUSY (1 << 24) | ||
| 145 | #define SE_TA_BUSY (1 << 25) | ||
| 146 | #define SE_SX_BUSY (1 << 26) | ||
| 147 | #define SE_SPI_BUSY (1 << 27) | ||
| 148 | #define SE_SC_BUSY (1 << 29) | ||
| 149 | #define SE_DB_BUSY (1 << 30) | ||
| 150 | #define SE_CB_BUSY (1 << 31) | ||
| 151 | |||
| 152 | #define GRBM_SOFT_RESET 0x8020 | ||
| 153 | #define SOFT_RESET_CP (1 << 0) | ||
| 154 | #define SOFT_RESET_CB (1 << 1) | ||
| 155 | #define SOFT_RESET_RLC (1 << 2) | ||
| 156 | #define SOFT_RESET_DB (1 << 3) | ||
| 157 | #define SOFT_RESET_GDS (1 << 4) | ||
| 158 | #define SOFT_RESET_PA (1 << 5) | ||
| 159 | #define SOFT_RESET_SC (1 << 6) | ||
| 160 | #define SOFT_RESET_BCI (1 << 7) | ||
| 161 | #define SOFT_RESET_SPI (1 << 8) | ||
| 162 | #define SOFT_RESET_SX (1 << 10) | ||
| 163 | #define SOFT_RESET_TC (1 << 11) | ||
| 164 | #define SOFT_RESET_TA (1 << 12) | ||
| 165 | #define SOFT_RESET_VGT (1 << 14) | ||
| 166 | #define SOFT_RESET_IA (1 << 15) | ||
| 167 | |||
| 168 | #define CP_ME_CNTL 0x86D8 | ||
| 169 | #define CP_CE_HALT (1 << 24) | ||
| 170 | #define CP_PFP_HALT (1 << 26) | ||
| 171 | #define CP_ME_HALT (1 << 28) | ||
| 172 | |||
| 173 | #define CP_RB0_RPTR 0x8700 | ||
| 174 | |||
| 105 | #define CP_QUEUE_THRESHOLDS 0x8760 | 175 | #define CP_QUEUE_THRESHOLDS 0x8760 |
| 106 | #define ROQ_IB1_START(x) ((x) << 0) | 176 | #define ROQ_IB1_START(x) ((x) << 0) |
| 107 | #define ROQ_IB2_START(x) ((x) << 8) | 177 | #define ROQ_IB2_START(x) ((x) << 8) |