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path: root/drivers/gpu/drm/radeon/si.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index c354c1094967..d4652af425b8 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -85,6 +85,9 @@ extern void si_dma_vm_set_page(struct radeon_device *rdev,
85 uint32_t incr, uint32_t flags); 85 uint32_t incr, uint32_t flags);
86static void si_enable_gui_idle_interrupt(struct radeon_device *rdev, 86static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
87 bool enable); 87 bool enable);
88static void si_fini_pg(struct radeon_device *rdev);
89static void si_fini_cg(struct radeon_device *rdev);
90static void si_rlc_stop(struct radeon_device *rdev);
88 91
89static const u32 verde_rlc_save_restore_register_list[] = 92static const u32 verde_rlc_save_restore_register_list[] =
90{ 93{
@@ -3608,6 +3611,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3608 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3611 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3609 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3612 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3610 3613
3614 /* disable PG/CG */
3615 si_fini_pg(rdev);
3616 si_fini_cg(rdev);
3617
3618 /* stop the rlc */
3619 si_rlc_stop(rdev);
3620
3611 /* Disable CP parsing/prefetching */ 3621 /* Disable CP parsing/prefetching */
3612 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 3622 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3613 3623