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path: root/drivers/gpu/drm/radeon/si.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c35
1 files changed, 31 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index c053f8193771..0139e227e3c7 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device *rdev)
1639 /* XXX what about 12? */ 1639 /* XXX what about 12? */
1640 rdev->config.si.tile_config |= (3 << 0); 1640 rdev->config.si.tile_config |= (3 << 0);
1641 break; 1641 break;
1642 } 1642 }
1643 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1643 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1644 rdev->config.si.tile_config |= 1 << 4; 1644 case 0: /* four banks */
1645 else
1646 rdev->config.si.tile_config |= 0 << 4; 1645 rdev->config.si.tile_config |= 0 << 4;
1646 break;
1647 case 1: /* eight banks */
1648 rdev->config.si.tile_config |= 1 << 4;
1649 break;
1650 case 2: /* sixteen banks */
1651 default:
1652 rdev->config.si.tile_config |= 2 << 4;
1653 break;
1654 }
1647 rdev->config.si.tile_config |= 1655 rdev->config.si.tile_config |=
1648 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1656 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1649 rdev->config.si.tile_config |= 1657 rdev->config.si.tile_config |=
@@ -3960,3 +3968,22 @@ void si_fini(struct radeon_device *rdev)
3960 rdev->bios = NULL; 3968 rdev->bios = NULL;
3961} 3969}
3962 3970
3971/**
3972 * si_get_gpu_clock - return GPU clock counter snapshot
3973 *
3974 * @rdev: radeon_device pointer
3975 *
3976 * Fetches a GPU clock counter snapshot (SI).
3977 * Returns the 64 bit clock counter snapshot.
3978 */
3979uint64_t si_get_gpu_clock(struct radeon_device *rdev)
3980{
3981 uint64_t clock;
3982
3983 mutex_lock(&rdev->gpu_clock_mutex);
3984 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3985 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
3986 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3987 mutex_unlock(&rdev->gpu_clock_mutex);
3988 return clock;
3989}