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-rw-r--r--drivers/gpu/drm/radeon/rv770_smc.h209
1 files changed, 209 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv770_smc.h b/drivers/gpu/drm/radeon/rv770_smc.h
new file mode 100644
index 000000000000..f78d92a4b325
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv770_smc.h
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1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __RV770_SMC_H__
24#define __RV770_SMC_H__
25
26#include "ppsmc.h"
27
28#pragma pack(push, 1)
29
30#define RV770_SMC_TABLE_ADDRESS 0xB000
31
32#define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3
33
34struct RV770_SMC_SCLK_VALUE
35{
36 uint32_t vCG_SPLL_FUNC_CNTL;
37 uint32_t vCG_SPLL_FUNC_CNTL_2;
38 uint32_t vCG_SPLL_FUNC_CNTL_3;
39 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
40 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
41 uint32_t sclk_value;
42};
43
44typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE;
45
46struct RV770_SMC_MCLK_VALUE
47{
48 uint32_t vMPLL_AD_FUNC_CNTL;
49 uint32_t vMPLL_AD_FUNC_CNTL_2;
50 uint32_t vMPLL_DQ_FUNC_CNTL;
51 uint32_t vMPLL_DQ_FUNC_CNTL_2;
52 uint32_t vMCLK_PWRMGT_CNTL;
53 uint32_t vDLL_CNTL;
54 uint32_t vMPLL_SS;
55 uint32_t vMPLL_SS2;
56 uint32_t mclk_value;
57};
58
59typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE;
60
61
62struct RV730_SMC_MCLK_VALUE
63{
64 uint32_t vMCLK_PWRMGT_CNTL;
65 uint32_t vDLL_CNTL;
66 uint32_t vMPLL_FUNC_CNTL;
67 uint32_t vMPLL_FUNC_CNTL2;
68 uint32_t vMPLL_FUNC_CNTL3;
69 uint32_t vMPLL_SS;
70 uint32_t vMPLL_SS2;
71 uint32_t mclk_value;
72};
73
74typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE;
75
76struct RV770_SMC_VOLTAGE_VALUE
77{
78 uint16_t value;
79 uint8_t index;
80 uint8_t padding;
81};
82
83typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE;
84
85union RV7XX_SMC_MCLK_VALUE
86{
87 RV770_SMC_MCLK_VALUE mclk770;
88 RV730_SMC_MCLK_VALUE mclk730;
89};
90
91typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE;
92
93struct RV770_SMC_HW_PERFORMANCE_LEVEL
94{
95 uint8_t arbValue;
96 union{
97 uint8_t seqValue;
98 uint8_t ACIndex;
99 };
100 uint8_t displayWatermark;
101 uint8_t gen2PCIE;
102 uint8_t gen2XSP;
103 uint8_t backbias;
104 uint8_t strobeMode;
105 uint8_t mcFlags;
106 uint32_t aT;
107 uint32_t bSP;
108 RV770_SMC_SCLK_VALUE sclk;
109 RV7XX_SMC_MCLK_VALUE mclk;
110 RV770_SMC_VOLTAGE_VALUE vddc;
111 RV770_SMC_VOLTAGE_VALUE mvdd;
112 RV770_SMC_VOLTAGE_VALUE vddci;
113 uint8_t reserved1;
114 uint8_t reserved2;
115 uint8_t stateFlags;
116 uint8_t padding;
117};
118
119#define SMC_STROBE_RATIO 0x0F
120#define SMC_STROBE_ENABLE 0x10
121
122#define SMC_MC_EDC_RD_FLAG 0x01
123#define SMC_MC_EDC_WR_FLAG 0x02
124#define SMC_MC_RTT_ENABLE 0x04
125#define SMC_MC_STUTTER_EN 0x08
126
127typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL;
128
129struct RV770_SMC_SWSTATE
130{
131 uint8_t flags;
132 uint8_t padding1;
133 uint8_t padding2;
134 uint8_t padding3;
135 RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
136};
137
138typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE;
139
140#define RV770_SMC_VOLTAGEMASK_VDDC 0
141#define RV770_SMC_VOLTAGEMASK_MVDD 1
142#define RV770_SMC_VOLTAGEMASK_VDDCI 2
143#define RV770_SMC_VOLTAGEMASK_MAX 4
144
145struct RV770_SMC_VOLTAGEMASKTABLE
146{
147 uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX];
148 uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];
149};
150
151typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE;
152
153#define MAX_NO_VREG_STEPS 32
154
155struct RV770_SMC_STATETABLE
156{
157 uint8_t thermalProtectType;
158 uint8_t systemFlags;
159 uint8_t maxVDDCIndexInPPTable;
160 uint8_t extraFlags;
161 uint8_t highSMIO[MAX_NO_VREG_STEPS];
162 uint32_t lowSMIO[MAX_NO_VREG_STEPS];
163 RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable;
164 RV770_SMC_SWSTATE initialState;
165 RV770_SMC_SWSTATE ACPIState;
166 RV770_SMC_SWSTATE driverState;
167 RV770_SMC_SWSTATE ULVState;
168};
169
170typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE;
171
172#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
173
174#pragma pack(pop)
175
176#define RV770_SMC_SOFT_REGISTERS_START 0x104
177
178#define RV770_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
179#define RV770_SMC_SOFT_REGISTER_baby_step_timer 0x8
180#define RV770_SMC_SOFT_REGISTER_delay_bbias 0xC
181#define RV770_SMC_SOFT_REGISTER_delay_vreg 0x10
182#define RV770_SMC_SOFT_REGISTER_delay_acpi 0x2C
183#define RV770_SMC_SOFT_REGISTER_seq_index 0x64
184#define RV770_SMC_SOFT_REGISTER_mvdd_chg_time 0x68
185#define RV770_SMC_SOFT_REGISTER_mclk_switch_lim 0x78
186#define RV770_SMC_SOFT_REGISTER_mc_block_delay 0x90
187#define RV770_SMC_SOFT_REGISTER_uvd_enabled 0x9C
188#define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0
189
190int rv770_set_smc_sram_address(struct radeon_device *rdev,
191 u16 smc_address, u16 limit);
192int rv770_copy_bytes_to_smc(struct radeon_device *rdev,
193 u16 smc_start_address, const u8 *src,
194 u16 byte_count, u16 limit);
195void rv770_start_smc(struct radeon_device *rdev);
196void rv770_reset_smc(struct radeon_device *rdev);
197void rv770_stop_smc_clock(struct radeon_device *rdev);
198void rv770_start_smc_clock(struct radeon_device *rdev);
199bool rv770_is_smc_running(struct radeon_device *rdev);
200PPSMC_Result rv770_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
201PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev);
202int rv770_read_smc_sram_dword(struct radeon_device *rdev,
203 u16 smc_address, u32 *value, u16 limit);
204int rv770_write_smc_sram_dword(struct radeon_device *rdev,
205 u16 smc_address, u32 value, u16 limit);
206int rv770_load_smc_ucode(struct radeon_device *rdev,
207 u16 limit);
208
209#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 04:22:38 -0500