1 files changed, 42 insertions, 17 deletions

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 595ac638039d..b0efd0ddae7a 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -529,11 +529,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
         if (rdev->family == CHIP_RV770)
                 gb_tiling_config |= BANK_TILING(1);
         else
-                gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
+                gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 
         gb_tiling_config |= GROUP_SIZE(0);
 
-        if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
+        if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
                 gb_tiling_config |= ROW_TILING(3);
                 gb_tiling_config |= SAMPLE_SPLIT(3);
         } else {
@@ -579,14 +579,14 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
         /* set HW defaults for 3D engine */
         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
-                                                ROQ_IB2_START(0x2b)));
+                                     ROQ_IB2_START(0x2b)));
 
         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 
         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
-                                        SYNC_GRADIENT |
-                                        SYNC_WALKER |
-                                        SYNC_ALIGNER));
+                             SYNC_GRADIENT |
+                             SYNC_WALKER |
+                             SYNC_ALIGNER));
 
         sx_debug_1 = RREG32(SX_DEBUG_1);
         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
@@ -598,9 +598,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 
         WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
-                                          GS_FLUSH_CTL(4) |
-                                          ACK_FLUSH_CTL(3) |
-                                          SYNC_FLUSH_CTL));
+                               GS_FLUSH_CTL(4) |
+                               ACK_FLUSH_CTL(3) |
+                               SYNC_FLUSH_CTL));
 
         if (rdev->family == CHIP_RV770)
                 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
@@ -611,12 +611,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
-                                                   POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
-                                                   SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
+                                        POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
+                                        SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 
         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
-                                                 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
-                                                 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
+                                 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
+                                 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 
         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 
@@ -774,14 +774,36 @@ int rv770_mc_init(struct radeon_device *rdev)
 {
         fixed20_12 a;
         u32 tmp;
+        int chansize, numchan;
         int r;
 
         /* Get VRAM informations */
-        /* FIXME: Don't know how to determine vram width, need to check
-         * vram_width usage
-         */
-        rdev->mc.vram_width = 128;
         rdev->mc.vram_is_ddr = true;
+        tmp = RREG32(MC_ARB_RAMCFG);
+        if (tmp & CHANSIZE_OVERRIDE) {
+                chansize = 16;
+        } else if (tmp & CHANSIZE_MASK) {
+                chansize = 64;
+        } else {
+                chansize = 32;
+        }
+        tmp = RREG32(MC_SHARED_CHMAP);
+        switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+        case 0:
+        default:
+                numchan = 1;
+                break;
+        case 1:
+                numchan = 2;
+                break;
+        case 2:
+                numchan = 4;
+                break;
+        case 3:
+                numchan = 8;
+                break;
+        }
+        rdev->mc.vram_width = numchan * chansize;
         /* Could aper size report 0 ? */
         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
@@ -961,10 +983,13 @@ int rv770_init(struct radeon_device *rdev)
         r600_scratch_init(rdev);
         /* Initialize surface registers */
         radeon_surface_init(rdev);
+        /* Initialize clocks */
         radeon_get_clock_info(rdev->ddev);
         r = radeon_clocks_init(rdev);
         if (r)
                 return r;
+        /* Initialize power management */
+        radeon_pm_init(rdev);
         /* Fence driver */
         r = radeon_fence_driver_init(rdev);
         if (r)