diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/rv515d.h')
-rw-r--r-- | drivers/gpu/drm/radeon/rv515d.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h index fc216e49384d..590309a710b1 100644 --- a/drivers/gpu/drm/radeon/rv515d.h +++ b/drivers/gpu/drm/radeon/rv515d.h | |||
@@ -217,6 +217,52 @@ | |||
217 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | 217 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
218 | 218 | ||
219 | /* Registers */ | 219 | /* Registers */ |
220 | #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 | ||
221 | #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) | ||
222 | #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) | ||
223 | #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE | ||
224 | #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) | ||
225 | #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) | ||
226 | #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD | ||
227 | #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) | ||
228 | #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) | ||
229 | #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB | ||
230 | #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) | ||
231 | #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) | ||
232 | #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 | ||
233 | #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) | ||
234 | #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) | ||
235 | #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF | ||
236 | #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) | ||
237 | #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) | ||
238 | #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF | ||
239 | #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) | ||
240 | #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) | ||
241 | #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF | ||
242 | #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) | ||
243 | #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) | ||
244 | #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F | ||
245 | #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) | ||
246 | #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) | ||
247 | #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF | ||
248 | #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) | ||
249 | #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) | ||
250 | #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF | ||
251 | #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) | ||
252 | #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) | ||
253 | #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF | ||
254 | #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) | ||
255 | #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) | ||
256 | #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF | ||
257 | #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) | ||
258 | #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) | ||
259 | #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF | ||
260 | #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) | ||
261 | #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) | ||
262 | #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF | ||
263 | #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) | ||
264 | #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) | ||
265 | #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF | ||
220 | #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 | 266 | #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 |
221 | #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) | 267 | #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) |
222 | #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) | 268 | #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) |