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path: root/drivers/gpu/drm/radeon/rs690.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/rs690.c')
-rw-r--r--drivers/gpu/drm/radeon/rs690.c44
1 files changed, 23 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index ce4ecbe10816..3e3f75718be3 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -154,13 +154,13 @@ void rs690_mc_init(struct radeon_device *rdev)
154 rdev->mc.vram_width = 128; 154 rdev->mc.vram_width = 128;
155 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 155 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
156 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 156 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
157 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
158 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16; 161 base = G_000100_MC_FB_START(base) << 16;
162 rs690_pm_info(rdev);
163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
163 rs690_pm_info(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base); 164 radeon_vram_location(rdev, &rdev->mc, base);
165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
166 radeon_gtt_location(rdev, &rdev->mc); 166 radeon_gtt_location(rdev, &rdev->mc);
@@ -398,7 +398,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
398 struct drm_display_mode *mode1 = NULL; 398 struct drm_display_mode *mode1 = NULL;
399 struct rs690_watermark wm0; 399 struct rs690_watermark wm0;
400 struct rs690_watermark wm1; 400 struct rs690_watermark wm1;
401 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; 401 u32 tmp;
402 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
403 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
402 fixed20_12 priority_mark02, priority_mark12, fill_rate; 404 fixed20_12 priority_mark02, priority_mark12, fill_rate;
403 fixed20_12 a, b; 405 fixed20_12 a, b;
404 406
@@ -495,10 +497,6 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
495 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 497 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
496 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 498 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
497 } 499 }
498 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
499 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
500 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
501 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
502 } else if (mode0) { 500 } else if (mode0) {
503 if (dfixed_trunc(wm0.dbpp) > 64) 501 if (dfixed_trunc(wm0.dbpp) > 64)
504 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 502 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
@@ -528,13 +526,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
528 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 526 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
529 if (rdev->disp_priority == 2) 527 if (rdev->disp_priority == 2)
530 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 528 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
531 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 529 } else if (mode1) {
532 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
533 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
534 S_006D48_D2MODE_PRIORITY_A_OFF(1));
535 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
536 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
537 } else {
538 if (dfixed_trunc(wm1.dbpp) > 64) 530 if (dfixed_trunc(wm1.dbpp) > 64)
539 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 531 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
540 else 532 else
@@ -563,13 +555,12 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
563 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 555 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
564 if (rdev->disp_priority == 2) 556 if (rdev->disp_priority == 2)
565 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 557 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
567 S_006548_D1MODE_PRIORITY_A_OFF(1));
568 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
569 S_00654C_D1MODE_PRIORITY_B_OFF(1));
570 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
571 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
572 } 558 }
559
560 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
561 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
562 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
563 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
573} 564}
574 565
575uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 566uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -641,6 +632,13 @@ static int rs690_startup(struct radeon_device *rdev)
641 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 632 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
642 return r; 633 return r;
643 } 634 }
635
636 r = r600_audio_init(rdev);
637 if (r) {
638 dev_err(rdev->dev, "failed initializing audio\n");
639 return r;
640 }
641
644 return 0; 642 return 0;
645} 643}
646 644
@@ -667,6 +665,7 @@ int rs690_resume(struct radeon_device *rdev)
667 665
668int rs690_suspend(struct radeon_device *rdev) 666int rs690_suspend(struct radeon_device *rdev)
669{ 667{
668 r600_audio_fini(rdev);
670 r100_cp_disable(rdev); 669 r100_cp_disable(rdev);
671 r100_wb_disable(rdev); 670 r100_wb_disable(rdev);
672 rs600_irq_disable(rdev); 671 rs600_irq_disable(rdev);
@@ -676,6 +675,7 @@ int rs690_suspend(struct radeon_device *rdev)
676 675
677void rs690_fini(struct radeon_device *rdev) 676void rs690_fini(struct radeon_device *rdev)
678{ 677{
678 r600_audio_fini(rdev);
679 r100_cp_fini(rdev); 679 r100_cp_fini(rdev);
680 r100_wb_fini(rdev); 680 r100_wb_fini(rdev);
681 r100_ib_fini(rdev); 681 r100_ib_fini(rdev);
@@ -699,6 +699,8 @@ int rs690_init(struct radeon_device *rdev)
699 radeon_scratch_init(rdev); 699 radeon_scratch_init(rdev);
700 /* Initialize surface registers */ 700 /* Initialize surface registers */
701 radeon_surface_init(rdev); 701 radeon_surface_init(rdev);
702 /* restore some register to sane defaults */
703 r100_restore_sanity(rdev);
702 /* TODO: disable VGA need to use VGA request */ 704 /* TODO: disable VGA need to use VGA request */
703 /* BIOS*/ 705 /* BIOS*/
704 if (!radeon_get_bios(rdev)) { 706 if (!radeon_get_bios(rdev)) {