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path: root/drivers/gpu/drm/radeon/rs600.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/rs600.c')
-rw-r--r--drivers/gpu/drm/radeon/rs600.c123
1 files changed, 123 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index b312b72d76ce..c3890b76a1c0 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -46,6 +46,129 @@
46void rs600_gpu_init(struct radeon_device *rdev); 46void rs600_gpu_init(struct radeon_device *rdev);
47int rs600_mc_wait_for_idle(struct radeon_device *rdev); 47int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48 48
49void rs600_pm_misc(struct radeon_device *rdev)
50{
51#if 0
52 int requested_index = rdev->pm.requested_power_state_index;
53 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
54 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
55 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
56 u32 hdp_dyn_cntl, mc_host_dyn_cntl;
57
58 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
59 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
60 tmp = RREG32(voltage->gpio.reg);
61 if (voltage->active_high)
62 tmp |= voltage->gpio.mask;
63 else
64 tmp &= ~(voltage->gpio.mask);
65 WREG32(voltage->gpio.reg, tmp);
66 if (voltage->delay)
67 udelay(voltage->delay);
68 } else {
69 tmp = RREG32(voltage->gpio.reg);
70 if (voltage->active_high)
71 tmp &= ~voltage->gpio.mask;
72 else
73 tmp |= voltage->gpio.mask;
74 WREG32(voltage->gpio.reg, tmp);
75 if (voltage->delay)
76 udelay(voltage->delay);
77 }
78 }
79
80 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
81 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
82 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
83 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
84 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
85 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
86 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
87 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
88 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
89 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
90 }
91 } else {
92 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
93 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
94 }
95 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
96
97 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
98 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
99 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
100 if (voltage->delay) {
101 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
102 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
103 } else
104 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
105 } else
106 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
107 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
108
109 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
110 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
111 hdp_dyn_cntl &= ~HDP_FORCEON;
112 else
113 hdp_dyn_cntl |= HDP_FORCEON;
114 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
115
116 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
117 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
118 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
119 else
120 mc_host_dyn_cntl |= MC_HOST_FORCEON;
121 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
122
123 /* set pcie lanes */
124 if ((rdev->flags & RADEON_IS_PCIE) &&
125 !(rdev->flags & RADEON_IS_IGP) &&
126 rdev->asic->set_pcie_lanes &&
127 (ps->pcie_lanes !=
128 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
129 radeon_set_pcie_lanes(rdev,
130 ps->pcie_lanes);
131 DRM_INFO("Setting: p: %d\n", ps->pcie_lanes);
132 }
133#endif
134}
135
136void rs600_pm_prepare(struct radeon_device *rdev)
137{
138 struct drm_device *ddev = rdev->ddev;
139 struct drm_crtc *crtc;
140 struct radeon_crtc *radeon_crtc;
141 u32 tmp;
142
143 /* disable any active CRTCs */
144 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
145 radeon_crtc = to_radeon_crtc(crtc);
146 if (radeon_crtc->enabled) {
147 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
148 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
149 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
150 }
151 }
152}
153
154void rs600_pm_finish(struct radeon_device *rdev)
155{
156 struct drm_device *ddev = rdev->ddev;
157 struct drm_crtc *crtc;
158 struct radeon_crtc *radeon_crtc;
159 u32 tmp;
160
161 /* enable any active CRTCs */
162 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
163 radeon_crtc = to_radeon_crtc(crtc);
164 if (radeon_crtc->enabled) {
165 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
166 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
167 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
168 }
169 }
170}
171
49/* hpd for digital panel detect/disconnect */ 172/* hpd for digital panel detect/disconnect */
50bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 173bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
51{ 174{
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 22:54:22 -0500