1 files changed, 234 insertions, 51 deletions

diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 5f117cd8736a..a81bc7a21e14 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -37,6 +37,7 @@
  */
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "rs600d.h"
 
@@ -45,6 +46,107 @@
 void rs600_gpu_init(struct radeon_device *rdev);
 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 
+/* hpd for digital panel detect/disconnect */
+bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
+{
+        u32 tmp;
+        bool connected = false;
+
+        switch (hpd) {
+        case RADEON_HPD_1:
+                tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
+                if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
+                        connected = true;
+                break;
+        case RADEON_HPD_2:
+                tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
+                if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
+                        connected = true;
+                break;
+        default:
+                break;
+        }
+        return connected;
+}
+
+void rs600_hpd_set_polarity(struct radeon_device *rdev,
+                            enum radeon_hpd_id hpd)
+{
+        u32 tmp;
+        bool connected = rs600_hpd_sense(rdev, hpd);
+
+        switch (hpd) {
+        case RADEON_HPD_1:
+                tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
+                if (connected)
+                        tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
+                else
+                        tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
+                WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
+                break;
+        case RADEON_HPD_2:
+                tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
+                if (connected)
+                        tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
+                else
+                        tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
+                WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
+                break;
+        default:
+                break;
+        }
+}
+
+void rs600_hpd_init(struct radeon_device *rdev)
+{
+        struct drm_device *dev = rdev->ddev;
+        struct drm_connector *connector;
+
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+                switch (radeon_connector->hpd.hpd) {
+                case RADEON_HPD_1:
+                        WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
+                               S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
+                        rdev->irq.hpd[0] = true;
+                        break;
+                case RADEON_HPD_2:
+                        WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
+                               S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
+                        rdev->irq.hpd[1] = true;
+                        break;
+                default:
+                        break;
+                }
+        }
+        if (rdev->irq.installed)
+                rs600_irq_set(rdev);
+}
+
+void rs600_hpd_fini(struct radeon_device *rdev)
+{
+        struct drm_device *dev = rdev->ddev;
+        struct drm_connector *connector;
+
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+                switch (radeon_connector->hpd.hpd) {
+                case RADEON_HPD_1:
+                        WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
+                               S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
+                        rdev->irq.hpd[0] = false;
+                        break;
+                case RADEON_HPD_2:
+                        WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
+                               S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
+                        rdev->irq.hpd[1] = false;
+                        break;
+                default:
+                        break;
+                }
+        }
+}
+
 /*
  * GART.
  */
@@ -57,7 +159,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
-        tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
+        tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
@@ -95,45 +197,46 @@ int rs600_gart_enable(struct radeon_device *rdev)
         r = radeon_gart_table_vram_pin(rdev);
         if (r)
                 return r;
+        radeon_gart_restore(rdev);
         /* Enable bus master */
         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
         WREG32(R_00004C_BUS_CNTL, tmp);
         /* FIXME: setup default page */
         WREG32_MC(R_000100_MC_PT0_CNTL,
-                 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
-                  S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
+                  (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
+                   S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
+
         for (i = 0; i < 19; i++) {
                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
-                        S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
-                        S_00016C_SYSTEM_ACCESS_MODE_MASK(
-                                V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
-                        S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
-                                V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) |
-                        S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) |
-                        S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
-                        S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
+                          S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
+                          S_00016C_SYSTEM_ACCESS_MODE_MASK(
+                                  V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
+                          S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
+                                  V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
+                          S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
+                          S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
+                          S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
         }
-
-        /* System context map to GART space */
-        WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
-        WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
-
         /* enable first context */
-        WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
-        WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
-                        S_000102_ENABLE_PAGE_TABLE(1) |
-                        S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
+                  S_000102_ENABLE_PAGE_TABLE(1) |
+                  S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
+
         /* disable all other contexts */
-        for (i = 1; i < 8; i++) {
+        for (i = 1; i < 8; i++)
                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
-        }
 
         /* setup the page table */
         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
-                        rdev->gart.table_addr);
+                  rdev->gart.table_addr);
+        WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
+        WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 
+        /* System context maps to VRAM space */
+        WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
+        WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
+
         /* enable page tables */
         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
@@ -146,23 +249,28 @@ int rs600_gart_enable(struct radeon_device *rdev)
 
 void rs600_gart_disable(struct radeon_device *rdev)
 {
-        uint32_t tmp;
+        u32 tmp;
+        int r;
 
         /* FIXME: disable out of gart access */
         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
         tmp = RREG32_MC(R_000009_MC_CNTL1);
         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
         if (rdev->gart.table.vram.robj) {
-                radeon_object_kunmap(rdev->gart.table.vram.robj);
-                radeon_object_unpin(rdev->gart.table.vram.robj);
+                r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
+                if (r == 0) {
+                        radeon_bo_kunmap(rdev->gart.table.vram.robj);
+                        radeon_bo_unpin(rdev->gart.table.vram.robj);
+                        radeon_bo_unreserve(rdev->gart.table.vram.robj);
+                }
         }
 }
 
 void rs600_gart_fini(struct radeon_device *rdev)
 {
+        radeon_gart_fini(rdev);
         rs600_gart_disable(rdev);
         radeon_gart_table_vram_free(rdev);
-        radeon_gart_fini(rdev);
 }
 
 #define R600_PTE_VALID     (1 << 0)
@@ -189,7 +297,16 @@ int rs600_irq_set(struct radeon_device *rdev)
 {
         uint32_t tmp = 0;
         uint32_t mode_int = 0;
-
+        u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
+                ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
+        u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
+                ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
+
+        if (!rdev->irq.installed) {
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WREG32(R_000040_GEN_INT_CNTL, 0);
+                return -EINVAL;
+        }
         if (rdev->irq.sw_int) {
                 tmp |= S_000040_SW_INT_EN(1);
         }
@@ -199,8 +316,16 @@ int rs600_irq_set(struct radeon_device *rdev)
         if (rdev->irq.crtc_vblank_int[1]) {
                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
         }
+        if (rdev->irq.hpd[0]) {
+                hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
+        }
+        if (rdev->irq.hpd[1]) {
+                hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
+        }
         WREG32(R_000040_GEN_INT_CNTL, tmp);
         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
+        WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
+        WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
         return 0;
 }
 
@@ -208,6 +333,7 @@ static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_
 {
         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
         uint32_t irq_mask = ~C_000044_SW_INT;
+        u32 tmp;
 
         if (G_000044_DISPLAY_INT_STAT(irqs)) {
                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
@@ -219,6 +345,16 @@ static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_
                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
                                 S_006D34_D2MODE_VBLANK_ACK(1));
                 }
+                if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
+                        tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
+                        tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
+                        WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
+                }
+                if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
+                        tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
+                        tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
+                        WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
+                }
         } else {
                 *r500_disp_int = 0;
         }
@@ -244,6 +380,7 @@ int rs600_irq_process(struct radeon_device *rdev)
 {
         uint32_t status, msi_rearm;
         uint32_t r500_disp_int;
+        bool queue_hotplug = false;
 
         status = rs600_irq_ack(rdev, &r500_disp_int);
         if (!status && !r500_disp_int) {
@@ -251,15 +388,31 @@ int rs600_irq_process(struct radeon_device *rdev)
         }
         while (status || r500_disp_int) {
                 /* SW interrupt */
-                if (G_000040_SW_INT_EN(status))
+                if (G_000044_SW_INT(status))
                         radeon_fence_process(rdev);
                 /* Vertical blank interrupts */
-                if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
+                if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
                         drm_handle_vblank(rdev->ddev, 0);
-                if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
+                        rdev->pm.vblank_sync = true;
+                        wake_up(&rdev->irq.vblank_queue);
+                }
+                if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
                         drm_handle_vblank(rdev->ddev, 1);
+                        rdev->pm.vblank_sync = true;
+                        wake_up(&rdev->irq.vblank_queue);
+                }
+                if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
+                        queue_hotplug = true;
+                        DRM_DEBUG("HPD1\n");
+                }
+                if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
+                        queue_hotplug = true;
+                        DRM_DEBUG("HPD2\n");
+                }
                 status = rs600_irq_ack(rdev, &r500_disp_int);
         }
+        if (queue_hotplug)
+                queue_work(rdev->wq, &rdev->hotplug_work);
         if (rdev->msi_enabled) {
                 switch (rdev->family) {
                 case CHIP_RS600:
@@ -301,25 +454,59 @@ int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 
 void rs600_gpu_init(struct radeon_device *rdev)
 {
-        /* FIXME: HDP same place on rs600 ? */
         r100_hdp_reset(rdev);
-        /* FIXME: is this correct ? */
         r420_pipes_init(rdev);
         /* Wait for mc idle */
         if (rs600_mc_wait_for_idle(rdev))
                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 }
 
-void rs600_vram_info(struct radeon_device *rdev)
+void rs600_mc_init(struct radeon_device *rdev)
 {
-        /* FIXME: to do or is these values sane ? */
+        u64 base;
+
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
         rdev->mc.vram_is_ddr = true;
         rdev->mc.vram_width = 128;
+        rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+        rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
+        rdev->mc.visible_vram_size = rdev->mc.aper_size;
+        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+        base = RREG32_MC(R_000004_MC_FB_LOCATION);
+        base = G_000004_MC_FB_START(base) << 16;
+        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+        radeon_vram_location(rdev, &rdev->mc, base);
+        radeon_gtt_location(rdev, &rdev->mc);
+        radeon_update_bandwidth_info(rdev);
 }
 
 void rs600_bandwidth_update(struct radeon_device *rdev)
 {
-        /* FIXME: implement, should this be like rs690 ? */
+        struct drm_display_mode *mode0 = NULL;
+        struct drm_display_mode *mode1 = NULL;
+        u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
+        /* FIXME: implement full support */
+
+        radeon_update_display_priority(rdev);
+
+        if (rdev->mode_info.crtcs[0]->base.enabled)
+                mode0 = &rdev->mode_info.crtcs[0]->base.mode;
+        if (rdev->mode_info.crtcs[1]->base.enabled)
+                mode1 = &rdev->mode_info.crtcs[1]->base.mode;
+
+        rs690_line_buffer_adjust(rdev, mode0, mode1);
+
+        if (rdev->disp_priority == 2) {
+                d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
+                d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
+                d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
+                d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
+                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
+                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
+                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
+                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
+        }
 }
 
 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
@@ -388,8 +575,8 @@ static int rs600_startup(struct radeon_device *rdev)
         if (r)
                 return r;
         /* Enable IRQ */
-        rdev->irq.sw_int = true;
         rs600_irq_set(rdev);
+        rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -423,6 +610,8 @@ int rs600_resume(struct radeon_device *rdev)
         atom_asic_init(rdev->mode_info.atom_context);
         /* Resume clock after posting */
         rv515_clock_startup(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
         return rs600_startup(rdev);
 }
 
@@ -437,7 +626,7 @@ int rs600_suspend(struct radeon_device *rdev)
 
 void rs600_fini(struct radeon_device *rdev)
 {
-        rs600_suspend(rdev);
+        radeon_pm_fini(rdev);
         r100_cp_fini(rdev);
         r100_wb_fini(rdev);
         r100_ib_fini(rdev);
@@ -445,7 +634,7 @@ void rs600_fini(struct radeon_device *rdev)
         rs600_gart_fini(rdev);
         radeon_irq_kms_fini(rdev);
         radeon_fence_driver_fini(rdev);
-        radeon_object_fini(rdev);
+        radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
         kfree(rdev->bios);
         rdev->bios = NULL;
@@ -482,20 +671,15 @@ int rs600_init(struct radeon_device *rdev)
                         RREG32(R_0007C0_CP_STAT));
         }
         /* check if cards are posted or not */
-        if (!radeon_card_posted(rdev) && rdev->bios) {
-                DRM_INFO("GPU not posted. posting now...\n");
-                atom_asic_init(rdev->mode_info.atom_context);
-        }
+        if (radeon_boot_test_post_card(rdev) == false)
+                return -EINVAL;
+
         /* Initialize clocks */
         radeon_get_clock_info(rdev->ddev);
         /* Initialize power management */
         radeon_pm_init(rdev);
-        /* Get vram informations */
-        rs600_vram_info(rdev);
-        /* Initialize memory controller (also test AGP) */
-        r = r420_mc_init(rdev);
-        if (r)
-                return r;
+        /* initialize memory controller */
+        rs600_mc_init(rdev);
         rs600_debugfs(rdev);
         /* Fence driver */
         r = radeon_fence_driver_init(rdev);
@@ -505,7 +689,7 @@ int rs600_init(struct radeon_device *rdev)
         if (r)
                 return r;
         /* Memory manager */
-        r = radeon_object_init(rdev);
+        r = radeon_bo_init(rdev);
         if (r)
                 return r;
         r = rs600_gart_init(rdev);
@@ -517,7 +701,6 @@ int rs600_init(struct radeon_device *rdev)
         if (r) {
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
-                rs600_suspend(rdev);
                 r100_cp_fini(rdev);
                 r100_wb_fini(rdev);
                 r100_ib_fini(rdev);