1 files changed, 75 insertions, 104 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index f87efec76236..aaa19dc418a0 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -23,6 +23,7 @@
 #include "drmP.h"
 #include "radeon.h"
 #include "avivod.h"
+#include "atom.h"
 #ifdef CONFIG_ACPI
 #include <linux/acpi.h>
 #endif
@@ -167,13 +168,13 @@ static void radeon_set_power_state(struct radeon_device *rdev)
         if (radeon_gui_idle(rdev)) {
                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
-                if (sclk > rdev->clock.default_sclk)
-                        sclk = rdev->clock.default_sclk;
+                if (sclk > rdev->pm.default_sclk)
+                        sclk = rdev->pm.default_sclk;
 
                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
-                if (mclk > rdev->clock.default_mclk)
-                        mclk = rdev->clock.default_mclk;
+                if (mclk > rdev->pm.default_mclk)
+                        mclk = rdev->pm.default_mclk;
 
                 /* upvolt before raising clocks, downvolt after lowering clocks */
                 if (sclk < rdev->pm.current_sclk)
@@ -365,12 +366,14 @@ static ssize_t radeon_set_pm_profile(struct device *dev,
                 else if (strncmp("high", buf, strlen("high")) == 0)
                         rdev->pm.profile = PM_PROFILE_HIGH;
                 else {
-                        DRM_ERROR("invalid power profile!\n");
+                        count = -EINVAL;
                         goto fail;
                 }
                 radeon_pm_update_profile(rdev);
                 radeon_pm_set_clocks(rdev);
-        }
+        } else
+                count = -EINVAL;
+
 fail:
         mutex_unlock(&rdev->pm.mutex);
 
@@ -405,22 +408,15 @@ static ssize_t radeon_set_pm_method(struct device *dev,
                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
                 mutex_unlock(&rdev->pm.mutex);
         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
-                bool flush_wq = false;
-
                 mutex_lock(&rdev->pm.mutex);
-                if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
-                        cancel_delayed_work(&rdev->pm.dynpm_idle_work);
-                        flush_wq = true;
-                }
                 /* disable dynpm */
                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
                 rdev->pm.pm_method = PM_METHOD_PROFILE;
                 mutex_unlock(&rdev->pm.mutex);
-                if (flush_wq)
-                        flush_workqueue(rdev->wq);
+                cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
         } else {
-                DRM_ERROR("invalid power method!\n");
+                count = -EINVAL;
                 goto fail;
         }
         radeon_pm_compute_clocks(rdev);
@@ -437,7 +433,7 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
 {
         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
         struct radeon_device *rdev = ddev->dev_private;
-        u32 temp;
+        int temp;
 
         switch (rdev->pm.int_thermal_type) {
         case THERMAL_TYPE_RV6XX:
@@ -447,8 +443,12 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
                 temp = rv770_get_temp(rdev);
                 break;
         case THERMAL_TYPE_EVERGREEN:
+        case THERMAL_TYPE_NI:
                 temp = evergreen_get_temp(rdev);
                 break;
+        case THERMAL_TYPE_SUMO:
+                temp = sumo_get_temp(rdev);
+                break;
         default:
                 temp = 0;
                 break;
@@ -487,6 +487,8 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
         case THERMAL_TYPE_RV6XX:
         case THERMAL_TYPE_RV770:
         case THERMAL_TYPE_EVERGREEN:
+        case THERMAL_TYPE_NI:
+        case THERMAL_TYPE_SUMO:
                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
@@ -520,34 +522,44 @@ static void radeon_hwmon_fini(struct radeon_device *rdev)
 
 void radeon_pm_suspend(struct radeon_device *rdev)
 {
-        bool flush_wq = false;
-
         mutex_lock(&rdev->pm.mutex);
         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
-                cancel_delayed_work(&rdev->pm.dynpm_idle_work);
                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
-                flush_wq = true;
         }
         mutex_unlock(&rdev->pm.mutex);
-        if (flush_wq)
-                flush_workqueue(rdev->wq);
+
+        cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 }
 
 void radeon_pm_resume(struct radeon_device *rdev)
 {
+        /* set up the default clocks if the MC ucode is loaded */
+        if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
+                if (rdev->pm.default_vddc)
+                        radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
+                                                SET_VOLTAGE_TYPE_ASIC_VDDC);
+                if (rdev->pm.default_vddci)
+                        radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
+                                                SET_VOLTAGE_TYPE_ASIC_VDDCI);
+                if (rdev->pm.default_sclk)
+                        radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
+                if (rdev->pm.default_mclk)
+                        radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
+        }
         /* asic init will reset the default power state */
         mutex_lock(&rdev->pm.mutex);
         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
         rdev->pm.current_clock_mode_index = 0;
-        rdev->pm.current_sclk = rdev->clock.default_sclk;
-        rdev->pm.current_mclk = rdev->clock.default_mclk;
+        rdev->pm.current_sclk = rdev->pm.default_sclk;
+        rdev->pm.current_mclk = rdev->pm.default_mclk;
         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
+        rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
         if (rdev->pm.pm_method == PM_METHOD_DYNPM
             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
-                queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
-                                        msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
+                schedule_delayed_work(&rdev->pm.dynpm_idle_work,
+                                      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
         }
         mutex_unlock(&rdev->pm.mutex);
         radeon_pm_compute_clocks(rdev);
@@ -564,6 +576,8 @@ int radeon_pm_init(struct radeon_device *rdev)
         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
         rdev->pm.dynpm_can_upclock = true;
         rdev->pm.dynpm_can_downclock = true;
+        rdev->pm.default_sclk = rdev->clock.default_sclk;
+        rdev->pm.default_mclk = rdev->clock.default_mclk;
         rdev->pm.current_sclk = rdev->clock.default_sclk;
         rdev->pm.current_mclk = rdev->clock.default_mclk;
         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
@@ -575,12 +589,25 @@ int radeon_pm_init(struct radeon_device *rdev)
                         radeon_combios_get_power_modes(rdev);
                 radeon_pm_print_states(rdev);
                 radeon_pm_init_profile(rdev);
+                /* set up the default clocks if the MC ucode is loaded */
+                if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
+                        if (rdev->pm.default_vddc)
+                                radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
+                                                        SET_VOLTAGE_TYPE_ASIC_VDDC);
+                        if (rdev->pm.default_sclk)
+                                radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
+                        if (rdev->pm.default_mclk)
+                                radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
+                }
         }
 
         /* set up the internal thermal sensor if applicable */
         ret = radeon_hwmon_init(rdev);
         if (ret)
                 return ret;
+
+        INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
+
         if (rdev->pm.num_power_states > 1) {
                 /* where's the best place to put these? */
                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
@@ -594,8 +621,6 @@ int radeon_pm_init(struct radeon_device *rdev)
                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
                 register_acpi_notifier(&rdev->acpi_nb);
 #endif
-                INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
-
                 if (radeon_debugfs_pm_init(rdev)) {
                         DRM_ERROR("Failed to register debugfs file for PM!\n");
                 }
@@ -609,25 +634,20 @@ int radeon_pm_init(struct radeon_device *rdev)
 void radeon_pm_fini(struct radeon_device *rdev)
 {
         if (rdev->pm.num_power_states > 1) {
-                bool flush_wq = false;
-
                 mutex_lock(&rdev->pm.mutex);
                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
                         rdev->pm.profile = PM_PROFILE_DEFAULT;
                         radeon_pm_update_profile(rdev);
                         radeon_pm_set_clocks(rdev);
                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
-                        /* cancel work */
-                        cancel_delayed_work(&rdev->pm.dynpm_idle_work);
-                        flush_wq = true;
                         /* reset default clocks */
                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
                         radeon_pm_set_clocks(rdev);
                 }
                 mutex_unlock(&rdev->pm.mutex);
-                if (flush_wq)
-                        flush_workqueue(rdev->wq);
+
+                cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 
                 device_remove_file(rdev->dev, &dev_attr_power_profile);
                 device_remove_file(rdev->dev, &dev_attr_power_method);
@@ -636,6 +656,9 @@ void radeon_pm_fini(struct radeon_device *rdev)
 #endif
         }
 
+        if (rdev->pm.power_state)
+                kfree(rdev->pm.power_state);
+
         radeon_hwmon_fini(rdev);
 }
 
@@ -686,12 +709,12 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
                                         radeon_pm_get_dynpm_state(rdev);
                                         radeon_pm_set_clocks(rdev);
 
-                                        queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
-                                                           msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
+                                        schedule_delayed_work(&rdev->pm.dynpm_idle_work,
+                                                              msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
-                                        queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
-                                                           msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
+                                        schedule_delayed_work(&rdev->pm.dynpm_idle_work,
+                                                              msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
                                 }
                         } else { /* count == 0 */
@@ -712,73 +735,21 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
 
 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 {
-        u32 stat_crtc = 0, vbl = 0, position = 0;
+        int  crtc, vpos, hpos, vbl_status;
         bool in_vbl = true;
 
-        if (ASIC_IS_DCE4(rdev)) {
-                if (rdev->pm.active_crtcs & (1 << 0)) {
-                        vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
-                                     EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
-                        position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
-                                          EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
-                }
-                if (rdev->pm.active_crtcs & (1 << 1)) {
-                        vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
-                                     EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
-                        position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
-                                          EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
-                }
-                if (rdev->pm.active_crtcs & (1 << 2)) {
-                        vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
-                                     EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
-                        position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
-                                          EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
-                }
-                if (rdev->pm.active_crtcs & (1 << 3)) {
-                        vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
-                                     EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
-                        position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
-                                          EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
-                }
-                if (rdev->pm.active_crtcs & (1 << 4)) {
-                        vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
-                                     EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
-                        position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
-                                          EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
-                }
-                if (rdev->pm.active_crtcs & (1 << 5)) {
-                        vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
-                                     EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
-                        position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
-                                          EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
-                }
-        } else if (ASIC_IS_AVIVO(rdev)) {
-                if (rdev->pm.active_crtcs & (1 << 0)) {
-                        vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
-                        position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
-                }
-                if (rdev->pm.active_crtcs & (1 << 1)) {
-                        vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
-                        position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
-                }
-                if (position < vbl && position > 1)
-                        in_vbl = false;
-        } else {
-                if (rdev->pm.active_crtcs & (1 << 0)) {
-                        stat_crtc = RREG32(RADEON_CRTC_STATUS);
-                        if (!(stat_crtc & 1))
-                                in_vbl = false;
-                }
-                if (rdev->pm.active_crtcs & (1 << 1)) {
-                        stat_crtc = RREG32(RADEON_CRTC2_STATUS);
-                        if (!(stat_crtc & 1))
+        /* Iterate over all active crtc's. All crtc's must be in vblank,
+         * otherwise return in_vbl == false.
+         */
+        for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
+                if (rdev->pm.active_crtcs & (1 << crtc)) {
+                        vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
+                        if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
+                            !(vbl_status & DRM_SCANOUTPOS_INVBL))
                                 in_vbl = false;
                 }
         }
 
-        if (position < vbl && position > 1)
-                in_vbl = false;
-
         return in_vbl;
 }
 
@@ -848,8 +819,8 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work)
                         radeon_pm_set_clocks(rdev);
                 }
 
-                queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
-                                        msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
+                schedule_delayed_work(&rdev->pm.dynpm_idle_work,
+                                      msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
         }
         mutex_unlock(&rdev->pm.mutex);
         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
@@ -866,9 +837,9 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
         struct drm_device *dev = node->minor->dev;
         struct radeon_device *rdev = dev->dev_private;
 
-        seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
+        seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
-        seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
+        seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
         if (rdev->asic->get_memory_clock)
                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
         if (rdev->pm.current_vddc)