1 files changed, 373 insertions, 54 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index c85df4afcb7a..bb1c122cad21 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -68,6 +68,36 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
 }
 
+static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        int i;
+
+        DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
+        WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
+
+        WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+        WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+        WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+
+        WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
+        WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
+        WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
+
+        WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
+        WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
+
+        WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
+        for (i = 0; i < 256; i++) {
+                WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
+                       (radeon_crtc->lut_r[i] << 20) |
+                       (radeon_crtc->lut_g[i] << 10) |
+                       (radeon_crtc->lut_b[i] << 0));
+        }
+}
+
 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 {
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -100,7 +130,9 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc)
         if (!crtc->enabled)
                 return;
 
-        if (ASIC_IS_AVIVO(rdev))
+        if (ASIC_IS_DCE4(rdev))
+                evergreen_crtc_load_lut(crtc);
+        else if (ASIC_IS_AVIVO(rdev))
                 avivo_crtc_load_lut(crtc);
         else
                 legacy_crtc_load_lut(crtc);
@@ -234,7 +266,7 @@ static const char *encoder_names[34] = {
         "INTERNAL_UNIPHY2",
 };
 
-static const char *connector_names[13] = {
+static const char *connector_names[15] = {
         "Unknown",
         "VGA",
         "DVI-I",
@@ -248,6 +280,18 @@ static const char *connector_names[13] = {
         "DisplayPort",
         "HDMI-A",
         "HDMI-B",
+        "TV",
+        "eDP",
+};
+
+static const char *hpd_names[7] = {
+        "NONE",
+        "HPD1",
+        "HPD2",
+        "HPD3",
+        "HPD4",
+        "HPD5",
+        "HPD6",
 };
 
 static void radeon_print_display_setup(struct drm_device *dev)
@@ -264,16 +308,27 @@ static void radeon_print_display_setup(struct drm_device *dev)
                 radeon_connector = to_radeon_connector(connector);
                 DRM_INFO("Connector %d:\n", i);
                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
-                if (radeon_connector->ddc_bus)
+                if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
+                        DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
+                if (radeon_connector->ddc_bus) {
                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
                                  radeon_connector->ddc_bus->rec.mask_data_reg,
                                  radeon_connector->ddc_bus->rec.a_clk_reg,
                                  radeon_connector->ddc_bus->rec.a_data_reg,
-                                 radeon_connector->ddc_bus->rec.put_clk_reg,
-                                 radeon_connector->ddc_bus->rec.put_data_reg,
-                                 radeon_connector->ddc_bus->rec.get_clk_reg,
-                                 radeon_connector->ddc_bus->rec.get_data_reg);
+                                 radeon_connector->ddc_bus->rec.en_clk_reg,
+                                 radeon_connector->ddc_bus->rec.en_data_reg,
+                                 radeon_connector->ddc_bus->rec.y_clk_reg,
+                                 radeon_connector->ddc_bus->rec.y_data_reg);
+                } else {
+                        if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+                            connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
+                                DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
+                }
                 DRM_INFO("  Encoders:\n");
                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                         radeon_encoder = to_radeon_encoder(encoder);
@@ -313,17 +368,20 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
 
         if (rdev->bios) {
                 if (rdev->is_atom_bios) {
-                        if (rdev->family >= CHIP_R600)
+                        ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
+                        if (ret == false)
                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
-                        else
-                                ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
-                } else
+                } else {
                         ret = radeon_get_legacy_connector_info_from_bios(dev);
+                        if (ret == false)
+                                ret = radeon_get_legacy_connector_info_from_table(dev);
+                }
         } else {
                 if (!ASIC_IS_AVIVO(rdev))
                         ret = radeon_get_legacy_connector_info_from_table(dev);
         }
         if (ret) {
+                radeon_setup_encoder_clones(dev);
                 radeon_print_display_setup(dev);
                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
                         radeon_ddc_dump(drm_connector);
@@ -334,16 +392,25 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
 
 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 {
+        struct drm_device *dev = radeon_connector->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
         int ret = 0;
 
+        if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+            (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
+                struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
+                if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
+                     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
+                        radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
+        }
         if (!radeon_connector->ddc_bus)
                 return -1;
         if (!radeon_connector->edid) {
-                radeon_i2c_do_lock(radeon_connector, 1);
                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
-                radeon_i2c_do_lock(radeon_connector, 0);
         }
-
+        /* some servers provide a hardcoded edid in rom for KVMs */
+        if (!radeon_connector->edid)
+                radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
         if (radeon_connector->edid) {
                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
@@ -361,9 +428,7 @@ static int radeon_ddc_dump(struct drm_connector *connector)
 
         if (!radeon_connector->ddc_bus)
                 return -1;
-        radeon_i2c_do_lock(radeon_connector, 1);
         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
-        radeon_i2c_do_lock(radeon_connector, 0);
         if (edid) {
                 kfree(edid);
         }
@@ -380,17 +445,18 @@ static inline uint32_t radeon_div(uint64_t n, uint32_t d)
         return n;
 }
 
-void radeon_compute_pll(struct radeon_pll *pll,
-                        uint64_t freq,
-                        uint32_t *dot_clock_p,
-                        uint32_t *fb_div_p,
-                        uint32_t *frac_fb_div_p,
-                        uint32_t *ref_div_p,
-                        uint32_t *post_div_p,
-                        int flags)
+static void radeon_compute_pll_legacy(struct radeon_pll *pll,
+                                      uint64_t freq,
+                                      uint32_t *dot_clock_p,
+                                      uint32_t *fb_div_p,
+                                      uint32_t *frac_fb_div_p,
+                                      uint32_t *ref_div_p,
+                                      uint32_t *post_div_p)
 {
         uint32_t min_ref_div = pll->min_ref_div;
         uint32_t max_ref_div = pll->max_ref_div;
+        uint32_t min_post_div = pll->min_post_div;
+        uint32_t max_post_div = pll->max_post_div;
         uint32_t min_fractional_feed_div = 0;
         uint32_t max_fractional_feed_div = 0;
         uint32_t best_vco = pll->best_vco;
@@ -402,11 +468,20 @@ void radeon_compute_pll(struct radeon_pll *pll,
         uint32_t best_error = 0xffffffff;
         uint32_t best_vco_diff = 1;
         uint32_t post_div;
+        u32 pll_out_min, pll_out_max;
 
         DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
         freq = freq * 1000;
 
-        if (flags & RADEON_PLL_USE_REF_DIV)
+        if (pll->flags & RADEON_PLL_IS_LCD) {
+                pll_out_min = pll->lcd_pll_out_min;
+                pll_out_max = pll->lcd_pll_out_max;
+        } else {
+                pll_out_min = pll->pll_out_min;
+                pll_out_max = pll->pll_out_max;
+        }
+
+        if (pll->flags & RADEON_PLL_USE_REF_DIV)
                 min_ref_div = max_ref_div = pll->reference_div;
         else {
                 while (min_ref_div < max_ref_div-1) {
@@ -421,19 +496,22 @@ void radeon_compute_pll(struct radeon_pll *pll,
                 }
         }
 
-        if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+        if (pll->flags & RADEON_PLL_USE_POST_DIV)
+                min_post_div = max_post_div = pll->post_div;
+
+        if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
                 min_fractional_feed_div = pll->min_frac_feedback_div;
                 max_fractional_feed_div = pll->max_frac_feedback_div;
         }
 
-        for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
+        for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
                 uint32_t ref_div;
 
-                if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+                if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
                         continue;
 
                 /* legacy radeons only have a few post_divs */
-                if (flags & RADEON_PLL_LEGACY) {
+                if (pll->flags & RADEON_PLL_LEGACY) {
                         if ((post_div == 5) ||
                             (post_div == 7) ||
                             (post_div == 9) ||
@@ -466,10 +544,10 @@ void radeon_compute_pll(struct radeon_pll *pll,
                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
                                 vco = radeon_div(tmp, ref_div);
 
-                                if (vco < pll->pll_out_min) {
+                                if (vco < pll_out_min) {
                                         min_feed_div = feedback_div + 1;
                                         continue;
-                                } else if (vco > pll->pll_out_max) {
+                                } else if (vco > pll_out_max) {
                                         max_feed_div = feedback_div;
                                         continue;
                                 }
@@ -480,7 +558,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
                                         current_freq = radeon_div(tmp, ref_div * post_div);
 
-                                        if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
+                                        if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
                                                 error = freq - current_freq;
                                                 error = error < 0 ? 0xffffffff : error;
                                         } else
@@ -507,12 +585,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
                                                         best_freq = current_freq;
                                                         best_error = error;
                                                         best_vco_diff = vco_diff;
-                                                } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
-                                                           ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
+                                                } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
+                                                           ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
                                                         best_post_div = post_div;
                                                         best_ref_div = ref_div;
                                                         best_feedback_div = feedback_div;
@@ -542,6 +620,214 @@ void radeon_compute_pll(struct radeon_pll *pll,
         *post_div_p = best_post_div;
 }
 
+static bool
+calc_fb_div(struct radeon_pll *pll,
+            uint32_t freq,
+            uint32_t post_div,
+            uint32_t ref_div,
+            uint32_t *fb_div,
+            uint32_t *fb_div_frac)
+{
+        fixed20_12 feedback_divider, a, b;
+        u32 vco_freq;
+
+        vco_freq = freq * post_div;
+        /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
+        a.full = rfixed_const(pll->reference_freq);
+        feedback_divider.full = rfixed_const(vco_freq);
+        feedback_divider.full = rfixed_div(feedback_divider, a);
+        a.full = rfixed_const(ref_div);
+        feedback_divider.full = rfixed_mul(feedback_divider, a);
+
+        if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+                /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
+                a.full = rfixed_const(10);
+                feedback_divider.full = rfixed_mul(feedback_divider, a);
+                feedback_divider.full += rfixed_const_half(0);
+                feedback_divider.full = rfixed_floor(feedback_divider);
+                feedback_divider.full = rfixed_div(feedback_divider, a);
+
+                /* *fb_div = floor(feedback_divider); */
+                a.full = rfixed_floor(feedback_divider);
+                *fb_div = rfixed_trunc(a);
+                /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
+                a.full = rfixed_const(10);
+                b.full = rfixed_mul(feedback_divider, a);
+
+                feedback_divider.full = rfixed_floor(feedback_divider);
+                feedback_divider.full = rfixed_mul(feedback_divider, a);
+                feedback_divider.full = b.full - feedback_divider.full;
+                *fb_div_frac = rfixed_trunc(feedback_divider);
+        } else {
+                /* *fb_div = floor(feedback_divider + 0.5); */
+                feedback_divider.full += rfixed_const_half(0);
+                feedback_divider.full = rfixed_floor(feedback_divider);
+
+                *fb_div = rfixed_trunc(feedback_divider);
+                *fb_div_frac = 0;
+        }
+
+        if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
+                return false;
+        else
+                return true;
+}
+
+static bool
+calc_fb_ref_div(struct radeon_pll *pll,
+                uint32_t freq,
+                uint32_t post_div,
+                uint32_t *fb_div,
+                uint32_t *fb_div_frac,
+                uint32_t *ref_div)
+{
+        fixed20_12 ffreq, max_error, error, pll_out, a;
+        u32 vco;
+        u32 pll_out_min, pll_out_max;
+
+        if (pll->flags & RADEON_PLL_IS_LCD) {
+                pll_out_min = pll->lcd_pll_out_min;
+                pll_out_max = pll->lcd_pll_out_max;
+        } else {
+                pll_out_min = pll->pll_out_min;
+                pll_out_max = pll->pll_out_max;
+        }
+
+        ffreq.full = rfixed_const(freq);
+        /* max_error = ffreq * 0.0025; */
+        a.full = rfixed_const(400);
+        max_error.full = rfixed_div(ffreq, a);
+
+        for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
+                if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
+                        vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
+                        vco = vco / ((*ref_div) * 10);
+
+                        if ((vco < pll_out_min) || (vco > pll_out_max))
+                                continue;
+
+                        /* pll_out = vco / post_div; */
+                        a.full = rfixed_const(post_div);
+                        pll_out.full = rfixed_const(vco);
+                        pll_out.full = rfixed_div(pll_out, a);
+
+                        if (pll_out.full >= ffreq.full) {
+                                error.full = pll_out.full - ffreq.full;
+                                if (error.full <= max_error.full)
+                                        return true;
+                        }
+                }
+        }
+        return false;
+}
+
+static void radeon_compute_pll_new(struct radeon_pll *pll,
+                                   uint64_t freq,
+                                   uint32_t *dot_clock_p,
+                                   uint32_t *fb_div_p,
+                                   uint32_t *frac_fb_div_p,
+                                   uint32_t *ref_div_p,
+                                   uint32_t *post_div_p)
+{
+        u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
+        u32 best_freq = 0, vco_frequency;
+        u32 pll_out_min, pll_out_max;
+
+        if (pll->flags & RADEON_PLL_IS_LCD) {
+                pll_out_min = pll->lcd_pll_out_min;
+                pll_out_max = pll->lcd_pll_out_max;
+        } else {
+                pll_out_min = pll->pll_out_min;
+                pll_out_max = pll->pll_out_max;
+        }
+
+        /* freq = freq / 10; */
+        do_div(freq, 10);
+
+        if (pll->flags & RADEON_PLL_USE_POST_DIV) {
+                post_div = pll->post_div;
+                if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
+                        goto done;
+
+                vco_frequency = freq * post_div;
+                if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
+                        goto done;
+
+                if (pll->flags & RADEON_PLL_USE_REF_DIV) {
+                        ref_div = pll->reference_div;
+                        if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
+                                goto done;
+                        if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
+                                goto done;
+                }
+        } else {
+                for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
+                        if (pll->flags & RADEON_PLL_LEGACY) {
+                                if ((post_div == 5) ||
+                                    (post_div == 7) ||
+                                    (post_div == 9) ||
+                                    (post_div == 10) ||
+                                    (post_div == 11))
+                                        continue;
+                        }
+
+                        if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+                                continue;
+
+                        vco_frequency = freq * post_div;
+                        if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
+                                continue;
+                        if (pll->flags & RADEON_PLL_USE_REF_DIV) {
+                                ref_div = pll->reference_div;
+                                if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
+                                        goto done;
+                                if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
+                                        break;
+                        } else {
+                                if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
+                                        break;
+                        }
+                }
+        }
+
+        best_freq = pll->reference_freq * 10 * fb_div;
+        best_freq += pll->reference_freq * fb_div_frac;
+        best_freq = best_freq / (ref_div * post_div);
+
+done:
+        if (best_freq == 0)
+                DRM_ERROR("Couldn't find valid PLL dividers\n");
+
+        *dot_clock_p = best_freq / 10;
+        *fb_div_p = fb_div;
+        *frac_fb_div_p = fb_div_frac;
+        *ref_div_p = ref_div;
+        *post_div_p = post_div;
+
+        DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
+}
+
+void radeon_compute_pll(struct radeon_pll *pll,
+                        uint64_t freq,
+                        uint32_t *dot_clock_p,
+                        uint32_t *fb_div_p,
+                        uint32_t *frac_fb_div_p,
+                        uint32_t *ref_div_p,
+                        uint32_t *post_div_p)
+{
+        switch (pll->algo) {
+        case PLL_ALGO_NEW:
+                radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
+                                       frac_fb_div_p, ref_div_p, post_div_p);
+                break;
+        case PLL_ALGO_LEGACY:
+        default:
+                radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
+                                          frac_fb_div_p, ref_div_p, post_div_p);
+                break;
+        }
+}
+
 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 {
         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
@@ -550,12 +836,8 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
         if (fb->fbdev)
                 radeonfb_remove(dev, fb);
 
-        if (radeon_fb->obj) {
-                radeon_gem_object_unpin(radeon_fb->obj);
-                mutex_lock(&dev->struct_mutex);
-                drm_gem_object_unreference(radeon_fb->obj);
-                mutex_unlock(&dev->struct_mutex);
-        }
+        if (radeon_fb->obj)
+                drm_gem_object_unreference_unlocked(radeon_fb->obj);
         drm_framebuffer_cleanup(fb);
         kfree(radeon_fb);
 }
@@ -599,7 +881,11 @@ radeon_user_framebuffer_create(struct drm_device *dev,
         struct drm_gem_object *obj;
 
         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
-
+        if (obj ==  NULL) {
+                dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
+                        "can't create framebuffer\n", mode_cmd->handle);
+                return NULL;
+        }
         return radeon_framebuffer_create(dev, mode_cmd, obj);
 }
 
@@ -629,7 +915,7 @@ static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
         { TV_STD_SECAM, "secam" },
 };
 
-int radeon_modeset_create_props(struct radeon_device *rdev)
+static int radeon_modeset_create_props(struct radeon_device *rdev)
 {
         int i, sz;
 
@@ -642,7 +928,7 @@ int radeon_modeset_create_props(struct radeon_device *rdev)
                         return -ENOMEM;
 
                 rdev->mode_info.coherent_mode_property->values[0] = 0;
-                rdev->mode_info.coherent_mode_property->values[0] = 1;
+                rdev->mode_info.coherent_mode_property->values[1] = 1;
         }
 
         if (!ASIC_IS_AVIVO(rdev)) {
@@ -666,7 +952,7 @@ int radeon_modeset_create_props(struct radeon_device *rdev)
         if (!rdev->mode_info.load_detect_property)
                 return -ENOMEM;
         rdev->mode_info.load_detect_property->values[0] = 0;
-        rdev->mode_info.load_detect_property->values[0] = 1;
+        rdev->mode_info.load_detect_property->values[1] = 1;
 
         drm_mode_create_scaling_mode_property(rdev->ddev);
 
@@ -685,9 +971,26 @@ int radeon_modeset_create_props(struct radeon_device *rdev)
         return 0;
 }
 
+void radeon_update_display_priority(struct radeon_device *rdev)
+{
+        /* adjustment options for the display watermarks */
+        if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
+                /* set display priority to high for r3xx, rv515 chips
+                 * this avoids flickering due to underflow to the
+                 * display controllers during heavy acceleration.
+                 */
+                if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515))
+                        rdev->disp_priority = 2;
+                else
+                        rdev->disp_priority = 0;
+        } else
+                rdev->disp_priority = radeon_disp_priority;
+
+}
+
 int radeon_modeset_init(struct radeon_device *rdev)
 {
-        int num_crtc = 2, i;
+        int i;
         int ret;
 
         drm_mode_config_init(rdev->ddev);
@@ -710,11 +1013,14 @@ int radeon_modeset_init(struct radeon_device *rdev)
                 return ret;
         }
 
-        if (rdev->flags & RADEON_SINGLE_CRTC)
-                num_crtc = 1;
+        /* check combios for a valid hardcoded EDID - Sun servers */
+        if (!rdev->is_atom_bios) {
+                /* check for hardcoded EDID in BIOS */
+                radeon_combios_check_hardcoded_edid(rdev);
+        }
 
         /* allocate crtcs */
-        for (i = 0; i < num_crtc; i++) {
+        for (i = 0; i < rdev->num_crtc; i++) {
                 radeon_crtc_init(rdev->ddev, i);
         }
 
@@ -723,13 +1029,18 @@ int radeon_modeset_init(struct radeon_device *rdev)
         if (!ret) {
                 return ret;
         }
+        /* initialize hpd */
+        radeon_hpd_init(rdev);
         drm_helper_initial_config(rdev->ddev);
         return 0;
 }
 
 void radeon_modeset_fini(struct radeon_device *rdev)
 {
+        kfree(rdev->mode_info.bios_hardcoded_edid);
+
         if (rdev->mode_info.mode_config_initialized) {
+                radeon_hpd_fini(rdev);
                 drm_mode_config_cleanup(rdev->ddev);
                 rdev->mode_info.mode_config_initialized = false;
         }
@@ -750,9 +1061,17 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
                 if (encoder->crtc != crtc)
                         continue;
                 if (first) {
-                        radeon_crtc->rmx_type = radeon_encoder->rmx_type;
+                        /* set scaling */
+                        if (radeon_encoder->rmx_type == RMX_OFF)
+                                radeon_crtc->rmx_type = RMX_OFF;
+                        else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
+                                 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
+                                radeon_crtc->rmx_type = radeon_encoder->rmx_type;
+                        else
+                                radeon_crtc->rmx_type = RMX_OFF;
+                        /* copy native mode */
                         memcpy(&radeon_crtc->native_mode,
-                                &radeon_encoder->native_mode,
+                               &radeon_encoder->native_mode,
                                 sizeof(struct drm_display_mode));
                         first = false;
                 } else {