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path: root/drivers/gpu/drm/radeon/radeon_device.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_device.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c20
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 044bc98fb459..835516d2d257 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1191,14 +1191,12 @@ int radeon_device_init(struct radeon_device *rdev,
1191 r = radeon_gem_init(rdev); 1191 r = radeon_gem_init(rdev);
1192 if (r) 1192 if (r)
1193 return r; 1193 return r;
1194 /* initialize vm here */ 1194
1195 mutex_init(&rdev->vm_manager.lock);
1196 /* Adjust VM size here. 1195 /* Adjust VM size here.
1197 * Currently set to 4GB ((1 << 20) 4k pages). 1196 * Currently set to 4GB ((1 << 20) 4k pages).
1198 * Max GPUVM size for cayman and SI is 40 bits. 1197 * Max GPUVM size for cayman and SI is 40 bits.
1199 */ 1198 */
1200 rdev->vm_manager.max_pfn = 1 << 20; 1199 rdev->vm_manager.max_pfn = 1 << 20;
1201 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1202 1200
1203 /* Set asic functions */ 1201 /* Set asic functions */
1204 r = radeon_asic_init(rdev); 1202 r = radeon_asic_init(rdev);
@@ -1426,7 +1424,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1426 1424
1427 /* unpin the front buffers */ 1425 /* unpin the front buffers */
1428 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1426 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1429 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 1427 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1430 struct radeon_bo *robj; 1428 struct radeon_bo *robj;
1431 1429
1432 if (rfb == NULL || rfb->obj == NULL) { 1430 if (rfb == NULL || rfb->obj == NULL) {
@@ -1445,10 +1443,9 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1445 /* evict vram memory */ 1443 /* evict vram memory */
1446 radeon_bo_evict_vram(rdev); 1444 radeon_bo_evict_vram(rdev);
1447 1445
1448 mutex_lock(&rdev->ring_lock);
1449 /* wait for gpu to finish processing current batch */ 1446 /* wait for gpu to finish processing current batch */
1450 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1447 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1451 r = radeon_fence_wait_empty_locked(rdev, i); 1448 r = radeon_fence_wait_empty(rdev, i);
1452 if (r) { 1449 if (r) {
1453 /* delay GPU reset to resume */ 1450 /* delay GPU reset to resume */
1454 force_completion = true; 1451 force_completion = true;
@@ -1457,7 +1454,6 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1457 if (force_completion) { 1454 if (force_completion) {
1458 radeon_fence_driver_force_completion(rdev); 1455 radeon_fence_driver_force_completion(rdev);
1459 } 1456 }
1460 mutex_unlock(&rdev->ring_lock);
1461 1457
1462 radeon_save_bios_scratch_regs(rdev); 1458 radeon_save_bios_scratch_regs(rdev);
1463 1459
@@ -1555,10 +1551,12 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1555 /* reset hpd state */ 1551 /* reset hpd state */
1556 radeon_hpd_init(rdev); 1552 radeon_hpd_init(rdev);
1557 /* blat the mode back in */ 1553 /* blat the mode back in */
1558 drm_helper_resume_force_mode(dev); 1554 if (fbcon) {
1559 /* turn on display hw */ 1555 drm_helper_resume_force_mode(dev);
1560 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1556 /* turn on display hw */
1561 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1557 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1558 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1559 }
1562 } 1560 }
1563 1561
1564 drm_kms_helper_poll_enable(dev); 1562 drm_kms_helper_poll_enable(dev);