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path: root/drivers/gpu/drm/radeon/radeon_cp.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_cp.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c64
1 files changed, 18 insertions, 46 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 4f7afc79dd82..2f042a3c0e62 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -417,8 +417,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
417 return -EBUSY; 417 return -EBUSY;
418} 418}
419 419
420static void radeon_init_pipes(drm_radeon_private_t *dev_priv) 420static void radeon_init_pipes(struct drm_device *dev)
421{ 421{
422 drm_radeon_private_t *dev_priv = dev->dev_private;
422 uint32_t gb_tile_config, gb_pipe_sel = 0; 423 uint32_t gb_tile_config, gb_pipe_sel = 0;
423 424
424 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) { 425 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
@@ -434,13 +435,19 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
434 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 435 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
435 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 436 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
436 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 437 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
438 /* SE cards have 1 pipe */
439 if ((dev->pdev->device == 0x5e4c) ||
440 (dev->pdev->device == 0x5e4f))
441 dev_priv->num_gb_pipes = 1;
437 } else { 442 } else {
438 /* R3xx */ 443 /* R3xx */
439 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 444 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
440 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 445 dev->pdev->device != 0x4144) ||
446 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
447 dev->pdev->device != 0x4148)) {
441 dev_priv->num_gb_pipes = 2; 448 dev_priv->num_gb_pipes = 2;
442 } else { 449 } else {
443 /* R3Vxx */ 450 /* RV3xx/R300 AD/R350 AH */
444 dev_priv->num_gb_pipes = 1; 451 dev_priv->num_gb_pipes = 1;
445 } 452 }
446 } 453 }
@@ -736,7 +743,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
736 743
737 /* setup the raster pipes */ 744 /* setup the raster pipes */
738 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 745 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
739 radeon_init_pipes(dev_priv); 746 radeon_init_pipes(dev);
740 747
741 /* Reset the CP ring */ 748 /* Reset the CP ring */
742 radeon_do_cp_reset(dev_priv); 749 radeon_do_cp_reset(dev_priv);
@@ -1644,6 +1651,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri
1644 radeon_cp_load_microcode(dev_priv); 1651 radeon_cp_load_microcode(dev_priv);
1645 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 1652 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1646 1653
1654 dev_priv->have_z_offset = 0;
1647 radeon_do_engine_reset(dev); 1655 radeon_do_engine_reset(dev);
1648 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); 1656 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1649 1657
@@ -1941,8 +1949,8 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1941 for (t = 0; t < dev_priv->usec_timeout; t++) { 1949 for (t = 0; t < dev_priv->usec_timeout; t++) {
1942 u32 done_age = GET_SCRATCH(dev_priv, 1); 1950 u32 done_age = GET_SCRATCH(dev_priv, 1);
1943 DRM_DEBUG("done_age = %d\n", done_age); 1951 DRM_DEBUG("done_age = %d\n", done_age);
1944 for (i = start; i < dma->buf_count; i++) { 1952 for (i = 0; i < dma->buf_count; i++) {
1945 buf = dma->buflist[i]; 1953 buf = dma->buflist[start];
1946 buf_priv = buf->dev_private; 1954 buf_priv = buf->dev_private;
1947 if (buf->file_priv == NULL || (buf->pending && 1955 if (buf->file_priv == NULL || (buf->pending &&
1948 buf_priv->age <= 1956 buf_priv->age <=
@@ -1951,7 +1959,8 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1951 buf->pending = 0; 1959 buf->pending = 0;
1952 return buf; 1960 return buf;
1953 } 1961 }
1954 start = 0; 1962 if (++start >= dma->buf_count)
1963 start = 0;
1955 } 1964 }
1956 1965
1957 if (t) { 1966 if (t) {
@@ -1960,47 +1969,9 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1960 } 1969 }
1961 } 1970 }
1962 1971
1963 DRM_DEBUG("returning NULL!\n");
1964 return NULL; 1972 return NULL;
1965} 1973}
1966 1974
1967#if 0
1968struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1969{
1970 struct drm_device_dma *dma = dev->dma;
1971 drm_radeon_private_t *dev_priv = dev->dev_private;
1972 drm_radeon_buf_priv_t *buf_priv;
1973 struct drm_buf *buf;
1974 int i, t;
1975 int start;
1976 u32 done_age;
1977
1978 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1979 if (++dev_priv->last_buf >= dma->buf_count)
1980 dev_priv->last_buf = 0;
1981
1982 start = dev_priv->last_buf;
1983 dev_priv->stats.freelist_loops++;
1984
1985 for (t = 0; t < 2; t++) {
1986 for (i = start; i < dma->buf_count; i++) {
1987 buf = dma->buflist[i];
1988 buf_priv = buf->dev_private;
1989 if (buf->file_priv == 0 || (buf->pending &&
1990 buf_priv->age <=
1991 done_age)) {
1992 dev_priv->stats.requested_bufs++;
1993 buf->pending = 0;
1994 return buf;
1995 }
1996 }
1997 start = 0;
1998 }
1999
2000 return NULL;
2001}
2002#endif
2003
2004void radeon_freelist_reset(struct drm_device * dev) 1975void radeon_freelist_reset(struct drm_device * dev)
2005{ 1976{
2006 struct drm_device_dma *dma = dev->dma; 1977 struct drm_device_dma *dma = dev->dma;
@@ -2182,6 +2153,7 @@ int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2182 &master_priv->sarea); 2153 &master_priv->sarea);
2183 if (ret) { 2154 if (ret) {
2184 DRM_ERROR("SAREA setup failed\n"); 2155 DRM_ERROR("SAREA setup failed\n");
2156 kfree(master_priv);
2185 return ret; 2157 return ret;
2186 } 2158 }
2187 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea); 2159 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);