1 files changed, 40 insertions, 7 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index a81354167621..f64936cc4dd9 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -44,6 +44,10 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
 
         ref_div =
             RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
+
+        if (ref_div == 0)
+                return 0;
+
         sclk = fb_div / ref_div;
 
         post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
@@ -52,13 +56,13 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
         else if (post_div == 3)
                 sclk >>= 2;
         else if (post_div == 4)
-                sclk >>= 4;
+                sclk >>= 3;
 
         return sclk;
 }
 
 /* 10 khz */
-static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
+uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
 {
         struct radeon_pll *mpll = &rdev->clock.mpll;
         uint32_t fb_div, ref_div, post_div, mclk;
@@ -70,6 +74,10 @@ static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
 
         ref_div =
             RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
+
+        if (ref_div == 0)
+                return 0;
+
         mclk = fb_div / ref_div;
 
         post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
@@ -78,7 +86,7 @@ static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
         else if (post_div == 3)
                 mclk >>= 2;
         else if (post_div == 4)
-                mclk >>= 4;
+                mclk >>= 3;
 
         return mclk;
 }
@@ -88,6 +96,7 @@ void radeon_get_clock_info(struct drm_device *dev)
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_pll *p1pll = &rdev->clock.p1pll;
         struct radeon_pll *p2pll = &rdev->clock.p2pll;
+        struct radeon_pll *dcpll = &rdev->clock.dcpll;
         struct radeon_pll *spll = &rdev->clock.spll;
         struct radeon_pll *mpll = &rdev->clock.mpll;
         int ret;
@@ -98,8 +107,19 @@ void radeon_get_clock_info(struct drm_device *dev)
                 ret = radeon_combios_get_clock_info(dev);
 
         if (ret) {
-                if (p1pll->reference_div < 2)
-                        p1pll->reference_div = 12;
+                if (p1pll->reference_div < 2) {
+                        if (!ASIC_IS_AVIVO(rdev)) {
+                                u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
+                                if (ASIC_IS_R300(rdev))
+                                        p1pll->reference_div =
+                                                (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
+                                else
+                                        p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
+                                if (p1pll->reference_div < 2)
+                                        p1pll->reference_div = 12;
+                        } else
+                                p1pll->reference_div = 12;
+                }
                 if (p2pll->reference_div < 2)
                         p2pll->reference_div = 12;
                 if (rdev->family < CHIP_RS600) {
@@ -185,6 +205,17 @@ void radeon_get_clock_info(struct drm_device *dev)
                 p2pll->max_frac_feedback_div = 0;
         }
 
+        /* dcpll is DCE4 only */
+        dcpll->min_post_div = 2;
+        dcpll->max_post_div = 0x7f;
+        dcpll->min_frac_feedback_div = 0;
+        dcpll->max_frac_feedback_div = 9;
+        dcpll->min_ref_div = 2;
+        dcpll->max_ref_div = 0x3ff;
+        dcpll->min_feedback_div = 4;
+        dcpll->max_feedback_div = 0xfff;
+        dcpll->best_vco = 0;
+
         p1pll->min_ref_div = 2;
         p1pll->max_ref_div = 0x3ff;
         p1pll->min_feedback_div = 4;
@@ -827,8 +858,10 @@ int radeon_static_clocks_init(struct drm_device *dev)
         /* XXX make sure engine is idle */
 
         if (radeon_dynclks != -1) {
-                if (radeon_dynclks)
-                        radeon_set_clock_gating(rdev, 1);
+                if (radeon_dynclks) {
+                        if (rdev->asic->set_clock_gating)
+                                radeon_set_clock_gating(rdev, 1);
+                }
         }
         radeon_apply_clock_quirks(rdev);
         return 0;