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path: root/drivers/gpu/drm/radeon/radeon_bios.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_bios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c77
1 files changed, 64 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 654787ec43f4..229a20f10e2b 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -104,7 +104,7 @@ static bool radeon_read_bios(struct radeon_device *rdev)
104static bool radeon_atrm_get_bios(struct radeon_device *rdev) 104static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{ 105{
106 int ret; 106 int ret;
107 int size = 64 * 1024; 107 int size = 256 * 1024;
108 int i; 108 int i;
109 109
110 if (!radeon_atrm_supported(rdev->pdev)) 110 if (!radeon_atrm_supported(rdev->pdev))
@@ -130,6 +130,46 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
130 } 130 }
131 return true; 131 return true;
132} 132}
133
134static bool ni_read_disabled_bios(struct radeon_device *rdev)
135{
136 u32 bus_cntl;
137 u32 d1vga_control;
138 u32 d2vga_control;
139 u32 vga_render_control;
140 u32 rom_cntl;
141 bool r;
142
143 bus_cntl = RREG32(R600_BUS_CNTL);
144 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
145 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
146 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
147 rom_cntl = RREG32(R600_ROM_CNTL);
148
149 /* enable the rom */
150 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
151 /* Disable VGA mode */
152 WREG32(AVIVO_D1VGA_CONTROL,
153 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
154 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
155 WREG32(AVIVO_D2VGA_CONTROL,
156 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
157 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
158 WREG32(AVIVO_VGA_RENDER_CONTROL,
159 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
160 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
161
162 r = radeon_read_bios(rdev);
163
164 /* restore regs */
165 WREG32(R600_BUS_CNTL, bus_cntl);
166 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
167 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
168 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
169 WREG32(R600_ROM_CNTL, rom_cntl);
170 return r;
171}
172
133static bool r700_read_disabled_bios(struct radeon_device *rdev) 173static bool r700_read_disabled_bios(struct radeon_device *rdev)
134{ 174{
135 uint32_t viph_control; 175 uint32_t viph_control;
@@ -143,7 +183,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
143 bool r; 183 bool r;
144 184
145 viph_control = RREG32(RADEON_VIPH_CONTROL); 185 viph_control = RREG32(RADEON_VIPH_CONTROL);
146 bus_cntl = RREG32(RADEON_BUS_CNTL); 186 bus_cntl = RREG32(R600_BUS_CNTL);
147 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 187 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
148 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 188 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
149 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 189 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -152,7 +192,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
152 /* disable VIP */ 192 /* disable VIP */
153 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 193 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
154 /* enable the rom */ 194 /* enable the rom */
155 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 195 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
156 /* Disable VGA mode */ 196 /* Disable VGA mode */
157 WREG32(AVIVO_D1VGA_CONTROL, 197 WREG32(AVIVO_D1VGA_CONTROL,
158 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 198 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
@@ -191,7 +231,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
191 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 231 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
192 } 232 }
193 WREG32(RADEON_VIPH_CONTROL, viph_control); 233 WREG32(RADEON_VIPH_CONTROL, viph_control);
194 WREG32(RADEON_BUS_CNTL, bus_cntl); 234 WREG32(R600_BUS_CNTL, bus_cntl);
195 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 235 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
196 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 236 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
197 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 237 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -216,7 +256,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
216 bool r; 256 bool r;
217 257
218 viph_control = RREG32(RADEON_VIPH_CONTROL); 258 viph_control = RREG32(RADEON_VIPH_CONTROL);
219 bus_cntl = RREG32(RADEON_BUS_CNTL); 259 bus_cntl = RREG32(R600_BUS_CNTL);
220 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 260 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
221 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 261 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
222 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 262 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -231,7 +271,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
231 /* disable VIP */ 271 /* disable VIP */
232 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 272 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
233 /* enable the rom */ 273 /* enable the rom */
234 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 274 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
235 /* Disable VGA mode */ 275 /* Disable VGA mode */
236 WREG32(AVIVO_D1VGA_CONTROL, 276 WREG32(AVIVO_D1VGA_CONTROL,
237 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 277 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
@@ -262,7 +302,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
262 302
263 /* restore regs */ 303 /* restore regs */
264 WREG32(RADEON_VIPH_CONTROL, viph_control); 304 WREG32(RADEON_VIPH_CONTROL, viph_control);
265 WREG32(RADEON_BUS_CNTL, bus_cntl); 305 WREG32(R600_BUS_CNTL, bus_cntl);
266 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 306 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
267 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 307 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
268 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 308 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -291,7 +331,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
291 331
292 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 332 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
293 viph_control = RREG32(RADEON_VIPH_CONTROL); 333 viph_control = RREG32(RADEON_VIPH_CONTROL);
294 bus_cntl = RREG32(RADEON_BUS_CNTL); 334 bus_cntl = RREG32(RV370_BUS_CNTL);
295 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 335 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
296 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 336 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
297 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 337 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -310,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
310 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
311 351
312 /* enable the rom */ 352 /* enable the rom */
313 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 353 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
314 354
315 /* Disable VGA mode */ 355 /* Disable VGA mode */
316 WREG32(AVIVO_D1VGA_CONTROL, 356 WREG32(AVIVO_D1VGA_CONTROL,
@@ -327,7 +367,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
327 /* restore regs */ 367 /* restore regs */
328 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 368 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
329 WREG32(RADEON_VIPH_CONTROL, viph_control); 369 WREG32(RADEON_VIPH_CONTROL, viph_control);
330 WREG32(RADEON_BUS_CNTL, bus_cntl); 370 WREG32(RV370_BUS_CNTL, bus_cntl);
331 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
332 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
333 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -350,7 +390,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
350 390
351 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 391 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
352 viph_control = RREG32(RADEON_VIPH_CONTROL); 392 viph_control = RREG32(RADEON_VIPH_CONTROL);
353 bus_cntl = RREG32(RADEON_BUS_CNTL); 393 if (rdev->flags & RADEON_IS_PCIE)
394 bus_cntl = RREG32(RV370_BUS_CNTL);
395 else
396 bus_cntl = RREG32(RADEON_BUS_CNTL);
354 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 397 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
355 crtc2_gen_cntl = 0; 398 crtc2_gen_cntl = 0;
356 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 399 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
@@ -372,7 +415,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
372 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 415 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
373 416
374 /* enable the rom */ 417 /* enable the rom */
375 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 418 if (rdev->flags & RADEON_IS_PCIE)
419 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
420 else
421 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
376 422
377 /* Turn off mem requests and CRTC for both controllers */ 423 /* Turn off mem requests and CRTC for both controllers */
378 WREG32(RADEON_CRTC_GEN_CNTL, 424 WREG32(RADEON_CRTC_GEN_CNTL,
@@ -399,7 +445,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
399 /* restore regs */ 445 /* restore regs */
400 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 446 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
401 WREG32(RADEON_VIPH_CONTROL, viph_control); 447 WREG32(RADEON_VIPH_CONTROL, viph_control);
402 WREG32(RADEON_BUS_CNTL, bus_cntl); 448 if (rdev->flags & RADEON_IS_PCIE)
449 WREG32(RV370_BUS_CNTL, bus_cntl);
450 else
451 WREG32(RADEON_BUS_CNTL, bus_cntl);
403 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 452 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
404 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 453 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
405 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 454 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
@@ -415,6 +464,8 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev)
415{ 464{
416 if (rdev->flags & RADEON_IS_IGP) 465 if (rdev->flags & RADEON_IS_IGP)
417 return igp_read_bios_from_vram(rdev); 466 return igp_read_bios_from_vram(rdev);
467 else if (rdev->family >= CHIP_BARTS)
468 return ni_read_disabled_bios(rdev);
418 else if (rdev->family >= CHIP_RV770) 469 else if (rdev->family >= CHIP_RV770)
419 return r700_read_disabled_bios(rdev); 470 return r700_read_disabled_bios(rdev);
420 else if (rdev->family >= CHIP_R600) 471 else if (rdev->family >= CHIP_R600)
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 19:59:21 -0400