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path: root/drivers/gpu/drm/radeon/radeon_bios.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_bios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 654787ec43f4..8f2c7b50dcf5 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -130,6 +130,7 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
130 } 130 }
131 return true; 131 return true;
132} 132}
133
133static bool r700_read_disabled_bios(struct radeon_device *rdev) 134static bool r700_read_disabled_bios(struct radeon_device *rdev)
134{ 135{
135 uint32_t viph_control; 136 uint32_t viph_control;
@@ -143,7 +144,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
143 bool r; 144 bool r;
144 145
145 viph_control = RREG32(RADEON_VIPH_CONTROL); 146 viph_control = RREG32(RADEON_VIPH_CONTROL);
146 bus_cntl = RREG32(RADEON_BUS_CNTL); 147 bus_cntl = RREG32(R600_BUS_CNTL);
147 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 148 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
148 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 149 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
149 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 150 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -152,7 +153,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
152 /* disable VIP */ 153 /* disable VIP */
153 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 154 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
154 /* enable the rom */ 155 /* enable the rom */
155 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 156 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
156 /* Disable VGA mode */ 157 /* Disable VGA mode */
157 WREG32(AVIVO_D1VGA_CONTROL, 158 WREG32(AVIVO_D1VGA_CONTROL,
158 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 159 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
@@ -191,7 +192,7 @@ static bool r700_read_disabled_bios(struct radeon_device *rdev)
191 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 192 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
192 } 193 }
193 WREG32(RADEON_VIPH_CONTROL, viph_control); 194 WREG32(RADEON_VIPH_CONTROL, viph_control);
194 WREG32(RADEON_BUS_CNTL, bus_cntl); 195 WREG32(R600_BUS_CNTL, bus_cntl);
195 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 196 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
196 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 197 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
197 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 198 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
@@ -216,7 +217,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
216 bool r; 217 bool r;
217 218
218 viph_control = RREG32(RADEON_VIPH_CONTROL); 219 viph_control = RREG32(RADEON_VIPH_CONTROL);
219 bus_cntl = RREG32(RADEON_BUS_CNTL); 220 bus_cntl = RREG32(R600_BUS_CNTL);
220 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 221 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
221 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 222 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
222 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 223 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
@@ -231,7 +232,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
231 /* disable VIP */ 232 /* disable VIP */
232 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 233 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
233 /* enable the rom */ 234 /* enable the rom */
234 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 235 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
235 /* Disable VGA mode */ 236 /* Disable VGA mode */
236 WREG32(AVIVO_D1VGA_CONTROL, 237 WREG32(AVIVO_D1VGA_CONTROL,
237 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 238 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
@@ -262,7 +263,7 @@ static bool r600_read_disabled_bios(struct radeon_device *rdev)
262 263
263 /* restore regs */ 264 /* restore regs */
264 WREG32(RADEON_VIPH_CONTROL, viph_control); 265 WREG32(RADEON_VIPH_CONTROL, viph_control);
265 WREG32(RADEON_BUS_CNTL, bus_cntl); 266 WREG32(R600_BUS_CNTL, bus_cntl);
266 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 267 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
267 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 268 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
268 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 269 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);