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path: root/drivers/gpu/drm/radeon/radeon.h
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 2f08219c39b6..9f19259667df 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1468,7 +1468,6 @@ struct radeon_uvd {
1468 void *cpu_addr; 1468 void *cpu_addr;
1469 uint64_t gpu_addr; 1469 uint64_t gpu_addr;
1470 void *saved_bo; 1470 void *saved_bo;
1471 unsigned fw_size;
1472 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1471 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1473 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1472 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1474 struct delayed_work idle_work; 1473 struct delayed_work idle_work;
@@ -2066,6 +2065,7 @@ struct radeon_device {
2066 const struct firmware *mec_fw; /* CIK MEC firmware */ 2065 const struct firmware *mec_fw; /* CIK MEC firmware */
2067 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2066 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2068 const struct firmware *smc_fw; /* SMC firmware */ 2067 const struct firmware *smc_fw; /* SMC firmware */
2068 const struct firmware *uvd_fw; /* UVD firmware */
2069 struct r600_blit r600_blit; 2069 struct r600_blit r600_blit;
2070 struct r600_vram_scratch vram_scratch; 2070 struct r600_vram_scratch vram_scratch;
2071 int msi_enabled; /* msi enabled */ 2071 int msi_enabled; /* msi enabled */
@@ -2095,6 +2095,8 @@ struct radeon_device {
2095 /* ACPI interface */ 2095 /* ACPI interface */
2096 struct radeon_atif atif; 2096 struct radeon_atif atif;
2097 struct radeon_atcs atcs; 2097 struct radeon_atcs atcs;
2098 /* srbm instance registers */
2099 struct mutex srbm_mutex;
2098}; 2100};
2099 2101
2100int radeon_device_init(struct radeon_device *rdev, 2102int radeon_device_init(struct radeon_device *rdev,
@@ -2161,7 +2163,7 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2161 WREG32(reg, tmp_); \ 2163 WREG32(reg, tmp_); \
2162 } while (0) 2164 } while (0)
2163#define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2165#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2164#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or) 2166#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2165#define WREG32_PLL_P(reg, val, mask) \ 2167#define WREG32_PLL_P(reg, val, mask) \
2166 do { \ 2168 do { \
2167 uint32_t tmp_ = RREG32_PLL(reg); \ 2169 uint32_t tmp_ = RREG32_PLL(reg); \