diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 38 |
1 files changed, 27 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 53b55608102b..c0356bb193e5 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
| @@ -96,6 +96,7 @@ extern int radeon_audio; | |||
| 96 | * symbol; | 96 | * symbol; |
| 97 | */ | 97 | */ |
| 98 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | 98 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 99 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ | ||
| 99 | #define RADEON_IB_POOL_SIZE 16 | 100 | #define RADEON_IB_POOL_SIZE 16 |
| 100 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | 101 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
| 101 | #define RADEONFB_CONN_LIMIT 4 | 102 | #define RADEONFB_CONN_LIMIT 4 |
| @@ -319,10 +320,12 @@ struct radeon_mc { | |||
| 319 | u64 real_vram_size; | 320 | u64 real_vram_size; |
| 320 | int vram_mtrr; | 321 | int vram_mtrr; |
| 321 | bool vram_is_ddr; | 322 | bool vram_is_ddr; |
| 323 | bool igp_sideport_enabled; | ||
| 322 | }; | 324 | }; |
| 323 | 325 | ||
| 324 | int radeon_mc_setup(struct radeon_device *rdev); | 326 | int radeon_mc_setup(struct radeon_device *rdev); |
| 325 | 327 | bool radeon_combios_sideport_present(struct radeon_device *rdev); | |
| 328 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | ||
| 326 | 329 | ||
| 327 | /* | 330 | /* |
| 328 | * GPU scratch registers structures, functions & helpers | 331 | * GPU scratch registers structures, functions & helpers |
| @@ -361,11 +364,12 @@ void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |||
| 361 | */ | 364 | */ |
| 362 | struct radeon_ib { | 365 | struct radeon_ib { |
| 363 | struct list_head list; | 366 | struct list_head list; |
| 364 | unsigned long idx; | 367 | unsigned idx; |
| 365 | uint64_t gpu_addr; | 368 | uint64_t gpu_addr; |
| 366 | struct radeon_fence *fence; | 369 | struct radeon_fence *fence; |
| 367 | uint32_t *ptr; | 370 | uint32_t *ptr; |
| 368 | uint32_t length_dw; | 371 | uint32_t length_dw; |
| 372 | bool free; | ||
| 369 | }; | 373 | }; |
| 370 | 374 | ||
| 371 | /* | 375 | /* |
| @@ -375,10 +379,9 @@ struct radeon_ib { | |||
| 375 | struct radeon_ib_pool { | 379 | struct radeon_ib_pool { |
| 376 | struct mutex mutex; | 380 | struct mutex mutex; |
| 377 | struct radeon_bo *robj; | 381 | struct radeon_bo *robj; |
| 378 | struct list_head scheduled_ibs; | ||
| 379 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; | 382 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| 380 | bool ready; | 383 | bool ready; |
| 381 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); | 384 | unsigned head_id; |
| 382 | }; | 385 | }; |
| 383 | 386 | ||
| 384 | struct radeon_cp { | 387 | struct radeon_cp { |
| @@ -408,13 +411,13 @@ struct r600_ih { | |||
| 408 | unsigned wptr_old; | 411 | unsigned wptr_old; |
| 409 | unsigned ring_size; | 412 | unsigned ring_size; |
| 410 | uint64_t gpu_addr; | 413 | uint64_t gpu_addr; |
| 411 | uint32_t align_mask; | ||
| 412 | uint32_t ptr_mask; | 414 | uint32_t ptr_mask; |
| 413 | spinlock_t lock; | 415 | spinlock_t lock; |
| 414 | bool enabled; | 416 | bool enabled; |
| 415 | }; | 417 | }; |
| 416 | 418 | ||
| 417 | struct r600_blit { | 419 | struct r600_blit { |
| 420 | struct mutex mutex; | ||
| 418 | struct radeon_bo *shader_obj; | 421 | struct radeon_bo *shader_obj; |
| 419 | u64 shader_gpu_addr; | 422 | u64 shader_gpu_addr; |
| 420 | u32 vs_offset, ps_offset; | 423 | u32 vs_offset, ps_offset; |
| @@ -463,6 +466,7 @@ struct radeon_cs_chunk { | |||
| 463 | }; | 466 | }; |
| 464 | 467 | ||
| 465 | struct radeon_cs_parser { | 468 | struct radeon_cs_parser { |
| 469 | struct device *dev; | ||
| 466 | struct radeon_device *rdev; | 470 | struct radeon_device *rdev; |
| 467 | struct drm_file *filp; | 471 | struct drm_file *filp; |
| 468 | /* chunks */ | 472 | /* chunks */ |
| @@ -654,11 +658,17 @@ struct radeon_asic { | |||
| 654 | uint32_t offset, uint32_t obj_size); | 658 | uint32_t offset, uint32_t obj_size); |
| 655 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); | 659 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
| 656 | void (*bandwidth_update)(struct radeon_device *rdev); | 660 | void (*bandwidth_update)(struct radeon_device *rdev); |
| 657 | void (*hdp_flush)(struct radeon_device *rdev); | ||
| 658 | void (*hpd_init)(struct radeon_device *rdev); | 661 | void (*hpd_init)(struct radeon_device *rdev); |
| 659 | void (*hpd_fini)(struct radeon_device *rdev); | 662 | void (*hpd_fini)(struct radeon_device *rdev); |
| 660 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | 663 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 661 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | 664 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 665 | /* ioctl hw specific callback. Some hw might want to perform special | ||
| 666 | * operation on specific ioctl. For instance on wait idle some hw | ||
| 667 | * might want to perform and HDP flush through MMIO as it seems that | ||
| 668 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | ||
| 669 | * through ring. | ||
| 670 | */ | ||
| 671 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | ||
| 662 | }; | 672 | }; |
| 663 | 673 | ||
| 664 | /* | 674 | /* |
| @@ -667,11 +677,14 @@ struct radeon_asic { | |||
| 667 | struct r100_asic { | 677 | struct r100_asic { |
| 668 | const unsigned *reg_safe_bm; | 678 | const unsigned *reg_safe_bm; |
| 669 | unsigned reg_safe_bm_size; | 679 | unsigned reg_safe_bm_size; |
| 680 | u32 hdp_cntl; | ||
| 670 | }; | 681 | }; |
| 671 | 682 | ||
| 672 | struct r300_asic { | 683 | struct r300_asic { |
| 673 | const unsigned *reg_safe_bm; | 684 | const unsigned *reg_safe_bm; |
| 674 | unsigned reg_safe_bm_size; | 685 | unsigned reg_safe_bm_size; |
| 686 | u32 resync_scratch; | ||
| 687 | u32 hdp_cntl; | ||
| 675 | }; | 688 | }; |
| 676 | 689 | ||
| 677 | struct r600_asic { | 690 | struct r600_asic { |
| @@ -843,7 +856,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev, | |||
| 843 | 856 | ||
| 844 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) | 857 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
| 845 | { | 858 | { |
| 846 | if (reg < 0x10000) | 859 | if (reg < rdev->rmmio_size) |
| 847 | return readl(((void __iomem *)rdev->rmmio) + reg); | 860 | return readl(((void __iomem *)rdev->rmmio) + reg); |
| 848 | else { | 861 | else { |
| 849 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | 862 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| @@ -853,7 +866,7 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) | |||
| 853 | 866 | ||
| 854 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | 867 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 855 | { | 868 | { |
| 856 | if (reg < 0x10000) | 869 | if (reg < rdev->rmmio_size) |
| 857 | writel(v, ((void __iomem *)rdev->rmmio) + reg); | 870 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
| 858 | else { | 871 | else { |
| 859 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | 872 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| @@ -1007,13 +1020,14 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) | |||
| 1007 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) | 1020 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
| 1008 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | 1021 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
| 1009 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) | 1022 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
| 1010 | #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev)) | ||
| 1011 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) | 1023 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
| 1012 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | 1024 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
| 1013 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | 1025 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
| 1014 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | 1026 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
| 1015 | 1027 | ||
| 1016 | /* Common functions */ | 1028 | /* Common functions */ |
| 1029 | /* AGP */ | ||
| 1030 | extern void radeon_agp_disable(struct radeon_device *rdev); | ||
| 1017 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); | 1031 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
| 1018 | extern int radeon_modeset_init(struct radeon_device *rdev); | 1032 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 1019 | extern void radeon_modeset_fini(struct radeon_device *rdev); | 1033 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
| @@ -1137,6 +1151,7 @@ extern bool r600_card_posted(struct radeon_device *rdev); | |||
| 1137 | extern void r600_cp_stop(struct radeon_device *rdev); | 1151 | extern void r600_cp_stop(struct radeon_device *rdev); |
| 1138 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); | 1152 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 1139 | extern int r600_cp_resume(struct radeon_device *rdev); | 1153 | extern int r600_cp_resume(struct radeon_device *rdev); |
| 1154 | extern void r600_cp_fini(struct radeon_device *rdev); | ||
| 1140 | extern int r600_count_pipe_bits(uint32_t val); | 1155 | extern int r600_count_pipe_bits(uint32_t val); |
| 1141 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); | 1156 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); |
| 1142 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); | 1157 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| @@ -1157,7 +1172,8 @@ extern int r600_irq_init(struct radeon_device *rdev); | |||
| 1157 | extern void r600_irq_fini(struct radeon_device *rdev); | 1172 | extern void r600_irq_fini(struct radeon_device *rdev); |
| 1158 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | 1173 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 1159 | extern int r600_irq_set(struct radeon_device *rdev); | 1174 | extern int r600_irq_set(struct radeon_device *rdev); |
| 1160 | 1175 | extern void r600_irq_suspend(struct radeon_device *rdev); | |
| 1176 | /* r600 audio */ | ||
| 1161 | extern int r600_audio_init(struct radeon_device *rdev); | 1177 | extern int r600_audio_init(struct radeon_device *rdev); |
| 1162 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); | 1178 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
| 1163 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); | 1179 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
