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-rw-r--r--drivers/gpu/drm/radeon/radeon.h445
1 files changed, 324 insertions, 121 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 224506a2f7b1..034218c3dbbb 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -28,8 +28,6 @@
28#ifndef __RADEON_H__ 28#ifndef __RADEON_H__
29#define __RADEON_H__ 29#define __RADEON_H__
30 30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done : 31/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should 32 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
@@ -67,6 +65,11 @@
67#include <linux/list.h> 65#include <linux/list.h>
68#include <linux/kref.h> 66#include <linux/kref.h>
69 67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
70#include "radeon_family.h" 73#include "radeon_family.h"
71#include "radeon_mode.h" 74#include "radeon_mode.h"
72#include "radeon_reg.h" 75#include "radeon_reg.h"
@@ -85,12 +88,18 @@ extern int radeon_benchmarking;
85extern int radeon_testing; 88extern int radeon_testing;
86extern int radeon_connector_table; 89extern int radeon_connector_table;
87extern int radeon_tv; 90extern int radeon_tv;
91extern int radeon_new_pll;
92extern int radeon_dynpm;
93extern int radeon_audio;
94extern int radeon_disp_priority;
95extern int radeon_hw_i2c;
88 96
89/* 97/*
90 * Copy from radeon_drv.h so we don't have to include both and have conflicting 98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
91 * symbol; 99 * symbol;
92 */ 100 */
93#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 101#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
102/* RADEON_IB_POOL_SIZE must be a power of 2 */
94#define RADEON_IB_POOL_SIZE 16 103#define RADEON_IB_POOL_SIZE 16
95#define RADEON_DEBUGFS_MAX_NUM_FILES 32 104#define RADEON_DEBUGFS_MAX_NUM_FILES 32
96#define RADEONFB_CONN_LIMIT 4 105#define RADEONFB_CONN_LIMIT 4
@@ -112,6 +121,21 @@ struct radeon_device;
112/* 121/*
113 * BIOS. 122 * BIOS.
114 */ 123 */
124#define ATRM_BIOS_PAGE 4096
125
126#if defined(CONFIG_VGA_SWITCHEROO)
127bool radeon_atrm_supported(struct pci_dev *pdev);
128int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
129#else
130static inline bool radeon_atrm_supported(struct pci_dev *pdev)
131{
132 return false;
133}
134
135static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
136 return -EINVAL;
137}
138#endif
115bool radeon_get_bios(struct radeon_device *rdev); 139bool radeon_get_bios(struct radeon_device *rdev);
116 140
117 141
@@ -132,17 +156,24 @@ void radeon_dummy_page_fini(struct radeon_device *rdev);
132struct radeon_clock { 156struct radeon_clock {
133 struct radeon_pll p1pll; 157 struct radeon_pll p1pll;
134 struct radeon_pll p2pll; 158 struct radeon_pll p2pll;
159 struct radeon_pll dcpll;
135 struct radeon_pll spll; 160 struct radeon_pll spll;
136 struct radeon_pll mpll; 161 struct radeon_pll mpll;
137 /* 10 Khz units */ 162 /* 10 Khz units */
138 uint32_t default_mclk; 163 uint32_t default_mclk;
139 uint32_t default_sclk; 164 uint32_t default_sclk;
165 uint32_t default_dispclk;
166 uint32_t dp_extclk;
140}; 167};
141 168
142/* 169/*
143 * Power management 170 * Power management
144 */ 171 */
145int radeon_pm_init(struct radeon_device *rdev); 172int radeon_pm_init(struct radeon_device *rdev);
173void radeon_pm_fini(struct radeon_device *rdev);
174void radeon_pm_compute_clocks(struct radeon_device *rdev);
175void radeon_combios_get_power_modes(struct radeon_device *rdev);
176void radeon_atombios_get_power_modes(struct radeon_device *rdev);
146 177
147/* 178/*
148 * Fences. 179 * Fences.
@@ -157,6 +188,7 @@ struct radeon_fence_driver {
157 struct list_head created; 188 struct list_head created;
158 struct list_head emited; 189 struct list_head emited;
159 struct list_head signaled; 190 struct list_head signaled;
191 bool initialized;
160}; 192};
161 193
162struct radeon_fence { 194struct radeon_fence {
@@ -186,76 +218,63 @@ void radeon_fence_unref(struct radeon_fence **fence);
186 * Tiling registers 218 * Tiling registers
187 */ 219 */
188struct radeon_surface_reg { 220struct radeon_surface_reg {
189 struct radeon_object *robj; 221 struct radeon_bo *bo;
190}; 222};
191 223
192#define RADEON_GEM_MAX_SURFACES 8 224#define RADEON_GEM_MAX_SURFACES 8
193 225
194/* 226/*
195 * Radeon buffer. 227 * TTM.
196 */ 228 */
197struct radeon_object; 229struct radeon_mman {
230 struct ttm_bo_global_ref bo_global_ref;
231 struct ttm_global_reference mem_global_ref;
232 struct ttm_bo_device bdev;
233 bool mem_global_referenced;
234 bool initialized;
235};
236
237struct radeon_bo {
238 /* Protected by gem.mutex */
239 struct list_head list;
240 /* Protected by tbo.reserved */
241 u32 placements[3];
242 struct ttm_placement placement;
243 struct ttm_buffer_object tbo;
244 struct ttm_bo_kmap_obj kmap;
245 unsigned pin_count;
246 void *kptr;
247 u32 tiling_flags;
248 u32 pitch;
249 int surface_reg;
250 /* Constant after initialization */
251 struct radeon_device *rdev;
252 struct drm_gem_object *gobj;
253};
198 254
199struct radeon_object_list { 255struct radeon_bo_list {
200 struct list_head list; 256 struct list_head list;
201 struct radeon_object *robj; 257 struct radeon_bo *bo;
202 uint64_t gpu_offset; 258 uint64_t gpu_offset;
203 unsigned rdomain; 259 unsigned rdomain;
204 unsigned wdomain; 260 unsigned wdomain;
205 uint32_t tiling_flags; 261 u32 tiling_flags;
206}; 262};
207 263
208int radeon_object_init(struct radeon_device *rdev);
209void radeon_object_fini(struct radeon_device *rdev);
210int radeon_object_create(struct radeon_device *rdev,
211 struct drm_gem_object *gobj,
212 unsigned long size,
213 bool kernel,
214 uint32_t domain,
215 bool interruptible,
216 struct radeon_object **robj_ptr);
217int radeon_object_kmap(struct radeon_object *robj, void **ptr);
218void radeon_object_kunmap(struct radeon_object *robj);
219void radeon_object_unref(struct radeon_object **robj);
220int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
221 uint64_t *gpu_addr);
222void radeon_object_unpin(struct radeon_object *robj);
223int radeon_object_wait(struct radeon_object *robj);
224int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
225int radeon_object_evict_vram(struct radeon_device *rdev);
226int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
227void radeon_object_force_delete(struct radeon_device *rdev);
228void radeon_object_list_add_object(struct radeon_object_list *lobj,
229 struct list_head *head);
230int radeon_object_list_validate(struct list_head *head, void *fence);
231void radeon_object_list_unvalidate(struct list_head *head);
232void radeon_object_list_clean(struct list_head *head);
233int radeon_object_fbdev_mmap(struct radeon_object *robj,
234 struct vm_area_struct *vma);
235unsigned long radeon_object_size(struct radeon_object *robj);
236void radeon_object_clear_surface_reg(struct radeon_object *robj);
237int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
238 bool force_drop);
239void radeon_object_set_tiling_flags(struct radeon_object *robj,
240 uint32_t tiling_flags, uint32_t pitch);
241void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
242void radeon_bo_move_notify(struct ttm_buffer_object *bo,
243 struct ttm_mem_reg *mem);
244void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
245/* 264/*
246 * GEM objects. 265 * GEM objects.
247 */ 266 */
248struct radeon_gem { 267struct radeon_gem {
268 struct mutex mutex;
249 struct list_head objects; 269 struct list_head objects;
250}; 270};
251 271
252int radeon_gem_init(struct radeon_device *rdev); 272int radeon_gem_init(struct radeon_device *rdev);
253void radeon_gem_fini(struct radeon_device *rdev); 273void radeon_gem_fini(struct radeon_device *rdev);
254int radeon_gem_object_create(struct radeon_device *rdev, int size, 274int radeon_gem_object_create(struct radeon_device *rdev, int size,
255 int alignment, int initial_domain, 275 int alignment, int initial_domain,
256 bool discardable, bool kernel, 276 bool discardable, bool kernel,
257 bool interruptible, 277 struct drm_gem_object **obj);
258 struct drm_gem_object **obj);
259int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 278int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
260 uint64_t *gpu_addr); 279 uint64_t *gpu_addr);
261void radeon_gem_object_unpin(struct drm_gem_object *obj); 280void radeon_gem_object_unpin(struct drm_gem_object *obj);
@@ -271,7 +290,7 @@ struct radeon_gart_table_ram {
271}; 290};
272 291
273struct radeon_gart_table_vram { 292struct radeon_gart_table_vram {
274 struct radeon_object *robj; 293 struct radeon_bo *robj;
275 volatile uint32_t *ptr; 294 volatile uint32_t *ptr;
276}; 295};
277 296
@@ -281,6 +300,7 @@ union radeon_gart_table {
281}; 300};
282 301
283#define RADEON_GPU_PAGE_SIZE 4096 302#define RADEON_GPU_PAGE_SIZE 4096
303#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
284 304
285struct radeon_gart { 305struct radeon_gart {
286 dma_addr_t table_addr; 306 dma_addr_t table_addr;
@@ -315,21 +335,21 @@ struct radeon_mc {
315 /* for some chips with <= 32MB we need to lie 335 /* for some chips with <= 32MB we need to lie
316 * about vram size near mc fb location */ 336 * about vram size near mc fb location */
317 u64 mc_vram_size; 337 u64 mc_vram_size;
318 u64 gtt_location; 338 u64 visible_vram_size;
319 u64 gtt_size; 339 u64 gtt_size;
320 u64 gtt_start; 340 u64 gtt_start;
321 u64 gtt_end; 341 u64 gtt_end;
322 u64 vram_location;
323 u64 vram_start; 342 u64 vram_start;
324 u64 vram_end; 343 u64 vram_end;
325 unsigned vram_width; 344 unsigned vram_width;
326 u64 real_vram_size; 345 u64 real_vram_size;
327 int vram_mtrr; 346 int vram_mtrr;
328 bool vram_is_ddr; 347 bool vram_is_ddr;
348 bool igp_sideport_enabled;
329}; 349};
330 350
331int radeon_mc_setup(struct radeon_device *rdev); 351bool radeon_combios_sideport_present(struct radeon_device *rdev);
332 352bool radeon_atombios_sideport_present(struct radeon_device *rdev);
333 353
334/* 354/*
335 * GPU scratch registers structures, functions & helpers 355 * GPU scratch registers structures, functions & helpers
@@ -352,22 +372,29 @@ struct radeon_irq {
352 bool sw_int; 372 bool sw_int;
353 /* FIXME: use a define max crtc rather than hardcode it */ 373 /* FIXME: use a define max crtc rather than hardcode it */
354 bool crtc_vblank_int[2]; 374 bool crtc_vblank_int[2];
375 wait_queue_head_t vblank_queue;
376 /* FIXME: use defines for max hpd/dacs */
377 bool hpd[6];
378 spinlock_t sw_lock;
379 int sw_refcount;
355}; 380};
356 381
357int radeon_irq_kms_init(struct radeon_device *rdev); 382int radeon_irq_kms_init(struct radeon_device *rdev);
358void radeon_irq_kms_fini(struct radeon_device *rdev); 383void radeon_irq_kms_fini(struct radeon_device *rdev);
359 384void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
385void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
360 386
361/* 387/*
362 * CP & ring. 388 * CP & ring.
363 */ 389 */
364struct radeon_ib { 390struct radeon_ib {
365 struct list_head list; 391 struct list_head list;
366 unsigned long idx; 392 unsigned idx;
367 uint64_t gpu_addr; 393 uint64_t gpu_addr;
368 struct radeon_fence *fence; 394 struct radeon_fence *fence;
369 uint32_t *ptr; 395 uint32_t *ptr;
370 uint32_t length_dw; 396 uint32_t length_dw;
397 bool free;
371}; 398};
372 399
373/* 400/*
@@ -376,15 +403,15 @@ struct radeon_ib {
376 */ 403 */
377struct radeon_ib_pool { 404struct radeon_ib_pool {
378 struct mutex mutex; 405 struct mutex mutex;
379 struct radeon_object *robj; 406 struct radeon_bo *robj;
380 struct list_head scheduled_ibs; 407 struct list_head bogus_ib;
381 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 408 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
382 bool ready; 409 bool ready;
383 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); 410 unsigned head_id;
384}; 411};
385 412
386struct radeon_cp { 413struct radeon_cp {
387 struct radeon_object *ring_obj; 414 struct radeon_bo *ring_obj;
388 volatile uint32_t *ring; 415 volatile uint32_t *ring;
389 unsigned rptr; 416 unsigned rptr;
390 unsigned wptr; 417 unsigned wptr;
@@ -399,8 +426,25 @@ struct radeon_cp {
399 bool ready; 426 bool ready;
400}; 427};
401 428
429/*
430 * R6xx+ IH ring
431 */
432struct r600_ih {
433 struct radeon_bo *ring_obj;
434 volatile uint32_t *ring;
435 unsigned rptr;
436 unsigned wptr;
437 unsigned wptr_old;
438 unsigned ring_size;
439 uint64_t gpu_addr;
440 uint32_t ptr_mask;
441 spinlock_t lock;
442 bool enabled;
443};
444
402struct r600_blit { 445struct r600_blit {
403 struct radeon_object *shader_obj; 446 struct mutex mutex;
447 struct radeon_bo *shader_obj;
404 u64 shader_gpu_addr; 448 u64 shader_gpu_addr;
405 u32 vs_offset, ps_offset; 449 u32 vs_offset, ps_offset;
406 u32 state_offset; 450 u32 state_offset;
@@ -415,6 +459,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
415int radeon_ib_pool_init(struct radeon_device *rdev); 459int radeon_ib_pool_init(struct radeon_device *rdev);
416void radeon_ib_pool_fini(struct radeon_device *rdev); 460void radeon_ib_pool_fini(struct radeon_device *rdev);
417int radeon_ib_test(struct radeon_device *rdev); 461int radeon_ib_test(struct radeon_device *rdev);
462extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
418/* Ring access between begin & end cannot sleep */ 463/* Ring access between begin & end cannot sleep */
419void radeon_ring_free_size(struct radeon_device *rdev); 464void radeon_ring_free_size(struct radeon_device *rdev);
420int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 465int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
@@ -430,8 +475,8 @@ void radeon_ring_fini(struct radeon_device *rdev);
430 */ 475 */
431struct radeon_cs_reloc { 476struct radeon_cs_reloc {
432 struct drm_gem_object *gobj; 477 struct drm_gem_object *gobj;
433 struct radeon_object *robj; 478 struct radeon_bo *robj;
434 struct radeon_object_list lobj; 479 struct radeon_bo_list lobj;
435 uint32_t handle; 480 uint32_t handle;
436 uint32_t flags; 481 uint32_t flags;
437}; 482};
@@ -448,6 +493,7 @@ struct radeon_cs_chunk {
448}; 493};
449 494
450struct radeon_cs_parser { 495struct radeon_cs_parser {
496 struct device *dev;
451 struct radeon_device *rdev; 497 struct radeon_device *rdev;
452 struct drm_file *filp; 498 struct drm_file *filp;
453 /* chunks */ 499 /* chunks */
@@ -527,7 +573,7 @@ void radeon_agp_fini(struct radeon_device *rdev);
527 * Writeback 573 * Writeback
528 */ 574 */
529struct radeon_wb { 575struct radeon_wb {
530 struct radeon_object *wb_obj; 576 struct radeon_bo *wb_obj;
531 volatile uint32_t *wb; 577 volatile uint32_t *wb;
532 uint64_t gpu_addr; 578 uint64_t gpu_addr;
533}; 579};
@@ -551,7 +597,100 @@ struct radeon_wb {
551 * Equation between gpu/memory clock and available bandwidth is hw dependent 597 * Equation between gpu/memory clock and available bandwidth is hw dependent
552 * (type of memory, bus size, efficiency, ...) 598 * (type of memory, bus size, efficiency, ...)
553 */ 599 */
600enum radeon_pm_state {
601 PM_STATE_DISABLED,
602 PM_STATE_MINIMUM,
603 PM_STATE_PAUSED,
604 PM_STATE_ACTIVE
605};
606enum radeon_pm_action {
607 PM_ACTION_NONE,
608 PM_ACTION_MINIMUM,
609 PM_ACTION_DOWNCLOCK,
610 PM_ACTION_UPCLOCK
611};
612
613enum radeon_voltage_type {
614 VOLTAGE_NONE = 0,
615 VOLTAGE_GPIO,
616 VOLTAGE_VDDC,
617 VOLTAGE_SW
618};
619
620enum radeon_pm_state_type {
621 POWER_STATE_TYPE_DEFAULT,
622 POWER_STATE_TYPE_POWERSAVE,
623 POWER_STATE_TYPE_BATTERY,
624 POWER_STATE_TYPE_BALANCED,
625 POWER_STATE_TYPE_PERFORMANCE,
626};
627
628enum radeon_pm_clock_mode_type {
629 POWER_MODE_TYPE_DEFAULT,
630 POWER_MODE_TYPE_LOW,
631 POWER_MODE_TYPE_MID,
632 POWER_MODE_TYPE_HIGH,
633};
634
635struct radeon_voltage {
636 enum radeon_voltage_type type;
637 /* gpio voltage */
638 struct radeon_gpio_rec gpio;
639 u32 delay; /* delay in usec from voltage drop to sclk change */
640 bool active_high; /* voltage drop is active when bit is high */
641 /* VDDC voltage */
642 u8 vddc_id; /* index into vddc voltage table */
643 u8 vddci_id; /* index into vddci voltage table */
644 bool vddci_enabled;
645 /* r6xx+ sw */
646 u32 voltage;
647};
648
649struct radeon_pm_non_clock_info {
650 /* pcie lanes */
651 int pcie_lanes;
652 /* standardized non-clock flags */
653 u32 flags;
654};
655
656struct radeon_pm_clock_info {
657 /* memory clock */
658 u32 mclk;
659 /* engine clock */
660 u32 sclk;
661 /* voltage info */
662 struct radeon_voltage voltage;
663 /* standardized clock flags - not sure we'll need these */
664 u32 flags;
665};
666
667struct radeon_power_state {
668 enum radeon_pm_state_type type;
669 /* XXX: use a define for num clock modes */
670 struct radeon_pm_clock_info clock_info[8];
671 /* number of valid clock modes in this power state */
672 int num_clock_modes;
673 struct radeon_pm_clock_info *default_clock_mode;
674 /* non clock info about this state */
675 struct radeon_pm_non_clock_info non_clock_info;
676 bool voltage_drop_active;
677};
678
679/*
680 * Some modes are overclocked by very low value, accept them
681 */
682#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
683
554struct radeon_pm { 684struct radeon_pm {
685 struct mutex mutex;
686 struct delayed_work idle_work;
687 enum radeon_pm_state state;
688 enum radeon_pm_action planned_action;
689 unsigned long action_timeout;
690 bool downclocked;
691 int active_crtcs;
692 int req_vblank;
693 bool vblank_sync;
555 fixed20_12 max_bandwidth; 694 fixed20_12 max_bandwidth;
556 fixed20_12 igp_sideport_mclk; 695 fixed20_12 igp_sideport_mclk;
557 fixed20_12 igp_system_mclk; 696 fixed20_12 igp_system_mclk;
@@ -562,7 +701,18 @@ struct radeon_pm {
562 fixed20_12 ht_bandwidth; 701 fixed20_12 ht_bandwidth;
563 fixed20_12 core_bandwidth; 702 fixed20_12 core_bandwidth;
564 fixed20_12 sclk; 703 fixed20_12 sclk;
704 fixed20_12 mclk;
565 fixed20_12 needed_bandwidth; 705 fixed20_12 needed_bandwidth;
706 /* XXX: use a define for num power modes */
707 struct radeon_power_state power_state[8];
708 /* number of valid power states */
709 int num_power_states;
710 struct radeon_power_state *current_power_state;
711 struct radeon_pm_clock_info *current_clock_mode;
712 struct radeon_power_state *requested_power_state;
713 struct radeon_pm_clock_info *requested_clock_mode;
714 struct radeon_power_state *default_power_state;
715 struct radeon_i2c_chan *i2c_bus;
566}; 716};
567 717
568 718
@@ -585,8 +735,6 @@ int radeon_debugfs_add_files(struct radeon_device *rdev,
585 struct drm_info_list *files, 735 struct drm_info_list *files,
586 unsigned nfiles); 736 unsigned nfiles);
587int radeon_debugfs_fence_init(struct radeon_device *rdev); 737int radeon_debugfs_fence_init(struct radeon_device *rdev);
588int r100_debugfs_rbbm_init(struct radeon_device *rdev);
589int r100_debugfs_cp_init(struct radeon_device *rdev);
590 738
591 739
592/* 740/*
@@ -632,13 +780,25 @@ struct radeon_asic {
632 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 780 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
633 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 781 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
634 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 782 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
783 int (*get_pcie_lanes)(struct radeon_device *rdev);
635 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 784 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
636 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 785 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
637 int (*set_surface_reg)(struct radeon_device *rdev, int reg, 786 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
638 uint32_t tiling_flags, uint32_t pitch, 787 uint32_t tiling_flags, uint32_t pitch,
639 uint32_t offset, uint32_t obj_size); 788 uint32_t offset, uint32_t obj_size);
640 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 789 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
641 void (*bandwidth_update)(struct radeon_device *rdev); 790 void (*bandwidth_update)(struct radeon_device *rdev);
791 void (*hpd_init)(struct radeon_device *rdev);
792 void (*hpd_fini)(struct radeon_device *rdev);
793 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
794 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
795 /* ioctl hw specific callback. Some hw might want to perform special
796 * operation on specific ioctl. For instance on wait idle some hw
797 * might want to perform and HDP flush through MMIO as it seems that
798 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
799 * through ring.
800 */
801 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
642}; 802};
643 803
644/* 804/*
@@ -647,11 +807,14 @@ struct radeon_asic {
647struct r100_asic { 807struct r100_asic {
648 const unsigned *reg_safe_bm; 808 const unsigned *reg_safe_bm;
649 unsigned reg_safe_bm_size; 809 unsigned reg_safe_bm_size;
810 u32 hdp_cntl;
650}; 811};
651 812
652struct r300_asic { 813struct r300_asic {
653 const unsigned *reg_safe_bm; 814 const unsigned *reg_safe_bm;
654 unsigned reg_safe_bm_size; 815 unsigned reg_safe_bm_size;
816 u32 resync_scratch;
817 u32 hdp_cntl;
655}; 818};
656 819
657struct r600_asic { 820struct r600_asic {
@@ -668,6 +831,9 @@ struct r600_asic {
668 unsigned sx_max_export_pos_size; 831 unsigned sx_max_export_pos_size;
669 unsigned sx_max_export_smx_size; 832 unsigned sx_max_export_smx_size;
670 unsigned sq_num_cf_insts; 833 unsigned sq_num_cf_insts;
834 unsigned tiling_nbanks;
835 unsigned tiling_npipes;
836 unsigned tiling_group_size;
671}; 837};
672 838
673struct rv770_asic { 839struct rv770_asic {
@@ -688,6 +854,9 @@ struct rv770_asic {
688 unsigned sc_prim_fifo_size; 854 unsigned sc_prim_fifo_size;
689 unsigned sc_hiz_tile_fifo_size; 855 unsigned sc_hiz_tile_fifo_size;
690 unsigned sc_earlyz_tile_fifo_fize; 856 unsigned sc_earlyz_tile_fifo_fize;
857 unsigned tiling_nbanks;
858 unsigned tiling_npipes;
859 unsigned tiling_group_size;
691}; 860};
692 861
693union radeon_asic_config { 862union radeon_asic_config {
@@ -697,6 +866,12 @@ union radeon_asic_config {
697 struct rv770_asic rv770; 866 struct rv770_asic rv770;
698}; 867};
699 868
869/*
870 * asic initizalization from radeon_asic.c
871 */
872void radeon_agp_disable(struct radeon_device *rdev);
873int radeon_asic_init(struct radeon_device *rdev);
874
700 875
701/* 876/*
702 * IOCTL. 877 * IOCTL.
@@ -751,9 +926,9 @@ struct radeon_device {
751 uint8_t *bios; 926 uint8_t *bios;
752 bool is_atom_bios; 927 bool is_atom_bios;
753 uint16_t bios_header_start; 928 uint16_t bios_header_start;
754 struct radeon_object *stollen_vga_memory; 929 struct radeon_bo *stollen_vga_memory;
755 struct fb_info *fbdev_info; 930 struct fb_info *fbdev_info;
756 struct radeon_object *fbdev_robj; 931 struct radeon_bo *fbdev_rbo;
757 struct radeon_framebuffer *fbdev_rfb; 932 struct radeon_framebuffer *fbdev_rfb;
758 /* Register mmio */ 933 /* Register mmio */
759 resource_size_t rmmio_base; 934 resource_size_t rmmio_base;
@@ -791,8 +966,24 @@ struct radeon_device {
791 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 966 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
792 const struct firmware *me_fw; /* all family ME firmware */ 967 const struct firmware *me_fw; /* all family ME firmware */
793 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 968 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
969 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
794 struct r600_blit r600_blit; 970 struct r600_blit r600_blit;
795 int msi_enabled; /* msi enabled */ 971 int msi_enabled; /* msi enabled */
972 struct r600_ih ih; /* r6/700 interrupt ring */
973 struct workqueue_struct *wq;
974 struct work_struct hotplug_work;
975 int num_crtc; /* number of crtcs */
976 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
977
978 /* audio stuff */
979 struct timer_list audio_timer;
980 int audio_channels;
981 int audio_rate;
982 int audio_bits_per_sample;
983 uint8_t audio_status_bits;
984 uint8_t audio_category_code;
985
986 bool powered_down;
796}; 987};
797 988
798int radeon_device_init(struct radeon_device *rdev, 989int radeon_device_init(struct radeon_device *rdev,
@@ -811,7 +1002,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
811 1002
812static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 1003static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
813{ 1004{
814 if (reg < 0x10000) 1005 if (reg < rdev->rmmio_size)
815 return readl(((void __iomem *)rdev->rmmio) + reg); 1006 return readl(((void __iomem *)rdev->rmmio) + reg);
816 else { 1007 else {
817 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1008 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -821,7 +1012,7 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
821 1012
822static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1013static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
823{ 1014{
824 if (reg < 0x10000) 1015 if (reg < rdev->rmmio_size)
825 writel(v, ((void __iomem *)rdev->rmmio) + reg); 1016 writel(v, ((void __iomem *)rdev->rmmio) + reg);
826 else { 1017 else {
827 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 1018 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -829,6 +1020,10 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
829 } 1020 }
830} 1021}
831 1022
1023/*
1024 * Cast helper
1025 */
1026#define to_radeon_fence(p) ((struct radeon_fence *)(p))
832 1027
833/* 1028/*
834 * Registers read & write functions. 1029 * Registers read & write functions.
@@ -846,6 +1041,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
846#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1041#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
847#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1042#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
848#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1043#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1044#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1045#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
849#define WREG32_P(reg, val, mask) \ 1046#define WREG32_P(reg, val, mask) \
850 do { \ 1047 do { \
851 uint32_t tmp_ = RREG32(reg); \ 1048 uint32_t tmp_ = RREG32(reg); \
@@ -907,7 +1104,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
907#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1104#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
908#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1105#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
909#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1106#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
910 1107#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
911 1108
912/* 1109/*
913 * BIOS helpers. 1110 * BIOS helpers.
@@ -965,18 +1162,29 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
965#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) 1162#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
966#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 1163#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
967#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) 1164#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
968#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 1165#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1166#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
969#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 1167#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
970#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 1168#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
971#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 1169#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
972#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 1170#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
973#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 1171#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1172#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1173#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1174#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1175#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
974 1176
975/* Common functions */ 1177/* Common functions */
1178/* AGP */
1179extern void radeon_agp_disable(struct radeon_device *rdev);
976extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1180extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1181extern void radeon_gart_restore(struct radeon_device *rdev);
977extern int radeon_modeset_init(struct radeon_device *rdev); 1182extern int radeon_modeset_init(struct radeon_device *rdev);
978extern void radeon_modeset_fini(struct radeon_device *rdev); 1183extern void radeon_modeset_fini(struct radeon_device *rdev);
979extern bool radeon_card_posted(struct radeon_device *rdev); 1184extern bool radeon_card_posted(struct radeon_device *rdev);
1185extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1186extern void radeon_update_display_priority(struct radeon_device *rdev);
1187extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
980extern int radeon_clocks_init(struct radeon_device *rdev); 1188extern int radeon_clocks_init(struct radeon_device *rdev);
981extern void radeon_clocks_fini(struct radeon_device *rdev); 1189extern void radeon_clocks_fini(struct radeon_device *rdev);
982extern void radeon_scratch_init(struct radeon_device *rdev); 1190extern void radeon_scratch_init(struct radeon_device *rdev);
@@ -984,51 +1192,14 @@ extern void radeon_surface_init(struct radeon_device *rdev);
984extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1192extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
985extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1193extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
986extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1194extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1195extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1196extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1197extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1198extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1199extern int radeon_resume_kms(struct drm_device *dev);
1200extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
987 1201
988/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1202/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
989struct r100_mc_save {
990 u32 GENMO_WT;
991 u32 CRTC_EXT_CNTL;
992 u32 CRTC_GEN_CNTL;
993 u32 CRTC2_GEN_CNTL;
994 u32 CUR_OFFSET;
995 u32 CUR2_OFFSET;
996};
997extern void r100_cp_disable(struct radeon_device *rdev);
998extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
999extern void r100_cp_fini(struct radeon_device *rdev);
1000extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
1001extern int r100_pci_gart_init(struct radeon_device *rdev);
1002extern void r100_pci_gart_fini(struct radeon_device *rdev);
1003extern int r100_pci_gart_enable(struct radeon_device *rdev);
1004extern void r100_pci_gart_disable(struct radeon_device *rdev);
1005extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
1006extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1007extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1008extern void r100_ib_fini(struct radeon_device *rdev);
1009extern int r100_ib_init(struct radeon_device *rdev);
1010extern void r100_irq_disable(struct radeon_device *rdev);
1011extern int r100_irq_set(struct radeon_device *rdev);
1012extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1013extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
1014extern void r100_vram_init_sizes(struct radeon_device *rdev);
1015extern void r100_wb_disable(struct radeon_device *rdev);
1016extern void r100_wb_fini(struct radeon_device *rdev);
1017extern int r100_wb_init(struct radeon_device *rdev);
1018extern void r100_hdp_reset(struct radeon_device *rdev);
1019extern int r100_rb2d_reset(struct radeon_device *rdev);
1020extern int r100_cp_reset(struct radeon_device *rdev);
1021extern void r100_vga_render_disable(struct radeon_device *rdev);
1022extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1023 struct radeon_cs_packet *pkt,
1024 struct radeon_object *robj);
1025extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1026 struct radeon_cs_packet *pkt,
1027 const unsigned *auth, unsigned n,
1028 radeon_packet0_check_t check);
1029extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1030 struct radeon_cs_packet *pkt,
1031 unsigned idx);
1032 1203
1033/* rv200,rv250,rv280 */ 1204/* rv200,rv250,rv280 */
1034extern void r200_set_safe_registers(struct radeon_device *rdev); 1205extern void r200_set_safe_registers(struct radeon_device *rdev);
@@ -1036,7 +1207,7 @@ extern void r200_set_safe_registers(struct radeon_device *rdev);
1036/* r300,r350,rv350,rv370,rv380 */ 1207/* r300,r350,rv350,rv370,rv380 */
1037extern void r300_set_reg_safe(struct radeon_device *rdev); 1208extern void r300_set_reg_safe(struct radeon_device *rdev);
1038extern void r300_mc_program(struct radeon_device *rdev); 1209extern void r300_mc_program(struct radeon_device *rdev);
1039extern void r300_vram_info(struct radeon_device *rdev); 1210extern void r300_mc_init(struct radeon_device *rdev);
1040extern void r300_clock_startup(struct radeon_device *rdev); 1211extern void r300_clock_startup(struct radeon_device *rdev);
1041extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 1212extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1042extern int rv370_pcie_gart_init(struct radeon_device *rdev); 1213extern int rv370_pcie_gart_init(struct radeon_device *rdev);
@@ -1045,7 +1216,6 @@ extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1045extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 1216extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1046 1217
1047/* r420,r423,rv410 */ 1218/* r420,r423,rv410 */
1048extern int r420_mc_init(struct radeon_device *rdev);
1049extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 1219extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1050extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1220extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1051extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 1221extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
@@ -1087,12 +1257,13 @@ extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1087 struct drm_display_mode *mode2); 1257 struct drm_display_mode *mode2);
1088 1258
1089/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1259/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1260extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1090extern bool r600_card_posted(struct radeon_device *rdev); 1261extern bool r600_card_posted(struct radeon_device *rdev);
1091extern void r600_cp_stop(struct radeon_device *rdev); 1262extern void r600_cp_stop(struct radeon_device *rdev);
1092extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1263extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1093extern int r600_cp_resume(struct radeon_device *rdev); 1264extern int r600_cp_resume(struct radeon_device *rdev);
1265extern void r600_cp_fini(struct radeon_device *rdev);
1094extern int r600_count_pipe_bits(uint32_t val); 1266extern int r600_count_pipe_bits(uint32_t val);
1095extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1096extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1267extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1097extern int r600_pcie_gart_init(struct radeon_device *rdev); 1268extern int r600_pcie_gart_init(struct radeon_device *rdev);
1098extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 1269extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
@@ -1104,7 +1275,39 @@ extern void r600_wb_disable(struct radeon_device *rdev);
1104extern void r600_scratch_init(struct radeon_device *rdev); 1275extern void r600_scratch_init(struct radeon_device *rdev);
1105extern int r600_blit_init(struct radeon_device *rdev); 1276extern int r600_blit_init(struct radeon_device *rdev);
1106extern void r600_blit_fini(struct radeon_device *rdev); 1277extern void r600_blit_fini(struct radeon_device *rdev);
1107extern int r600_cp_init_microcode(struct radeon_device *rdev); 1278extern int r600_init_microcode(struct radeon_device *rdev);
1108extern int r600_gpu_reset(struct radeon_device *rdev); 1279extern int r600_gpu_reset(struct radeon_device *rdev);
1280/* r600 irq */
1281extern int r600_irq_init(struct radeon_device *rdev);
1282extern void r600_irq_fini(struct radeon_device *rdev);
1283extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1284extern int r600_irq_set(struct radeon_device *rdev);
1285extern void r600_irq_suspend(struct radeon_device *rdev);
1286/* r600 audio */
1287extern int r600_audio_init(struct radeon_device *rdev);
1288extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1289extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1290extern void r600_audio_fini(struct radeon_device *rdev);
1291extern void r600_hdmi_init(struct drm_encoder *encoder);
1292extern void r600_hdmi_enable(struct drm_encoder *encoder);
1293extern void r600_hdmi_disable(struct drm_encoder *encoder);
1294extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1295extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1296extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1297 int channels,
1298 int rate,
1299 int bps,
1300 uint8_t status_bits,
1301 uint8_t category_code);
1302
1303/* evergreen */
1304struct evergreen_mc_save {
1305 u32 vga_control[6];
1306 u32 vga_render_control;
1307 u32 vga_hdp_control;
1308 u32 crtc_control[6];
1309};
1310
1311#include "radeon_object.h"
1109 1312
1110#endif 1313#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-24 10:42:46 -0400