diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 233 |
1 files changed, 233 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 59f9c993cc31..15bd3b216243 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
| @@ -824,6 +824,239 @@ | |||
| 824 | # define TARGET_LINK_SPEED_MASK (0xf << 0) | 824 | # define TARGET_LINK_SPEED_MASK (0xf << 0) |
| 825 | # define SELECTABLE_DEEMPHASIS (1 << 6) | 825 | # define SELECTABLE_DEEMPHASIS (1 << 6) |
| 826 | 826 | ||
| 827 | /* Audio clocks */ | ||
| 828 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 | ||
| 829 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 | ||
| 830 | #define DCCG_AUDIO_DTO0_LOAD 0x051c | ||
| 831 | # define DTO_LOAD (1 << 31) | ||
| 832 | #define DCCG_AUDIO_DTO0_CNTL 0x0520 | ||
| 833 | |||
| 834 | #define DCCG_AUDIO_DTO1_PHASE 0x0524 | ||
| 835 | #define DCCG_AUDIO_DTO1_MODULE 0x0528 | ||
| 836 | #define DCCG_AUDIO_DTO1_LOAD 0x052c | ||
| 837 | #define DCCG_AUDIO_DTO1_CNTL 0x0530 | ||
| 838 | |||
| 839 | #define DCCG_AUDIO_DTO_SELECT 0x0534 | ||
| 840 | |||
| 841 | /* digital blocks */ | ||
| 842 | #define TMDSA_CNTL 0x7880 | ||
| 843 | # define TMDSA_HDMI_EN (1 << 2) | ||
| 844 | #define LVTMA_CNTL 0x7a80 | ||
| 845 | # define LVTMA_HDMI_EN (1 << 2) | ||
| 846 | #define DDIA_CNTL 0x7200 | ||
| 847 | # define DDIA_HDMI_EN (1 << 2) | ||
| 848 | #define DIG0_CNTL 0x75a0 | ||
| 849 | # define DIG_MODE(x) (((x) & 7) << 8) | ||
| 850 | # define DIG_MODE_DP 0 | ||
| 851 | # define DIG_MODE_LVDS 1 | ||
| 852 | # define DIG_MODE_TMDS_DVI 2 | ||
| 853 | # define DIG_MODE_TMDS_HDMI 3 | ||
| 854 | # define DIG_MODE_SDVO 4 | ||
| 855 | #define DIG1_CNTL 0x79a0 | ||
| 856 | |||
| 857 | /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one | ||
| 858 | * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly | ||
| 859 | * different due to the new DIG blocks, but also have 2 instances. | ||
| 860 | * DCE 3.0 HDMI blocks are part of each DIG encoder. | ||
| 861 | */ | ||
| 862 | |||
| 863 | /* rs6xx/rs740/r6xx/dce3 */ | ||
| 864 | #define HDMI0_CONTROL 0x7400 | ||
| 865 | /* rs6xx/rs740/r6xx */ | ||
| 866 | # define HDMI0_ENABLE (1 << 0) | ||
| 867 | # define HDMI0_STREAM(x) (((x) & 3) << 2) | ||
| 868 | # define HDMI0_STREAM_TMDSA 0 | ||
| 869 | # define HDMI0_STREAM_LVTMA 1 | ||
| 870 | # define HDMI0_STREAM_DVOA 2 | ||
| 871 | # define HDMI0_STREAM_DDIA 3 | ||
| 872 | /* rs6xx/r6xx/dce3 */ | ||
| 873 | # define HDMI0_ERROR_ACK (1 << 8) | ||
| 874 | # define HDMI0_ERROR_MASK (1 << 9) | ||
| 875 | #define HDMI0_STATUS 0x7404 | ||
| 876 | # define HDMI0_ACTIVE_AVMUTE (1 << 0) | ||
| 877 | # define HDMI0_AUDIO_ENABLE (1 << 4) | ||
| 878 | # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) | ||
| 879 | # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) | ||
| 880 | #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 | ||
| 881 | # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) | ||
| 882 | # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) | ||
| 883 | # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) | ||
| 884 | # define HDMI0_AUDIO_TEST_EN (1 << 12) | ||
| 885 | # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) | ||
| 886 | # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) | ||
| 887 | # define HDMI0_60958_CS_UPDATE (1 << 26) | ||
| 888 | # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) | ||
| 889 | # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) | ||
| 890 | #define HDMI0_AUDIO_CRC_CONTROL 0x740c | ||
| 891 | # define HDMI0_AUDIO_CRC_EN (1 << 0) | ||
| 892 | #define HDMI0_VBI_PACKET_CONTROL 0x7410 | ||
| 893 | # define HDMI0_NULL_SEND (1 << 0) | ||
| 894 | # define HDMI0_GC_SEND (1 << 4) | ||
| 895 | # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ | ||
| 896 | #define HDMI0_INFOFRAME_CONTROL0 0x7414 | ||
| 897 | # define HDMI0_AVI_INFO_SEND (1 << 0) | ||
| 898 | # define HDMI0_AVI_INFO_CONT (1 << 1) | ||
| 899 | # define HDMI0_AUDIO_INFO_SEND (1 << 4) | ||
| 900 | # define HDMI0_AUDIO_INFO_CONT (1 << 5) | ||
| 901 | # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ | ||
| 902 | # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) | ||
| 903 | # define HDMI0_MPEG_INFO_SEND (1 << 8) | ||
| 904 | # define HDMI0_MPEG_INFO_CONT (1 << 9) | ||
| 905 | # define HDMI0_MPEG_INFO_UPDATE (1 << 10) | ||
| 906 | #define HDMI0_INFOFRAME_CONTROL1 0x7418 | ||
| 907 | # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) | ||
| 908 | # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) | ||
| 909 | # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) | ||
| 910 | #define HDMI0_GENERIC_PACKET_CONTROL 0x741c | ||
| 911 | # define HDMI0_GENERIC0_SEND (1 << 0) | ||
| 912 | # define HDMI0_GENERIC0_CONT (1 << 1) | ||
| 913 | # define HDMI0_GENERIC0_UPDATE (1 << 2) | ||
| 914 | # define HDMI0_GENERIC1_SEND (1 << 4) | ||
| 915 | # define HDMI0_GENERIC1_CONT (1 << 5) | ||
| 916 | # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) | ||
| 917 | # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) | ||
| 918 | #define HDMI0_GC 0x7428 | ||
| 919 | # define HDMI0_GC_AVMUTE (1 << 0) | ||
| 920 | #define HDMI0_AVI_INFO0 0x7454 | ||
| 921 | # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | ||
| 922 | # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) | ||
| 923 | # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) | ||
| 924 | # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) | ||
| 925 | # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) | ||
| 926 | # define HDMI0_AVI_INFO_Y_RGB 0 | ||
| 927 | # define HDMI0_AVI_INFO_Y_YCBCR422 1 | ||
| 928 | # define HDMI0_AVI_INFO_Y_YCBCR444 2 | ||
| 929 | # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) | ||
| 930 | # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) | ||
| 931 | # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) | ||
| 932 | # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) | ||
| 933 | # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) | ||
| 934 | # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) | ||
| 935 | # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) | ||
| 936 | #define HDMI0_AVI_INFO1 0x7458 | ||
| 937 | # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ | ||
| 938 | # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ | ||
| 939 | # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) | ||
| 940 | #define HDMI0_AVI_INFO2 0x745c | ||
| 941 | # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) | ||
| 942 | # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) | ||
| 943 | #define HDMI0_AVI_INFO3 0x7460 | ||
| 944 | # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) | ||
| 945 | # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) | ||
| 946 | #define HDMI0_MPEG_INFO0 0x7464 | ||
| 947 | # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | ||
| 948 | # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) | ||
| 949 | # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) | ||
| 950 | # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) | ||
| 951 | #define HDMI0_MPEG_INFO1 0x7468 | ||
| 952 | # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) | ||
| 953 | # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) | ||
| 954 | # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) | ||
| 955 | #define HDMI0_GENERIC0_HDR 0x746c | ||
| 956 | #define HDMI0_GENERIC0_0 0x7470 | ||
| 957 | #define HDMI0_GENERIC0_1 0x7474 | ||
| 958 | #define HDMI0_GENERIC0_2 0x7478 | ||
| 959 | #define HDMI0_GENERIC0_3 0x747c | ||
| 960 | #define HDMI0_GENERIC0_4 0x7480 | ||
| 961 | #define HDMI0_GENERIC0_5 0x7484 | ||
| 962 | #define HDMI0_GENERIC0_6 0x7488 | ||
| 963 | #define HDMI0_GENERIC1_HDR 0x748c | ||
| 964 | #define HDMI0_GENERIC1_0 0x7490 | ||
| 965 | #define HDMI0_GENERIC1_1 0x7494 | ||
| 966 | #define HDMI0_GENERIC1_2 0x7498 | ||
| 967 | #define HDMI0_GENERIC1_3 0x749c | ||
| 968 | #define HDMI0_GENERIC1_4 0x74a0 | ||
| 969 | #define HDMI0_GENERIC1_5 0x74a4 | ||
| 970 | #define HDMI0_GENERIC1_6 0x74a8 | ||
| 971 | #define HDMI0_ACR_32_0 0x74ac | ||
| 972 | # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) | ||
| 973 | #define HDMI0_ACR_32_1 0x74b0 | ||
| 974 | # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) | ||
| 975 | #define HDMI0_ACR_44_0 0x74b4 | ||
| 976 | # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) | ||
| 977 | #define HDMI0_ACR_44_1 0x74b8 | ||
| 978 | # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) | ||
| 979 | #define HDMI0_ACR_48_0 0x74bc | ||
| 980 | # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) | ||
| 981 | #define HDMI0_ACR_48_1 0x74c0 | ||
| 982 | # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) | ||
| 983 | #define HDMI0_ACR_STATUS_0 0x74c4 | ||
| 984 | #define HDMI0_ACR_STATUS_1 0x74c8 | ||
| 985 | #define HDMI0_AUDIO_INFO0 0x74cc | ||
| 986 | # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | ||
| 987 | # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) | ||
| 988 | #define HDMI0_AUDIO_INFO1 0x74d0 | ||
| 989 | # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) | ||
| 990 | # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) | ||
| 991 | # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) | ||
| 992 | # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) | ||
| 993 | #define HDMI0_60958_0 0x74d4 | ||
| 994 | # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) | ||
| 995 | # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) | ||
| 996 | # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) | ||
| 997 | # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) | ||
| 998 | # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) | ||
| 999 | # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) | ||
| 1000 | # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) | ||
| 1001 | # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) | ||
| 1002 | # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) | ||
| 1003 | # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) | ||
| 1004 | #define HDMI0_60958_1 0x74d8 | ||
| 1005 | # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) | ||
| 1006 | # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) | ||
| 1007 | # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) | ||
| 1008 | # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) | ||
| 1009 | # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) | ||
| 1010 | #define HDMI0_ACR_PACKET_CONTROL 0x74dc | ||
| 1011 | # define HDMI0_ACR_SEND (1 << 0) | ||
| 1012 | # define HDMI0_ACR_CONT (1 << 1) | ||
| 1013 | # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) | ||
| 1014 | # define HDMI0_ACR_HW 0 | ||
| 1015 | # define HDMI0_ACR_32 1 | ||
| 1016 | # define HDMI0_ACR_44 2 | ||
| 1017 | # define HDMI0_ACR_48 3 | ||
| 1018 | # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ | ||
| 1019 | # define HDMI0_ACR_AUTO_SEND (1 << 12) | ||
| 1020 | #define HDMI0_RAMP_CONTROL0 0x74e0 | ||
| 1021 | # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) | ||
| 1022 | #define HDMI0_RAMP_CONTROL1 0x74e4 | ||
| 1023 | # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) | ||
| 1024 | #define HDMI0_RAMP_CONTROL2 0x74e8 | ||
| 1025 | # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) | ||
| 1026 | #define HDMI0_RAMP_CONTROL3 0x74ec | ||
| 1027 | # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) | ||
| 1028 | /* HDMI0_60958_2 is r7xx only */ | ||
| 1029 | #define HDMI0_60958_2 0x74f0 | ||
| 1030 | # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) | ||
| 1031 | # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) | ||
| 1032 | # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) | ||
| 1033 | # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) | ||
| 1034 | # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) | ||
| 1035 | # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) | ||
| 1036 | /* r6xx only; second instance starts at 0x7700 */ | ||
| 1037 | #define HDMI1_CONTROL 0x7700 | ||
| 1038 | #define HDMI1_STATUS 0x7704 | ||
| 1039 | #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 | ||
| 1040 | /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ | ||
| 1041 | #define DCE3_HDMI1_CONTROL 0x7800 | ||
| 1042 | #define DCE3_HDMI1_STATUS 0x7804 | ||
| 1043 | #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 | ||
| 1044 | /* DCE3.2 (for interrupts) */ | ||
| 1045 | #define AFMT_STATUS 0x7600 | ||
| 1046 | # define AFMT_AUDIO_ENABLE (1 << 4) | ||
| 1047 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) | ||
| 1048 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) | ||
| 1049 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) | ||
| 1050 | #define AFMT_AUDIO_PACKET_CONTROL 0x7604 | ||
| 1051 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) | ||
| 1052 | # define AFMT_AUDIO_TEST_EN (1 << 12) | ||
| 1053 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) | ||
| 1054 | # define AFMT_60958_CS_UPDATE (1 << 26) | ||
| 1055 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) | ||
| 1056 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) | ||
| 1057 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) | ||
| 1058 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) | ||
| 1059 | |||
| 827 | /* | 1060 | /* |
| 828 | * PM4 | 1061 | * PM4 |
| 829 | */ | 1062 | */ |