diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_hdmi.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_hdmi.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index f443010ce90b..b0fa6002af3e 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c | |||
@@ -257,10 +257,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
257 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | 257 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
258 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | 258 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
259 | */ | 259 | */ |
260 | if (ASIC_IS_DCE3(rdev)) { | 260 | if (ASIC_IS_DCE32(rdev)) { |
261 | /* according to the reg specs, this should DCE3.2 only, but in | ||
262 | * practice it seems to cover DCE3.0 as well. | ||
263 | */ | ||
264 | if (dig->dig_encoder == 0) { | 261 | if (dig->dig_encoder == 0) { |
265 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; | 262 | dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
266 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); | 263 | dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
@@ -276,8 +273,21 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
276 | WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); | 273 | WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); |
277 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ | 274 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ |
278 | } | 275 | } |
276 | } else if (ASIC_IS_DCE3(rdev)) { | ||
277 | /* according to the reg specs, this should DCE3.2 only, but in | ||
278 | * practice it seems to cover DCE3.0/3.1 as well. | ||
279 | */ | ||
280 | if (dig->dig_encoder == 0) { | ||
281 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); | ||
282 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); | ||
283 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ | ||
284 | } else { | ||
285 | WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100); | ||
286 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); | ||
287 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ | ||
288 | } | ||
279 | } else { | 289 | } else { |
280 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ | 290 | /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */ |
281 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | | 291 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | |
282 | AUDIO_DTO_MODULE(clock / 10)); | 292 | AUDIO_DTO_MODULE(clock / 10)); |
283 | } | 293 | } |