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path: root/drivers/gpu/drm/radeon/r600_hdmi.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r600_hdmi.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c11
1 files changed, 2 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 456750a0daa5..e73b2a73494a 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -133,14 +133,7 @@ static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
133 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 133 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
134 uint32_t offset = dig->afmt->offset; 134 uint32_t offset = dig->afmt->offset;
135 uint8_t *frame = buffer + 3; 135 uint8_t *frame = buffer + 3;
136 136 uint8_t *header = buffer;
137 /* Our header values (type, version, length) should be alright, Intel
138 * is using the same. Checksum function also seems to be OK, it works
139 * fine for audio infoframe. However calculated value is always lower
140 * by 2 in comparison to fglrx. It breaks displaying anything in case
141 * of TVs that strictly check the checksum. Hack it manually here to
142 * workaround this issue. */
143 frame[0x0] += 2;
144 137
145 WREG32(HDMI0_AVI_INFO0 + offset, 138 WREG32(HDMI0_AVI_INFO0 + offset,
146 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 139 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
@@ -149,7 +142,7 @@ static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
149 WREG32(HDMI0_AVI_INFO2 + offset, 142 WREG32(HDMI0_AVI_INFO2 + offset,
150 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 143 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
151 WREG32(HDMI0_AVI_INFO3 + offset, 144 WREG32(HDMI0_AVI_INFO3 + offset,
152 frame[0xC] | (frame[0xD] << 8)); 145 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
153} 146}
154 147
155/* 148/*