diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 46 |
1 files changed, 26 insertions, 20 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index fe0c8eb76010..0a0848f0346d 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -388,17 +388,18 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
388 | } | 388 | } |
389 | 389 | ||
390 | if (!IS_ALIGNED(pitch, pitch_align)) { | 390 | if (!IS_ALIGNED(pitch, pitch_align)) { |
391 | dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", | 391 | dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", |
392 | __func__, __LINE__, pitch); | 392 | __func__, __LINE__, pitch, pitch_align, array_mode); |
393 | return -EINVAL; | 393 | return -EINVAL; |
394 | } | 394 | } |
395 | if (!IS_ALIGNED(height, height_align)) { | 395 | if (!IS_ALIGNED(height, height_align)) { |
396 | dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", | 396 | dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", |
397 | __func__, __LINE__, height); | 397 | __func__, __LINE__, height, height_align, array_mode); |
398 | return -EINVAL; | 398 | return -EINVAL; |
399 | } | 399 | } |
400 | if (!IS_ALIGNED(base_offset, base_align)) { | 400 | if (!IS_ALIGNED(base_offset, base_align)) { |
401 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | 401 | dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, |
402 | base_offset, base_align, array_mode); | ||
402 | return -EINVAL; | 403 | return -EINVAL; |
403 | } | 404 | } |
404 | 405 | ||
@@ -413,7 +414,10 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
413 | * broken userspace. | 414 | * broken userspace. |
414 | */ | 415 | */ |
415 | } else { | 416 | } else { |
416 | dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); | 417 | dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i, |
418 | array_mode, | ||
419 | track->cb_color_bo_offset[i], tmp, | ||
420 | radeon_bo_size(track->cb_color_bo[i])); | ||
417 | return -EINVAL; | 421 | return -EINVAL; |
418 | } | 422 | } |
419 | } | 423 | } |
@@ -548,17 +552,18 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
548 | } | 552 | } |
549 | 553 | ||
550 | if (!IS_ALIGNED(pitch, pitch_align)) { | 554 | if (!IS_ALIGNED(pitch, pitch_align)) { |
551 | dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n", | 555 | dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", |
552 | __func__, __LINE__, pitch); | 556 | __func__, __LINE__, pitch, pitch_align, array_mode); |
553 | return -EINVAL; | 557 | return -EINVAL; |
554 | } | 558 | } |
555 | if (!IS_ALIGNED(height, height_align)) { | 559 | if (!IS_ALIGNED(height, height_align)) { |
556 | dev_warn(p->dev, "%s:%d db height (%d) invalid\n", | 560 | dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", |
557 | __func__, __LINE__, height); | 561 | __func__, __LINE__, height, height_align, array_mode); |
558 | return -EINVAL; | 562 | return -EINVAL; |
559 | } | 563 | } |
560 | if (!IS_ALIGNED(base_offset, base_align)) { | 564 | if (!IS_ALIGNED(base_offset, base_align)) { |
561 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | 565 | dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i, |
566 | base_offset, base_align, array_mode); | ||
562 | return -EINVAL; | 567 | return -EINVAL; |
563 | } | 568 | } |
564 | 569 | ||
@@ -566,9 +571,10 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
566 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; | 571 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; |
567 | tmp = ntiles * bpe * 64 * nviews; | 572 | tmp = ntiles * bpe * 64 * nviews; |
568 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { | 573 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { |
569 | dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n", | 574 | dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", |
570 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, | 575 | array_mode, |
571 | radeon_bo_size(track->db_bo)); | 576 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, |
577 | radeon_bo_size(track->db_bo)); | ||
572 | return -EINVAL; | 578 | return -EINVAL; |
573 | } | 579 | } |
574 | } | 580 | } |
@@ -1350,18 +1356,18 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i | |||
1350 | /* XXX check height as well... */ | 1356 | /* XXX check height as well... */ |
1351 | 1357 | ||
1352 | if (!IS_ALIGNED(pitch, pitch_align)) { | 1358 | if (!IS_ALIGNED(pitch, pitch_align)) { |
1353 | dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", | 1359 | dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", |
1354 | __func__, __LINE__, pitch); | 1360 | __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); |
1355 | return -EINVAL; | 1361 | return -EINVAL; |
1356 | } | 1362 | } |
1357 | if (!IS_ALIGNED(base_offset, base_align)) { | 1363 | if (!IS_ALIGNED(base_offset, base_align)) { |
1358 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n", | 1364 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", |
1359 | __func__, __LINE__, base_offset); | 1365 | __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); |
1360 | return -EINVAL; | 1366 | return -EINVAL; |
1361 | } | 1367 | } |
1362 | if (!IS_ALIGNED(mip_offset, base_align)) { | 1368 | if (!IS_ALIGNED(mip_offset, base_align)) { |
1363 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n", | 1369 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", |
1364 | __func__, __LINE__, mip_offset); | 1370 | __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); |
1365 | return -EINVAL; | 1371 | return -EINVAL; |
1366 | } | 1372 | } |
1367 | 1373 | ||