diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_blit_kms.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_blit_kms.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index 39ae19d38c2f..62dd1c281c76 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c | |||
@@ -50,7 +50,7 @@ static void | |||
50 | set_render_target(struct radeon_device *rdev, int format, | 50 | set_render_target(struct radeon_device *rdev, int format, |
51 | int w, int h, u64 gpu_addr) | 51 | int w, int h, u64 gpu_addr) |
52 | { | 52 | { |
53 | struct radeon_cp *cp = &rdev->cp; | 53 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
54 | u32 cb_color_info; | 54 | u32 cb_color_info; |
55 | int pitch, slice; | 55 | int pitch, slice; |
56 | 56 | ||
@@ -104,7 +104,7 @@ cp_set_surface_sync(struct radeon_device *rdev, | |||
104 | u32 sync_type, u32 size, | 104 | u32 sync_type, u32 size, |
105 | u64 mc_addr) | 105 | u64 mc_addr) |
106 | { | 106 | { |
107 | struct radeon_cp *cp = &rdev->cp; | 107 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
108 | u32 cp_coher_size; | 108 | u32 cp_coher_size; |
109 | 109 | ||
110 | if (size == 0xffffffff) | 110 | if (size == 0xffffffff) |
@@ -123,7 +123,7 @@ cp_set_surface_sync(struct radeon_device *rdev, | |||
123 | static void | 123 | static void |
124 | set_shaders(struct radeon_device *rdev) | 124 | set_shaders(struct radeon_device *rdev) |
125 | { | 125 | { |
126 | struct radeon_cp *cp = &rdev->cp; | 126 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
127 | u64 gpu_addr; | 127 | u64 gpu_addr; |
128 | u32 sq_pgm_resources; | 128 | u32 sq_pgm_resources; |
129 | 129 | ||
@@ -170,7 +170,7 @@ set_shaders(struct radeon_device *rdev) | |||
170 | static void | 170 | static void |
171 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) | 171 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
172 | { | 172 | { |
173 | struct radeon_cp *cp = &rdev->cp; | 173 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
174 | u32 sq_vtx_constant_word2; | 174 | u32 sq_vtx_constant_word2; |
175 | 175 | ||
176 | sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | | 176 | sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | |
@@ -207,7 +207,7 @@ set_tex_resource(struct radeon_device *rdev, | |||
207 | int format, int w, int h, int pitch, | 207 | int format, int w, int h, int pitch, |
208 | u64 gpu_addr, u32 size) | 208 | u64 gpu_addr, u32 size) |
209 | { | 209 | { |
210 | struct radeon_cp *cp = &rdev->cp; | 210 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
211 | uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; | 211 | uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; |
212 | 212 | ||
213 | if (h < 1) | 213 | if (h < 1) |
@@ -246,7 +246,7 @@ static void | |||
246 | set_scissors(struct radeon_device *rdev, int x1, int y1, | 246 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
247 | int x2, int y2) | 247 | int x2, int y2) |
248 | { | 248 | { |
249 | struct radeon_cp *cp = &rdev->cp; | 249 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
250 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | 250 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
251 | radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); | 251 | radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
252 | radeon_ring_write(cp, (x1 << 0) | (y1 << 16)); | 252 | radeon_ring_write(cp, (x1 << 0) | (y1 << 16)); |
@@ -267,7 +267,7 @@ set_scissors(struct radeon_device *rdev, int x1, int y1, | |||
267 | static void | 267 | static void |
268 | draw_auto(struct radeon_device *rdev) | 268 | draw_auto(struct radeon_device *rdev) |
269 | { | 269 | { |
270 | struct radeon_cp *cp = &rdev->cp; | 270 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
271 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 271 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
272 | radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | 272 | radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
273 | radeon_ring_write(cp, DI_PT_RECTLIST); | 273 | radeon_ring_write(cp, DI_PT_RECTLIST); |
@@ -292,7 +292,7 @@ draw_auto(struct radeon_device *rdev) | |||
292 | static void | 292 | static void |
293 | set_default_state(struct radeon_device *rdev) | 293 | set_default_state(struct radeon_device *rdev) |
294 | { | 294 | { |
295 | struct radeon_cp *cp = &rdev->cp; | 295 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
296 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; | 296 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
297 | u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; | 297 | u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
298 | int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; | 298 | int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
@@ -687,7 +687,7 @@ static unsigned r600_blit_create_rect(unsigned num_gpu_pages, | |||
687 | 687 | ||
688 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages) | 688 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages) |
689 | { | 689 | { |
690 | struct radeon_cp *cp = &rdev->cp; | 690 | struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; |
691 | int r; | 691 | int r; |
692 | int ring_size; | 692 | int ring_size; |
693 | int num_loops = 0; | 693 | int num_loops = 0; |
@@ -727,7 +727,7 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) | |||
727 | if (fence) | 727 | if (fence) |
728 | r = radeon_fence_emit(rdev, fence); | 728 | r = radeon_fence_emit(rdev, fence); |
729 | 729 | ||
730 | radeon_ring_unlock_commit(rdev, &rdev->cp); | 730 | radeon_ring_unlock_commit(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]); |
731 | } | 731 | } |
732 | 732 | ||
733 | void r600_kms_blit_copy(struct radeon_device *rdev, | 733 | void r600_kms_blit_copy(struct radeon_device *rdev, |