1 files changed, 34 insertions, 26 deletions

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c70a504d96af..ea5c9af722ef 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1812,7 +1812,6 @@ static void r600_gpu_init(struct radeon_device *rdev)
 {
         u32 tiling_config;
         u32 ramcfg;
-        u32 cc_rb_backend_disable;
         u32 cc_gc_shader_pipe_config;
         u32 tmp;
         int i, j;
@@ -1939,29 +1938,20 @@ static void r600_gpu_init(struct radeon_device *rdev)
         }
         tiling_config |= BANK_SWAPS(1);
 
-        cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
-        tmp = R6XX_MAX_BACKENDS -
-                r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
-        if (tmp < rdev->config.r600.max_backends) {
-                rdev->config.r600.max_backends = tmp;
-        }
-
         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
-        tmp = R6XX_MAX_PIPES -
-                r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
-        if (tmp < rdev->config.r600.max_pipes) {
-                rdev->config.r600.max_pipes = tmp;
-        }
-        tmp = R6XX_MAX_SIMDS -
-                r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
-        if (tmp < rdev->config.r600.max_simds) {
-                rdev->config.r600.max_simds = tmp;
-        }
         tmp = rdev->config.r600.max_simds -
                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
         rdev->config.r600.active_simds = tmp;
 
         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
+        tmp = 0;
+        for (i = 0; i < rdev->config.r600.max_backends; i++)
+                tmp |= (1 << i);
+        /* if all the backends are disabled, fix it up here */
+        if ((disabled_rb_mask & tmp) == tmp) {
+                for (i = 0; i < rdev->config.r600.max_backends; i++)
+                        disabled_rb_mask &= ~(1 << i);
+        }
         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
@@ -2547,7 +2537,7 @@ int r600_cp_start(struct radeon_device *rdev)
         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
         radeon_ring_write(ring, 0);
         radeon_ring_write(ring, 0);
-        radeon_ring_unlock_commit(rdev, ring);
+        radeon_ring_unlock_commit(rdev, ring, false);
 
         cp_me = 0xff;
         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
@@ -2683,7 +2673,7 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
         radeon_ring_write(ring, 0xDEADBEEF);
-        radeon_ring_unlock_commit(rdev, ring);
+        radeon_ring_unlock_commit(rdev, ring, false);
         for (i = 0; i < rdev->usec_timeout; i++) {
                 tmp = RREG32(scratch);
                 if (tmp == 0xDEADBEEF)
@@ -2753,6 +2743,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
         }
 }
 
+/**
+ * r600_semaphore_ring_emit - emit a semaphore on the CP ring
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring buffer object
+ * @semaphore: radeon semaphore object
+ * @emit_wait: Is this a sempahore wait?
+ *
+ * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
+ * from running ahead of semaphore waits.
+ */
 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
                               struct radeon_ring *ring,
                               struct radeon_semaphore *semaphore,
@@ -2768,6 +2769,13 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(ring, lower_32_bits(addr));
         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
 
+        /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
+        if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
+                /* Prevent the PFP from running ahead of the semaphore wait */
+                radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
+                radeon_ring_write(ring, 0x0);
+        }
+
         return true;
 }
 
@@ -2845,7 +2853,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
                 return r;
         }
 
-        radeon_ring_unlock_commit(rdev, ring);
+        radeon_ring_unlock_commit(rdev, ring, false);
         radeon_semaphore_free(rdev, &sem, *fence);
 
         return r;
@@ -3165,7 +3173,7 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
         ib.ptr[2] = 0xDEADBEEF;
         ib.length_dw = 3;
-        r = radeon_ib_schedule(rdev, &ib, NULL);
+        r = radeon_ib_schedule(rdev, &ib, NULL, false);
         if (r) {
                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
                 goto free_ib;
@@ -3784,17 +3792,17 @@ static u32 r600_get_ih_wptr(struct radeon_device *rdev)
                 wptr = RREG32(IH_RB_WPTR);
 
         if (wptr & RB_OVERFLOW) {
+                wptr &= ~RB_OVERFLOW;
                 /* When a ring buffer overflow happen start parsing interrupt
                  * from the last not overwritten vector (wptr + 16). Hopefully
                  * this should allow us to catchup.
                  */
-                dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
-                        wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
+                dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
+                         wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
                 tmp = RREG32(IH_RB_CNTL);
                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
                 WREG32(IH_RB_CNTL, tmp);
-                wptr &= ~RB_OVERFLOW;
         }
         return (wptr & rdev->ih.ptr_mask);
 }
@@ -4040,6 +4048,7 @@ restart_ih:
                 /* wptr/rptr are in bytes! */
                 rptr += 16;
                 rptr &= rdev->ih.ptr_mask;
+                WREG32(IH_RB_RPTR, rptr);
         }
         if (queue_hotplug)
                 schedule_work(&rdev->hotplug_work);
@@ -4048,7 +4057,6 @@ restart_ih:
         if (queue_thermal && rdev->pm.dpm_enabled)
                 schedule_work(&rdev->pm.dpm.thermal.work);
         rdev->ih.rptr = rptr;
-        WREG32(IH_RB_RPTR, rdev->ih.rptr);
         atomic_set(&rdev->ih.lock, 0);
 
         /* make sure wptr hasn't changed while processing */