diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index a0ac3c134b1b..f5ff3490929f 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -285,7 +285,8 @@ void r600_hpd_init(struct radeon_device *rdev) | |||
285 | } | 285 | } |
286 | } | 286 | } |
287 | } | 287 | } |
288 | r600_irq_set(rdev); | 288 | if (rdev->irq.installed) |
289 | r600_irq_set(rdev); | ||
289 | } | 290 | } |
290 | 291 | ||
291 | void r600_hpd_fini(struct radeon_device *rdev) | 292 | void r600_hpd_fini(struct radeon_device *rdev) |
@@ -726,6 +727,10 @@ int r600_mc_init(struct radeon_device *rdev) | |||
726 | a.full = rfixed_const(100); | 727 | a.full = rfixed_const(100); |
727 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); | 728 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
728 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | 729 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
730 | |||
731 | if (rdev->flags & RADEON_IS_IGP) | ||
732 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | ||
733 | |||
729 | return 0; | 734 | return 0; |
730 | } | 735 | } |
731 | 736 | ||
@@ -1384,11 +1389,6 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |||
1384 | (void)RREG32(PCIE_PORT_DATA); | 1389 | (void)RREG32(PCIE_PORT_DATA); |
1385 | } | 1390 | } |
1386 | 1391 | ||
1387 | void r600_hdp_flush(struct radeon_device *rdev) | ||
1388 | { | ||
1389 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | ||
1390 | } | ||
1391 | |||
1392 | /* | 1392 | /* |
1393 | * CP & Ring | 1393 | * CP & Ring |
1394 | */ | 1394 | */ |
@@ -1785,6 +1785,8 @@ void r600_fence_ring_emit(struct radeon_device *rdev, | |||
1785 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 1785 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1786 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | 1786 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
1787 | radeon_ring_write(rdev, fence->seq); | 1787 | radeon_ring_write(rdev, fence->seq); |
1788 | radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); | ||
1789 | radeon_ring_write(rdev, 1); | ||
1788 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ | 1790 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
1789 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); | 1791 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); |
1790 | radeon_ring_write(rdev, RB_INT_STAT); | 1792 | radeon_ring_write(rdev, RB_INT_STAT); |
@@ -2089,8 +2091,7 @@ void r600_fini(struct radeon_device *rdev) | |||
2089 | radeon_gem_fini(rdev); | 2091 | radeon_gem_fini(rdev); |
2090 | radeon_fence_driver_fini(rdev); | 2092 | radeon_fence_driver_fini(rdev); |
2091 | radeon_clocks_fini(rdev); | 2093 | radeon_clocks_fini(rdev); |
2092 | if (rdev->flags & RADEON_IS_AGP) | 2094 | radeon_agp_fini(rdev); |
2093 | radeon_agp_fini(rdev); | ||
2094 | radeon_bo_fini(rdev); | 2095 | radeon_bo_fini(rdev); |
2095 | radeon_atombios_fini(rdev); | 2096 | radeon_atombios_fini(rdev); |
2096 | kfree(rdev->bios); | 2097 | kfree(rdev->bios); |
@@ -2461,6 +2462,10 @@ int r600_irq_set(struct radeon_device *rdev) | |||
2461 | u32 mode_int = 0; | 2462 | u32 mode_int = 0; |
2462 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | 2463 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
2463 | 2464 | ||
2465 | if (!rdev->irq.installed) { | ||
2466 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | ||
2467 | return -EINVAL; | ||
2468 | } | ||
2464 | /* don't enable anything if the ih is disabled */ | 2469 | /* don't enable anything if the ih is disabled */ |
2465 | if (!rdev->ih.enabled) | 2470 | if (!rdev->ih.enabled) |
2466 | return 0; | 2471 | return 0; |
@@ -2724,7 +2729,7 @@ restart_ih: | |||
2724 | } | 2729 | } |
2725 | break; | 2730 | break; |
2726 | default: | 2731 | default: |
2727 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | 2732 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2728 | break; | 2733 | break; |
2729 | } | 2734 | } |
2730 | break; | 2735 | break; |
@@ -2744,7 +2749,7 @@ restart_ih: | |||
2744 | } | 2749 | } |
2745 | break; | 2750 | break; |
2746 | default: | 2751 | default: |
2747 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | 2752 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2748 | break; | 2753 | break; |
2749 | } | 2754 | } |
2750 | break; | 2755 | break; |
@@ -2793,7 +2798,7 @@ restart_ih: | |||
2793 | } | 2798 | } |
2794 | break; | 2799 | break; |
2795 | default: | 2800 | default: |
2796 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | 2801 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2797 | break; | 2802 | break; |
2798 | } | 2803 | } |
2799 | break; | 2804 | break; |
@@ -2807,7 +2812,7 @@ restart_ih: | |||
2807 | DRM_DEBUG("IH: CP EOP\n"); | 2812 | DRM_DEBUG("IH: CP EOP\n"); |
2808 | break; | 2813 | break; |
2809 | default: | 2814 | default: |
2810 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | 2815 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
2811 | break; | 2816 | break; |
2812 | } | 2817 | } |
2813 | 2818 | ||