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path: root/drivers/gpu/drm/radeon/r600.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index aa5571b73aa0..720dd99163f8 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2209,7 +2209,8 @@ int r600_cp_resume(struct radeon_device *rdev)
2209 /* Initialize the ring buffer's read and write pointers */ 2209 /* Initialize the ring buffer's read and write pointers */
2210 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2210 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2211 WREG32(CP_RB_RPTR_WR, 0); 2211 WREG32(CP_RB_RPTR_WR, 0);
2212 WREG32(CP_RB_WPTR, 0); 2212 rdev->cp.wptr = 0;
2213 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2213 2214
2214 /* set the wb address whether it's enabled or not */ 2215 /* set the wb address whether it's enabled or not */
2215 WREG32(CP_RB_RPTR_ADDR, 2216 WREG32(CP_RB_RPTR_ADDR,
@@ -2231,7 +2232,6 @@ int r600_cp_resume(struct radeon_device *rdev)
2231 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2232 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2232 2233
2233 rdev->cp.rptr = RREG32(CP_RB_RPTR); 2234 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2234 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2235 2235
2236 r600_cp_start(rdev); 2236 r600_cp_start(rdev);
2237 rdev->cp.ready = true; 2237 rdev->cp.ready = true;
@@ -2353,21 +2353,23 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2353} 2353}
2354 2354
2355int r600_copy_blit(struct radeon_device *rdev, 2355int r600_copy_blit(struct radeon_device *rdev,
2356 uint64_t src_offset, uint64_t dst_offset, 2356 uint64_t src_offset,
2357 unsigned num_pages, struct radeon_fence *fence) 2357 uint64_t dst_offset,
2358 unsigned num_gpu_pages,
2359 struct radeon_fence *fence)
2358{ 2360{
2359 int r; 2361 int r;
2360 2362
2361 mutex_lock(&rdev->r600_blit.mutex); 2363 mutex_lock(&rdev->r600_blit.mutex);
2362 rdev->r600_blit.vb_ib = NULL; 2364 rdev->r600_blit.vb_ib = NULL;
2363 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 2365 r = r600_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
2364 if (r) { 2366 if (r) {
2365 if (rdev->r600_blit.vb_ib) 2367 if (rdev->r600_blit.vb_ib)
2366 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 2368 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2367 mutex_unlock(&rdev->r600_blit.mutex); 2369 mutex_unlock(&rdev->r600_blit.mutex);
2368 return r; 2370 return r;
2369 } 2371 }
2370 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 2372 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
2371 r600_blit_done_copy(rdev, fence); 2373 r600_blit_done_copy(rdev, fence);
2372 mutex_unlock(&rdev->r600_blit.mutex); 2374 mutex_unlock(&rdev->r600_blit.mutex);
2373 return 0; 2375 return 0;