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path: root/drivers/gpu/drm/radeon/r420.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r420.c')
-rw-r--r--drivers/gpu/drm/radeon/r420.c49
1 files changed, 15 insertions, 34 deletions
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index d9373246c97f..c7593b8f58ee 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -40,28 +40,6 @@ static void r420_set_reg_safe(struct radeon_device *rdev)
40 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 40 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
41} 41}
42 42
43int r420_mc_init(struct radeon_device *rdev)
44{
45 int r;
46
47 /* Setup GPU memory space */
48 rdev->mc.vram_location = 0xFFFFFFFFUL;
49 rdev->mc.gtt_location = 0xFFFFFFFFUL;
50 if (rdev->flags & RADEON_IS_AGP) {
51 r = radeon_agp_init(rdev);
52 if (r) {
53 radeon_agp_disable(rdev);
54 } else {
55 rdev->mc.gtt_location = rdev->mc.agp_base;
56 }
57 }
58 r = radeon_mc_setup(rdev);
59 if (r) {
60 return r;
61 }
62 return 0;
63}
64
65void r420_pipes_init(struct radeon_device *rdev) 43void r420_pipes_init(struct radeon_device *rdev)
66{ 44{
67 unsigned tmp; 45 unsigned tmp;
@@ -69,7 +47,8 @@ void r420_pipes_init(struct radeon_device *rdev)
69 unsigned num_pipes; 47 unsigned num_pipes;
70 48
71 /* GA_ENHANCE workaround TCL deadlock issue */ 49 /* GA_ENHANCE workaround TCL deadlock issue */
72 WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); 50 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
51 (1 << 2) | (1 << 3));
73 /* add idle wait as per freedesktop.org bug 24041 */ 52 /* add idle wait as per freedesktop.org bug 24041 */
74 if (r100_gui_wait_for_idle(rdev)) { 53 if (r100_gui_wait_for_idle(rdev)) {
75 printk(KERN_WARNING "Failed to wait GUI idle while " 54 printk(KERN_WARNING "Failed to wait GUI idle while "
@@ -97,17 +76,17 @@ void r420_pipes_init(struct radeon_device *rdev)
97 tmp = (7 << 1); 76 tmp = (7 << 1);
98 break; 77 break;
99 } 78 }
100 WREG32(0x42C8, (1 << num_pipes) - 1); 79 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
101 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 80 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
102 tmp |= (1 << 4) | (1 << 0); 81 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
103 WREG32(0x4018, tmp); 82 WREG32(R300_GB_TILE_CONFIG, tmp);
104 if (r100_gui_wait_for_idle(rdev)) { 83 if (r100_gui_wait_for_idle(rdev)) {
105 printk(KERN_WARNING "Failed to wait GUI idle while " 84 printk(KERN_WARNING "Failed to wait GUI idle while "
106 "programming pipes. Bad things might happen.\n"); 85 "programming pipes. Bad things might happen.\n");
107 } 86 }
108 87
109 tmp = RREG32(0x170C); 88 tmp = RREG32(R300_DST_PIPE_CONFIG);
110 WREG32(0x170C, tmp | (1 << 31)); 89 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
111 90
112 WREG32(R300_RB2D_DSTCACHE_MODE, 91 WREG32(R300_RB2D_DSTCACHE_MODE,
113 RREG32(R300_RB2D_DSTCACHE_MODE) | 92 RREG32(R300_RB2D_DSTCACHE_MODE) |
@@ -348,13 +327,15 @@ int r420_init(struct radeon_device *rdev)
348 radeon_get_clock_info(rdev->ddev); 327 radeon_get_clock_info(rdev->ddev);
349 /* Initialize power management */ 328 /* Initialize power management */
350 radeon_pm_init(rdev); 329 radeon_pm_init(rdev);
351 /* Get vram informations */ 330 /* initialize AGP */
352 r300_vram_info(rdev); 331 if (rdev->flags & RADEON_IS_AGP) {
353 /* Initialize memory controller (also test AGP) */ 332 r = radeon_agp_init(rdev);
354 r = r420_mc_init(rdev); 333 if (r) {
355 if (r) { 334 radeon_agp_disable(rdev);
356 return r; 335 }
357 } 336 }
337 /* initialize memory controller */
338 r300_mc_init(rdev);
358 r420_debugfs(rdev); 339 r420_debugfs(rdev);
359 /* Fence driver */ 340 /* Fence driver */
360 r = radeon_fence_driver_init(rdev); 341 r = radeon_fence_driver_init(rdev);