diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r300.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 106 |
1 files changed, 83 insertions, 23 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index c827738ad7dd..55a7f190027e 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -69,6 +69,9 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) | |||
69 | mb(); | 69 | mb(); |
70 | } | 70 | } |
71 | 71 | ||
72 | #define R300_PTE_WRITEABLE (1 << 2) | ||
73 | #define R300_PTE_READABLE (1 << 3) | ||
74 | |||
72 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | 75 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
73 | { | 76 | { |
74 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | 77 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
@@ -78,7 +81,7 @@ int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |||
78 | } | 81 | } |
79 | addr = (lower_32_bits(addr) >> 8) | | 82 | addr = (lower_32_bits(addr) >> 8) | |
80 | ((upper_32_bits(addr) & 0xff) << 24) | | 83 | ((upper_32_bits(addr) & 0xff) << 24) | |
81 | 0xc; | 84 | R300_PTE_WRITEABLE | R300_PTE_READABLE; |
82 | /* on x86 we want this to be CPU endian, on powerpc | 85 | /* on x86 we want this to be CPU endian, on powerpc |
83 | * on powerpc without HW swappers, it'll get swapped on way | 86 | * on powerpc without HW swappers, it'll get swapped on way |
84 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ | 87 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ |
@@ -91,7 +94,7 @@ int rv370_pcie_gart_init(struct radeon_device *rdev) | |||
91 | int r; | 94 | int r; |
92 | 95 | ||
93 | if (rdev->gart.table.vram.robj) { | 96 | if (rdev->gart.table.vram.robj) { |
94 | WARN(1, "RV370 PCIE GART already initialized.\n"); | 97 | WARN(1, "RV370 PCIE GART already initialized\n"); |
95 | return 0; | 98 | return 0; |
96 | } | 99 | } |
97 | /* Initialize common gart structure */ | 100 | /* Initialize common gart structure */ |
@@ -135,7 +138,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) | |||
135 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); | 138 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
136 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); | 139 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
137 | /* Clear error */ | 140 | /* Clear error */ |
138 | WREG32_PCIE(0x18, 0); | 141 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
139 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | 142 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
140 | tmp |= RADEON_PCIE_TX_GART_EN; | 143 | tmp |= RADEON_PCIE_TX_GART_EN; |
141 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | 144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; |
@@ -405,12 +408,13 @@ int r300_asic_reset(struct radeon_device *rdev) | |||
405 | { | 408 | { |
406 | struct r100_mc_save save; | 409 | struct r100_mc_save save; |
407 | u32 status, tmp; | 410 | u32 status, tmp; |
411 | int ret = 0; | ||
408 | 412 | ||
409 | r100_mc_stop(rdev, &save); | ||
410 | status = RREG32(R_000E40_RBBM_STATUS); | 413 | status = RREG32(R_000E40_RBBM_STATUS); |
411 | if (!G_000E40_GUI_ACTIVE(status)) { | 414 | if (!G_000E40_GUI_ACTIVE(status)) { |
412 | return 0; | 415 | return 0; |
413 | } | 416 | } |
417 | r100_mc_stop(rdev, &save); | ||
414 | status = RREG32(R_000E40_RBBM_STATUS); | 418 | status = RREG32(R_000E40_RBBM_STATUS); |
415 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | 419 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
416 | /* stop CP */ | 420 | /* stop CP */ |
@@ -433,7 +437,7 @@ int r300_asic_reset(struct radeon_device *rdev) | |||
433 | status = RREG32(R_000E40_RBBM_STATUS); | 437 | status = RREG32(R_000E40_RBBM_STATUS); |
434 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | 438 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
435 | /* resetting the CP seems to be problematic sometimes it end up | 439 | /* resetting the CP seems to be problematic sometimes it end up |
436 | * hard locking the computer, but it's necessary for successfull | 440 | * hard locking the computer, but it's necessary for successful |
437 | * reset more test & playing is needed on R3XX/R4XX to find a | 441 | * reset more test & playing is needed on R3XX/R4XX to find a |
438 | * reliable (if any solution) | 442 | * reliable (if any solution) |
439 | */ | 443 | */ |
@@ -451,11 +455,11 @@ int r300_asic_reset(struct radeon_device *rdev) | |||
451 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { | 455 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
452 | dev_err(rdev->dev, "failed to reset GPU\n"); | 456 | dev_err(rdev->dev, "failed to reset GPU\n"); |
453 | rdev->gpu_lockup = true; | 457 | rdev->gpu_lockup = true; |
454 | return -1; | 458 | ret = -1; |
455 | } | 459 | } else |
460 | dev_info(rdev->dev, "GPU reset succeed\n"); | ||
456 | r100_mc_resume(rdev, &save); | 461 | r100_mc_resume(rdev, &save); |
457 | dev_info(rdev->dev, "GPU reset succeed\n"); | 462 | return ret; |
458 | return 0; | ||
459 | } | 463 | } |
460 | 464 | ||
461 | /* | 465 | /* |
@@ -558,10 +562,7 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev) | |||
558 | 562 | ||
559 | /* FIXME wait for idle */ | 563 | /* FIXME wait for idle */ |
560 | 564 | ||
561 | if (rdev->family < CHIP_R600) | 565 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
562 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | ||
563 | else | ||
564 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | ||
565 | 566 | ||
566 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { | 567 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { |
567 | case RADEON_PCIE_LC_LINK_WIDTH_X0: | 568 | case RADEON_PCIE_LC_LINK_WIDTH_X0: |
@@ -666,6 +667,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
666 | } | 667 | } |
667 | track->cb[i].robj = reloc->robj; | 668 | track->cb[i].robj = reloc->robj; |
668 | track->cb[i].offset = idx_value; | 669 | track->cb[i].offset = idx_value; |
670 | track->cb_dirty = true; | ||
669 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 671 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
670 | break; | 672 | break; |
671 | case R300_ZB_DEPTHOFFSET: | 673 | case R300_ZB_DEPTHOFFSET: |
@@ -678,6 +680,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
678 | } | 680 | } |
679 | track->zb.robj = reloc->robj; | 681 | track->zb.robj = reloc->robj; |
680 | track->zb.offset = idx_value; | 682 | track->zb.offset = idx_value; |
683 | track->zb_dirty = true; | ||
681 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 684 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
682 | break; | 685 | break; |
683 | case R300_TX_OFFSET_0: | 686 | case R300_TX_OFFSET_0: |
@@ -716,6 +719,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
716 | tmp |= tile_flags; | 719 | tmp |= tile_flags; |
717 | ib[idx] = tmp; | 720 | ib[idx] = tmp; |
718 | track->textures[i].robj = reloc->robj; | 721 | track->textures[i].robj = reloc->robj; |
722 | track->tex_dirty = true; | ||
719 | break; | 723 | break; |
720 | /* Tracked registers */ | 724 | /* Tracked registers */ |
721 | case 0x2084: | 725 | case 0x2084: |
@@ -742,10 +746,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
742 | if (p->rdev->family < CHIP_RV515) { | 746 | if (p->rdev->family < CHIP_RV515) { |
743 | track->maxy -= 1440; | 747 | track->maxy -= 1440; |
744 | } | 748 | } |
749 | track->cb_dirty = true; | ||
750 | track->zb_dirty = true; | ||
745 | break; | 751 | break; |
746 | case 0x4E00: | 752 | case 0x4E00: |
747 | /* RB3D_CCTL */ | 753 | /* RB3D_CCTL */ |
754 | if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ | ||
755 | p->rdev->cmask_filp != p->filp) { | ||
756 | DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); | ||
757 | return -EINVAL; | ||
758 | } | ||
748 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; | 759 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
760 | track->cb_dirty = true; | ||
749 | break; | 761 | break; |
750 | case 0x4E38: | 762 | case 0x4E38: |
751 | case 0x4E3C: | 763 | case 0x4E3C: |
@@ -787,6 +799,13 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
787 | case 15: | 799 | case 15: |
788 | track->cb[i].cpp = 2; | 800 | track->cb[i].cpp = 2; |
789 | break; | 801 | break; |
802 | case 5: | ||
803 | if (p->rdev->family < CHIP_RV515) { | ||
804 | DRM_ERROR("Invalid color buffer format (%d)!\n", | ||
805 | ((idx_value >> 21) & 0xF)); | ||
806 | return -EINVAL; | ||
807 | } | ||
808 | /* Pass through. */ | ||
790 | case 6: | 809 | case 6: |
791 | track->cb[i].cpp = 4; | 810 | track->cb[i].cpp = 4; |
792 | break; | 811 | break; |
@@ -801,6 +820,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
801 | ((idx_value >> 21) & 0xF)); | 820 | ((idx_value >> 21) & 0xF)); |
802 | return -EINVAL; | 821 | return -EINVAL; |
803 | } | 822 | } |
823 | track->cb_dirty = true; | ||
804 | break; | 824 | break; |
805 | case 0x4F00: | 825 | case 0x4F00: |
806 | /* ZB_CNTL */ | 826 | /* ZB_CNTL */ |
@@ -809,6 +829,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
809 | } else { | 829 | } else { |
810 | track->z_enabled = false; | 830 | track->z_enabled = false; |
811 | } | 831 | } |
832 | track->zb_dirty = true; | ||
812 | break; | 833 | break; |
813 | case 0x4F10: | 834 | case 0x4F10: |
814 | /* ZB_FORMAT */ | 835 | /* ZB_FORMAT */ |
@@ -825,6 +846,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
825 | (idx_value & 0xF)); | 846 | (idx_value & 0xF)); |
826 | return -EINVAL; | 847 | return -EINVAL; |
827 | } | 848 | } |
849 | track->zb_dirty = true; | ||
828 | break; | 850 | break; |
829 | case 0x4F24: | 851 | case 0x4F24: |
830 | /* ZB_DEPTHPITCH */ | 852 | /* ZB_DEPTHPITCH */ |
@@ -848,14 +870,17 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
848 | ib[idx] = tmp; | 870 | ib[idx] = tmp; |
849 | 871 | ||
850 | track->zb.pitch = idx_value & 0x3FFC; | 872 | track->zb.pitch = idx_value & 0x3FFC; |
873 | track->zb_dirty = true; | ||
851 | break; | 874 | break; |
852 | case 0x4104: | 875 | case 0x4104: |
876 | /* TX_ENABLE */ | ||
853 | for (i = 0; i < 16; i++) { | 877 | for (i = 0; i < 16; i++) { |
854 | bool enabled; | 878 | bool enabled; |
855 | 879 | ||
856 | enabled = !!(idx_value & (1 << i)); | 880 | enabled = !!(idx_value & (1 << i)); |
857 | track->textures[i].enabled = enabled; | 881 | track->textures[i].enabled = enabled; |
858 | } | 882 | } |
883 | track->tex_dirty = true; | ||
859 | break; | 884 | break; |
860 | case 0x44C0: | 885 | case 0x44C0: |
861 | case 0x44C4: | 886 | case 0x44C4: |
@@ -885,6 +910,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
885 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; | 910 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
886 | break; | 911 | break; |
887 | case R300_TX_FORMAT_X16: | 912 | case R300_TX_FORMAT_X16: |
913 | case R300_TX_FORMAT_FL_I16: | ||
888 | case R300_TX_FORMAT_Y8X8: | 914 | case R300_TX_FORMAT_Y8X8: |
889 | case R300_TX_FORMAT_Z5Y6X5: | 915 | case R300_TX_FORMAT_Z5Y6X5: |
890 | case R300_TX_FORMAT_Z6Y5X5: | 916 | case R300_TX_FORMAT_Z6Y5X5: |
@@ -897,6 +923,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
897 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; | 923 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
898 | break; | 924 | break; |
899 | case R300_TX_FORMAT_Y16X16: | 925 | case R300_TX_FORMAT_Y16X16: |
926 | case R300_TX_FORMAT_FL_I16A16: | ||
900 | case R300_TX_FORMAT_Z11Y11X10: | 927 | case R300_TX_FORMAT_Z11Y11X10: |
901 | case R300_TX_FORMAT_Z10Y11X11: | 928 | case R300_TX_FORMAT_Z10Y11X11: |
902 | case R300_TX_FORMAT_W8Z8Y8X8: | 929 | case R300_TX_FORMAT_W8Z8Y8X8: |
@@ -938,8 +965,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
938 | DRM_ERROR("Invalid texture format %u\n", | 965 | DRM_ERROR("Invalid texture format %u\n", |
939 | (idx_value & 0x1F)); | 966 | (idx_value & 0x1F)); |
940 | return -EINVAL; | 967 | return -EINVAL; |
941 | break; | ||
942 | } | 968 | } |
969 | track->tex_dirty = true; | ||
943 | break; | 970 | break; |
944 | case 0x4400: | 971 | case 0x4400: |
945 | case 0x4404: | 972 | case 0x4404: |
@@ -967,6 +994,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
967 | if (tmp == 2 || tmp == 4 || tmp == 6) { | 994 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
968 | track->textures[i].roundup_h = false; | 995 | track->textures[i].roundup_h = false; |
969 | } | 996 | } |
997 | track->tex_dirty = true; | ||
970 | break; | 998 | break; |
971 | case 0x4500: | 999 | case 0x4500: |
972 | case 0x4504: | 1000 | case 0x4504: |
@@ -1004,6 +1032,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1004 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); | 1032 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); |
1005 | return -EINVAL; | 1033 | return -EINVAL; |
1006 | } | 1034 | } |
1035 | track->tex_dirty = true; | ||
1007 | break; | 1036 | break; |
1008 | case 0x4480: | 1037 | case 0x4480: |
1009 | case 0x4484: | 1038 | case 0x4484: |
@@ -1033,6 +1062,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1033 | track->textures[i].use_pitch = !!tmp; | 1062 | track->textures[i].use_pitch = !!tmp; |
1034 | tmp = (idx_value >> 22) & 0xF; | 1063 | tmp = (idx_value >> 22) & 0xF; |
1035 | track->textures[i].txdepth = tmp; | 1064 | track->textures[i].txdepth = tmp; |
1065 | track->tex_dirty = true; | ||
1036 | break; | 1066 | break; |
1037 | case R300_ZB_ZPASS_ADDR: | 1067 | case R300_ZB_ZPASS_ADDR: |
1038 | r = r100_cs_packet_next_reloc(p, &reloc); | 1068 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1047,6 +1077,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1047 | case 0x4e0c: | 1077 | case 0x4e0c: |
1048 | /* RB3D_COLOR_CHANNEL_MASK */ | 1078 | /* RB3D_COLOR_CHANNEL_MASK */ |
1049 | track->color_channel_mask = idx_value; | 1079 | track->color_channel_mask = idx_value; |
1080 | track->cb_dirty = true; | ||
1050 | break; | 1081 | break; |
1051 | case 0x43a4: | 1082 | case 0x43a4: |
1052 | /* SC_HYPERZ_EN */ | 1083 | /* SC_HYPERZ_EN */ |
@@ -1060,6 +1091,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1060 | case 0x4f1c: | 1091 | case 0x4f1c: |
1061 | /* ZB_BW_CNTL */ | 1092 | /* ZB_BW_CNTL */ |
1062 | track->zb_cb_clear = !!(idx_value & (1 << 5)); | 1093 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
1094 | track->cb_dirty = true; | ||
1095 | track->zb_dirty = true; | ||
1063 | if (p->rdev->hyperz_filp != p->filp) { | 1096 | if (p->rdev->hyperz_filp != p->filp) { |
1064 | if (idx_value & (R300_HIZ_ENABLE | | 1097 | if (idx_value & (R300_HIZ_ENABLE | |
1065 | R300_RD_COMP_ENABLE | | 1098 | R300_RD_COMP_ENABLE | |
@@ -1071,8 +1104,28 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1071 | case 0x4e04: | 1104 | case 0x4e04: |
1072 | /* RB3D_BLENDCNTL */ | 1105 | /* RB3D_BLENDCNTL */ |
1073 | track->blend_read_enable = !!(idx_value & (1 << 2)); | 1106 | track->blend_read_enable = !!(idx_value & (1 << 2)); |
1107 | track->cb_dirty = true; | ||
1108 | break; | ||
1109 | case R300_RB3D_AARESOLVE_OFFSET: | ||
1110 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1111 | if (r) { | ||
1112 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
1113 | idx, reg); | ||
1114 | r100_cs_dump_packet(p, pkt); | ||
1115 | return r; | ||
1116 | } | ||
1117 | track->aa.robj = reloc->robj; | ||
1118 | track->aa.offset = idx_value; | ||
1119 | track->aa_dirty = true; | ||
1120 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | ||
1121 | break; | ||
1122 | case R300_RB3D_AARESOLVE_PITCH: | ||
1123 | track->aa.pitch = idx_value & 0x3FFE; | ||
1124 | track->aa_dirty = true; | ||
1074 | break; | 1125 | break; |
1075 | case 0x4f28: /* ZB_DEPTHCLEARVALUE */ | 1126 | case R300_RB3D_AARESOLVE_CTL: |
1127 | track->aaresolve = idx_value & 0x1; | ||
1128 | track->aa_dirty = true; | ||
1076 | break; | 1129 | break; |
1077 | case 0x4f30: /* ZB_MASK_OFFSET */ | 1130 | case 0x4f30: /* ZB_MASK_OFFSET */ |
1078 | case 0x4f34: /* ZB_ZMASK_PITCH */ | 1131 | case 0x4f34: /* ZB_ZMASK_PITCH */ |
@@ -1199,6 +1252,10 @@ static int r300_packet3_check(struct radeon_cs_parser *p, | |||
1199 | if (p->rdev->hyperz_filp != p->filp) | 1252 | if (p->rdev->hyperz_filp != p->filp) |
1200 | return -EINVAL; | 1253 | return -EINVAL; |
1201 | break; | 1254 | break; |
1255 | case PACKET3_3D_CLEAR_CMASK: | ||
1256 | if (p->rdev->cmask_filp != p->filp) | ||
1257 | return -EINVAL; | ||
1258 | break; | ||
1202 | case PACKET3_NOP: | 1259 | case PACKET3_NOP: |
1203 | break; | 1260 | break; |
1204 | default: | 1261 | default: |
@@ -1332,21 +1389,24 @@ static int r300_startup(struct radeon_device *rdev) | |||
1332 | if (r) | 1389 | if (r) |
1333 | return r; | 1390 | return r; |
1334 | } | 1391 | } |
1392 | |||
1393 | /* allocate wb buffer */ | ||
1394 | r = radeon_wb_init(rdev); | ||
1395 | if (r) | ||
1396 | return r; | ||
1397 | |||
1335 | /* Enable IRQ */ | 1398 | /* Enable IRQ */ |
1336 | r100_irq_set(rdev); | 1399 | r100_irq_set(rdev); |
1337 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); | 1400 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1338 | /* 1M ring buffer */ | 1401 | /* 1M ring buffer */ |
1339 | r = r100_cp_init(rdev, 1024 * 1024); | 1402 | r = r100_cp_init(rdev, 1024 * 1024); |
1340 | if (r) { | 1403 | if (r) { |
1341 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | 1404 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1342 | return r; | 1405 | return r; |
1343 | } | 1406 | } |
1344 | r = r100_wb_init(rdev); | ||
1345 | if (r) | ||
1346 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | ||
1347 | r = r100_ib_init(rdev); | 1407 | r = r100_ib_init(rdev); |
1348 | if (r) { | 1408 | if (r) { |
1349 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | 1409 | dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
1350 | return r; | 1410 | return r; |
1351 | } | 1411 | } |
1352 | return 0; | 1412 | return 0; |
@@ -1379,7 +1439,7 @@ int r300_resume(struct radeon_device *rdev) | |||
1379 | int r300_suspend(struct radeon_device *rdev) | 1439 | int r300_suspend(struct radeon_device *rdev) |
1380 | { | 1440 | { |
1381 | r100_cp_disable(rdev); | 1441 | r100_cp_disable(rdev); |
1382 | r100_wb_disable(rdev); | 1442 | radeon_wb_disable(rdev); |
1383 | r100_irq_disable(rdev); | 1443 | r100_irq_disable(rdev); |
1384 | if (rdev->flags & RADEON_IS_PCIE) | 1444 | if (rdev->flags & RADEON_IS_PCIE) |
1385 | rv370_pcie_gart_disable(rdev); | 1445 | rv370_pcie_gart_disable(rdev); |
@@ -1391,7 +1451,7 @@ int r300_suspend(struct radeon_device *rdev) | |||
1391 | void r300_fini(struct radeon_device *rdev) | 1451 | void r300_fini(struct radeon_device *rdev) |
1392 | { | 1452 | { |
1393 | r100_cp_fini(rdev); | 1453 | r100_cp_fini(rdev); |
1394 | r100_wb_fini(rdev); | 1454 | radeon_wb_fini(rdev); |
1395 | r100_ib_fini(rdev); | 1455 | r100_ib_fini(rdev); |
1396 | radeon_gem_fini(rdev); | 1456 | radeon_gem_fini(rdev); |
1397 | if (rdev->flags & RADEON_IS_PCIE) | 1457 | if (rdev->flags & RADEON_IS_PCIE) |
@@ -1484,7 +1544,7 @@ int r300_init(struct radeon_device *rdev) | |||
1484 | /* Somethings want wront with the accel init stop accel */ | 1544 | /* Somethings want wront with the accel init stop accel */ |
1485 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | 1545 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
1486 | r100_cp_fini(rdev); | 1546 | r100_cp_fini(rdev); |
1487 | r100_wb_fini(rdev); | 1547 | radeon_wb_fini(rdev); |
1488 | r100_ib_fini(rdev); | 1548 | r100_ib_fini(rdev); |
1489 | radeon_irq_kms_fini(rdev); | 1549 | radeon_irq_kms_fini(rdev); |
1490 | if (rdev->flags & RADEON_IS_PCIE) | 1550 | if (rdev->flags & RADEON_IS_PCIE) |