1 files changed, 79 insertions, 30 deletions

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 333cde9d4e7b..81801c176aa5 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -65,6 +65,40 @@ MODULE_FIRMWARE(FIRMWARE_R520);
 
 #include "r100_track.h"
 
+void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
+{
+        struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
+        int i;
+
+        if (radeon_crtc->crtc_id == 0) {
+                if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
+                        for (i = 0; i < rdev->usec_timeout; i++) {
+                                if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
+                                        break;
+                                udelay(1);
+                        }
+                        for (i = 0; i < rdev->usec_timeout; i++) {
+                                if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
+                                        break;
+                                udelay(1);
+                        }
+                }
+        } else {
+                if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
+                        for (i = 0; i < rdev->usec_timeout; i++) {
+                                if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
+                                        break;
+                                udelay(1);
+                        }
+                        for (i = 0; i < rdev->usec_timeout; i++) {
+                                if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
+                                        break;
+                                udelay(1);
+                        }
+                }
+        }
+}
+
 /* This files gather functions specifics to:
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  */
@@ -87,23 +121,27 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
                 r100_cs_dump_packet(p, pkt);
                 return r;
         }
+
         value = radeon_get_ib_value(p, idx);
         tmp = value & 0x003fffff;
         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
 
-        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                tile_flags |= RADEON_DST_TILE_MACRO;
-        if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
-                if (reg == RADEON_SRC_PITCH_OFFSET) {
-                        DRM_ERROR("Cannot src blit from microtiled surface\n");
-                        r100_cs_dump_packet(p, pkt);
-                        return -EINVAL;
+        if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
+                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                        tile_flags |= RADEON_DST_TILE_MACRO;
+                if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+                        if (reg == RADEON_SRC_PITCH_OFFSET) {
+                                DRM_ERROR("Cannot src blit from microtiled surface\n");
+                                r100_cs_dump_packet(p, pkt);
+                                return -EINVAL;
+                        }
+                        tile_flags |= RADEON_DST_TILE_MICRO;
                 }
-                tile_flags |= RADEON_DST_TILE_MICRO;
-        }
 
-        tmp |= tile_flags;
-        p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
+                tmp |= tile_flags;
+                p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
+        } else
+                p->ib->ptr[idx] = (value & 0xffc00000) | tmp;
         return 0;
 }
 
@@ -412,7 +450,7 @@ void r100_pm_misc(struct radeon_device *rdev)
         /* set pcie lanes */
         if ((rdev->flags & RADEON_IS_PCIE) &&
             !(rdev->flags & RADEON_IS_IGP) &&
-            rdev->asic->set_pcie_lanes &&
+            rdev->asic->pm.set_pcie_lanes &&
             (ps->pcie_lanes !=
              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
                 radeon_set_pcie_lanes(rdev,
@@ -592,8 +630,8 @@ int r100_pci_gart_init(struct radeon_device *rdev)
         if (r)
                 return r;
         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
-        rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
-        rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+        rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
+        rdev->asic->gart.set_page = &r100_pci_gart_set_page;
         return radeon_gart_table_ram_alloc(rdev);
 }
 
@@ -930,9 +968,8 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev)
         return -1;
 }
 
-void r100_ring_start(struct radeon_device *rdev)
+void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 {
-        struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         int r;
 
         r = radeon_ring_lock(rdev, ring, 2);
@@ -1143,8 +1180,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
-        radeon_ring_start(rdev);
-        r = radeon_ring_test(rdev, ring);
+        radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
+        r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
         if (r) {
                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
                 return r;
@@ -1552,7 +1589,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                         r100_cs_dump_packet(p, pkt);
                         return r;
                 }
-                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                tile_flags |= RADEON_TXO_MACRO_TILE;
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                tile_flags |= RADEON_TXO_MICRO_TILE_X2;
+
+                        tmp = idx_value & ~(0x7 << 2);
+                        tmp |= tile_flags;
+                        ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
+                } else
+                        ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 track->textures[i].robj = reloc->robj;
                 track->tex_dirty = true;
                 break;
@@ -1623,15 +1670,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                         r100_cs_dump_packet(p, pkt);
                         return r;
                 }
-
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                        tile_flags |= RADEON_COLOR_TILE_ENABLE;
-                if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                        tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
-
-                tmp = idx_value & ~(0x7 << 16);
-                tmp |= tile_flags;
-                ib[idx] = tmp;
+                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                tile_flags |= RADEON_COLOR_TILE_ENABLE;
+                        if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
+
+                        tmp = idx_value & ~(0x7 << 16);
+                        tmp |= tile_flags;
+                        ib[idx] = tmp;
+                } else
+                        ib[idx] = idx_value;
 
                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
                 track->cb_dirty = true;
@@ -3691,7 +3740,7 @@ void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
         radeon_ring_write(ring, ib->length_dw);
 }
 
-int r100_ib_test(struct radeon_device *rdev)
+int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
 {
         struct radeon_ib *ib;
         uint32_t scratch;
@@ -3916,7 +3965,7 @@ static int r100_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = r100_ib_test(rdev);
+        r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
         if (r) {
                 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
                 rdev->accel_working = false;