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path: root/drivers/gpu/drm/radeon/r100.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c25
1 files changed, 19 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 91eb762eb3f9..3ae51ada1abf 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -31,6 +31,7 @@
31#include "radeon_drm.h" 31#include "radeon_drm.h"
32#include "radeon_reg.h" 32#include "radeon_reg.h"
33#include "radeon.h" 33#include "radeon.h"
34#include "radeon_asic.h"
34#include "r100d.h" 35#include "r100d.h"
35#include "rs100d.h" 36#include "rs100d.h"
36#include "rv200d.h" 37#include "rv200d.h"
@@ -235,9 +236,9 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
235 236
236void r100_pci_gart_fini(struct radeon_device *rdev) 237void r100_pci_gart_fini(struct radeon_device *rdev)
237{ 238{
239 radeon_gart_fini(rdev);
238 r100_pci_gart_disable(rdev); 240 r100_pci_gart_disable(rdev);
239 radeon_gart_table_ram_free(rdev); 241 radeon_gart_table_ram_free(rdev);
240 radeon_gart_fini(rdev);
241} 242}
242 243
243int r100_irq_set(struct radeon_device *rdev) 244int r100_irq_set(struct radeon_device *rdev)
@@ -312,10 +313,12 @@ int r100_irq_process(struct radeon_device *rdev)
312 /* Vertical blank interrupts */ 313 /* Vertical blank interrupts */
313 if (status & RADEON_CRTC_VBLANK_STAT) { 314 if (status & RADEON_CRTC_VBLANK_STAT) {
314 drm_handle_vblank(rdev->ddev, 0); 315 drm_handle_vblank(rdev->ddev, 0);
316 rdev->pm.vblank_sync = true;
315 wake_up(&rdev->irq.vblank_queue); 317 wake_up(&rdev->irq.vblank_queue);
316 } 318 }
317 if (status & RADEON_CRTC2_VBLANK_STAT) { 319 if (status & RADEON_CRTC2_VBLANK_STAT) {
318 drm_handle_vblank(rdev->ddev, 1); 320 drm_handle_vblank(rdev->ddev, 1);
321 rdev->pm.vblank_sync = true;
319 wake_up(&rdev->irq.vblank_queue); 322 wake_up(&rdev->irq.vblank_queue);
320 } 323 }
321 if (status & RADEON_FP_DETECT_STAT) { 324 if (status & RADEON_FP_DETECT_STAT) {
@@ -741,6 +744,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
741 udelay(10); 744 udelay(10);
742 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 745 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
743 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); 746 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
747 /* protect against crazy HW on resume */
748 rdev->cp.wptr &= rdev->cp.ptr_mask;
744 /* Set cp mode to bus mastering & enable cp*/ 749 /* Set cp mode to bus mastering & enable cp*/
745 WREG32(RADEON_CP_CSQ_MODE, 750 WREG32(RADEON_CP_CSQ_MODE,
746 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 751 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -1804,6 +1809,7 @@ void r100_set_common_regs(struct radeon_device *rdev)
1804{ 1809{
1805 struct drm_device *dev = rdev->ddev; 1810 struct drm_device *dev = rdev->ddev;
1806 bool force_dac2 = false; 1811 bool force_dac2 = false;
1812 u32 tmp;
1807 1813
1808 /* set these so they don't interfere with anything */ 1814 /* set these so they don't interfere with anything */
1809 WREG32(RADEON_OV0_SCALE_CNTL, 0); 1815 WREG32(RADEON_OV0_SCALE_CNTL, 0);
@@ -1875,6 +1881,12 @@ void r100_set_common_regs(struct radeon_device *rdev)
1875 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1881 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1876 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1882 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1877 } 1883 }
1884
1885 /* switch PM block to ACPI mode */
1886 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1887 tmp &= ~RADEON_PM_MODE_SEL;
1888 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1889
1878} 1890}
1879 1891
1880/* 1892/*
@@ -2022,6 +2034,7 @@ void r100_mc_init(struct radeon_device *rdev)
2022 radeon_vram_location(rdev, &rdev->mc, base); 2034 radeon_vram_location(rdev, &rdev->mc, base);
2023 if (!(rdev->flags & RADEON_IS_AGP)) 2035 if (!(rdev->flags & RADEON_IS_AGP))
2024 radeon_gtt_location(rdev, &rdev->mc); 2036 radeon_gtt_location(rdev, &rdev->mc);
2037 radeon_update_bandwidth_info(rdev);
2025} 2038}
2026 2039
2027 2040
@@ -2385,6 +2398,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2385 uint32_t pixel_bytes1 = 0; 2398 uint32_t pixel_bytes1 = 0;
2386 uint32_t pixel_bytes2 = 0; 2399 uint32_t pixel_bytes2 = 0;
2387 2400
2401 radeon_update_display_priority(rdev);
2402
2388 if (rdev->mode_info.crtcs[0]->base.enabled) { 2403 if (rdev->mode_info.crtcs[0]->base.enabled) {
2389 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2404 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2390 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2405 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
@@ -2413,11 +2428,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2413 /* 2428 /*
2414 * determine is there is enough bw for current mode 2429 * determine is there is enough bw for current mode
2415 */ 2430 */
2416 mclk_ff.full = rfixed_const(rdev->clock.default_mclk); 2431 sclk_ff = rdev->pm.sclk;
2417 temp_ff.full = rfixed_const(100); 2432 mclk_ff = rdev->pm.mclk;
2418 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2419 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2420 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2421 2433
2422 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2434 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2423 temp_ff.full = rfixed_const(temp); 2435 temp_ff.full = rfixed_const(temp);
@@ -3440,6 +3452,7 @@ int r100_suspend(struct radeon_device *rdev)
3440 3452
3441void r100_fini(struct radeon_device *rdev) 3453void r100_fini(struct radeon_device *rdev)
3442{ 3454{
3455 radeon_pm_fini(rdev);
3443 r100_cp_fini(rdev); 3456 r100_cp_fini(rdev);
3444 r100_wb_fini(rdev); 3457 r100_wb_fini(rdev);
3445 r100_ib_fini(rdev); 3458 r100_ib_fini(rdev);