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path: root/drivers/gpu/drm/radeon/r100.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c544
1 files changed, 408 insertions, 136 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index c9e93eabcf16..cf60c0b3ef15 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -26,11 +26,13 @@
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#include <linux/seq_file.h> 28#include <linux/seq_file.h>
29#include <linux/slab.h>
29#include "drmP.h" 30#include "drmP.h"
30#include "drm.h" 31#include "drm.h"
31#include "radeon_drm.h" 32#include "radeon_drm.h"
32#include "radeon_reg.h" 33#include "radeon_reg.h"
33#include "radeon.h" 34#include "radeon.h"
35#include "radeon_asic.h"
34#include "r100d.h" 36#include "r100d.h"
35#include "rs100d.h" 37#include "rs100d.h"
36#include "rv200d.h" 38#include "rv200d.h"
@@ -65,6 +67,96 @@ MODULE_FIRMWARE(FIRMWARE_R520);
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
66 */ 68 */
67 69
70/* hpd for digital panel detect/disconnect */
71bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
72{
73 bool connected = false;
74
75 switch (hpd) {
76 case RADEON_HPD_1:
77 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
78 connected = true;
79 break;
80 case RADEON_HPD_2:
81 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
82 connected = true;
83 break;
84 default:
85 break;
86 }
87 return connected;
88}
89
90void r100_hpd_set_polarity(struct radeon_device *rdev,
91 enum radeon_hpd_id hpd)
92{
93 u32 tmp;
94 bool connected = r100_hpd_sense(rdev, hpd);
95
96 switch (hpd) {
97 case RADEON_HPD_1:
98 tmp = RREG32(RADEON_FP_GEN_CNTL);
99 if (connected)
100 tmp &= ~RADEON_FP_DETECT_INT_POL;
101 else
102 tmp |= RADEON_FP_DETECT_INT_POL;
103 WREG32(RADEON_FP_GEN_CNTL, tmp);
104 break;
105 case RADEON_HPD_2:
106 tmp = RREG32(RADEON_FP2_GEN_CNTL);
107 if (connected)
108 tmp &= ~RADEON_FP2_DETECT_INT_POL;
109 else
110 tmp |= RADEON_FP2_DETECT_INT_POL;
111 WREG32(RADEON_FP2_GEN_CNTL, tmp);
112 break;
113 default:
114 break;
115 }
116}
117
118void r100_hpd_init(struct radeon_device *rdev)
119{
120 struct drm_device *dev = rdev->ddev;
121 struct drm_connector *connector;
122
123 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
124 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
125 switch (radeon_connector->hpd.hpd) {
126 case RADEON_HPD_1:
127 rdev->irq.hpd[0] = true;
128 break;
129 case RADEON_HPD_2:
130 rdev->irq.hpd[1] = true;
131 break;
132 default:
133 break;
134 }
135 }
136 if (rdev->irq.installed)
137 r100_irq_set(rdev);
138}
139
140void r100_hpd_fini(struct radeon_device *rdev)
141{
142 struct drm_device *dev = rdev->ddev;
143 struct drm_connector *connector;
144
145 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
146 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
147 switch (radeon_connector->hpd.hpd) {
148 case RADEON_HPD_1:
149 rdev->irq.hpd[0] = false;
150 break;
151 case RADEON_HPD_2:
152 rdev->irq.hpd[1] = false;
153 break;
154 default:
155 break;
156 }
157 }
158}
159
68/* 160/*
69 * PCI GART 161 * PCI GART
70 */ 162 */
@@ -94,20 +186,26 @@ int r100_pci_gart_init(struct radeon_device *rdev)
94 return radeon_gart_table_ram_alloc(rdev); 186 return radeon_gart_table_ram_alloc(rdev);
95} 187}
96 188
189/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
190void r100_enable_bm(struct radeon_device *rdev)
191{
192 uint32_t tmp;
193 /* Enable bus mastering */
194 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
195 WREG32(RADEON_BUS_CNTL, tmp);
196}
197
97int r100_pci_gart_enable(struct radeon_device *rdev) 198int r100_pci_gart_enable(struct radeon_device *rdev)
98{ 199{
99 uint32_t tmp; 200 uint32_t tmp;
100 201
202 radeon_gart_restore(rdev);
101 /* discard memory request outside of configured range */ 203 /* discard memory request outside of configured range */
102 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 204 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
103 WREG32(RADEON_AIC_CNTL, tmp); 205 WREG32(RADEON_AIC_CNTL, tmp);
104 /* set address range for PCI address translate */ 206 /* set address range for PCI address translate */
105 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); 207 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
106 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 208 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
107 WREG32(RADEON_AIC_HI_ADDR, tmp);
108 /* Enable bus mastering */
109 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
110 WREG32(RADEON_BUS_CNTL, tmp);
111 /* set PCI GART page-table base address */ 209 /* set PCI GART page-table base address */
112 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 210 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
113 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 211 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
@@ -139,15 +237,20 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
139 237
140void r100_pci_gart_fini(struct radeon_device *rdev) 238void r100_pci_gart_fini(struct radeon_device *rdev)
141{ 239{
240 radeon_gart_fini(rdev);
142 r100_pci_gart_disable(rdev); 241 r100_pci_gart_disable(rdev);
143 radeon_gart_table_ram_free(rdev); 242 radeon_gart_table_ram_free(rdev);
144 radeon_gart_fini(rdev);
145} 243}
146 244
147int r100_irq_set(struct radeon_device *rdev) 245int r100_irq_set(struct radeon_device *rdev)
148{ 246{
149 uint32_t tmp = 0; 247 uint32_t tmp = 0;
150 248
249 if (!rdev->irq.installed) {
250 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
251 WREG32(R_000040_GEN_INT_CNTL, 0);
252 return -EINVAL;
253 }
151 if (rdev->irq.sw_int) { 254 if (rdev->irq.sw_int) {
152 tmp |= RADEON_SW_INT_ENABLE; 255 tmp |= RADEON_SW_INT_ENABLE;
153 } 256 }
@@ -157,6 +260,12 @@ int r100_irq_set(struct radeon_device *rdev)
157 if (rdev->irq.crtc_vblank_int[1]) { 260 if (rdev->irq.crtc_vblank_int[1]) {
158 tmp |= RADEON_CRTC2_VBLANK_MASK; 261 tmp |= RADEON_CRTC2_VBLANK_MASK;
159 } 262 }
263 if (rdev->irq.hpd[0]) {
264 tmp |= RADEON_FP_DETECT_MASK;
265 }
266 if (rdev->irq.hpd[1]) {
267 tmp |= RADEON_FP2_DETECT_MASK;
268 }
160 WREG32(RADEON_GEN_INT_CNTL, tmp); 269 WREG32(RADEON_GEN_INT_CNTL, tmp);
161 return 0; 270 return 0;
162} 271}
@@ -175,8 +284,9 @@ void r100_irq_disable(struct radeon_device *rdev)
175static inline uint32_t r100_irq_ack(struct radeon_device *rdev) 284static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
176{ 285{
177 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 286 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
178 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT | 287 uint32_t irq_mask = RADEON_SW_INT_TEST |
179 RADEON_CRTC2_VBLANK_STAT; 288 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
289 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
180 290
181 if (irqs) { 291 if (irqs) {
182 WREG32(RADEON_GEN_INT_STATUS, irqs); 292 WREG32(RADEON_GEN_INT_STATUS, irqs);
@@ -187,6 +297,7 @@ static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
187int r100_irq_process(struct radeon_device *rdev) 297int r100_irq_process(struct radeon_device *rdev)
188{ 298{
189 uint32_t status, msi_rearm; 299 uint32_t status, msi_rearm;
300 bool queue_hotplug = false;
190 301
191 status = r100_irq_ack(rdev); 302 status = r100_irq_ack(rdev);
192 if (!status) { 303 if (!status) {
@@ -203,12 +314,26 @@ int r100_irq_process(struct radeon_device *rdev)
203 /* Vertical blank interrupts */ 314 /* Vertical blank interrupts */
204 if (status & RADEON_CRTC_VBLANK_STAT) { 315 if (status & RADEON_CRTC_VBLANK_STAT) {
205 drm_handle_vblank(rdev->ddev, 0); 316 drm_handle_vblank(rdev->ddev, 0);
317 rdev->pm.vblank_sync = true;
318 wake_up(&rdev->irq.vblank_queue);
206 } 319 }
207 if (status & RADEON_CRTC2_VBLANK_STAT) { 320 if (status & RADEON_CRTC2_VBLANK_STAT) {
208 drm_handle_vblank(rdev->ddev, 1); 321 drm_handle_vblank(rdev->ddev, 1);
322 rdev->pm.vblank_sync = true;
323 wake_up(&rdev->irq.vblank_queue);
324 }
325 if (status & RADEON_FP_DETECT_STAT) {
326 queue_hotplug = true;
327 DRM_DEBUG("HPD1\n");
328 }
329 if (status & RADEON_FP2_DETECT_STAT) {
330 queue_hotplug = true;
331 DRM_DEBUG("HPD2\n");
209 } 332 }
210 status = r100_irq_ack(rdev); 333 status = r100_irq_ack(rdev);
211 } 334 }
335 if (queue_hotplug)
336 queue_work(rdev->wq, &rdev->hotplug_work);
212 if (rdev->msi_enabled) { 337 if (rdev->msi_enabled) {
213 switch (rdev->family) { 338 switch (rdev->family) {
214 case CHIP_RS400: 339 case CHIP_RS400:
@@ -235,14 +360,25 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
235 return RREG32(RADEON_CRTC2_CRNT_FRAME); 360 return RREG32(RADEON_CRTC2_CRNT_FRAME);
236} 361}
237 362
363/* Who ever call radeon_fence_emit should call ring_lock and ask
364 * for enough space (today caller are ib schedule and buffer move) */
238void r100_fence_ring_emit(struct radeon_device *rdev, 365void r100_fence_ring_emit(struct radeon_device *rdev,
239 struct radeon_fence *fence) 366 struct radeon_fence *fence)
240{ 367{
241 /* Who ever call radeon_fence_emit should call ring_lock and ask 368 /* We have to make sure that caches are flushed before
242 * for enough space (today caller are ib schedule and buffer move) */ 369 * CPU might read something from VRAM. */
370 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
371 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
372 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
373 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
243 /* Wait until IDLE & CLEAN */ 374 /* Wait until IDLE & CLEAN */
244 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 375 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
245 radeon_ring_write(rdev, (1 << 16) | (1 << 17)); 376 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
377 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
378 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
379 RADEON_HDP_READ_BUFFER_INVALIDATE);
380 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
381 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
246 /* Emit fence sequence & fire IRQ */ 382 /* Emit fence sequence & fire IRQ */
247 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 383 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
248 radeon_ring_write(rdev, fence->seq); 384 radeon_ring_write(rdev, fence->seq);
@@ -255,24 +391,27 @@ int r100_wb_init(struct radeon_device *rdev)
255 int r; 391 int r;
256 392
257 if (rdev->wb.wb_obj == NULL) { 393 if (rdev->wb.wb_obj == NULL) {
258 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, 394 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
259 true, 395 RADEON_GEM_DOMAIN_GTT,
260 RADEON_GEM_DOMAIN_GTT, 396 &rdev->wb.wb_obj);
261 false, &rdev->wb.wb_obj);
262 if (r) { 397 if (r) {
263 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r); 398 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
264 return r; 399 return r;
265 } 400 }
266 r = radeon_object_pin(rdev->wb.wb_obj, 401 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
267 RADEON_GEM_DOMAIN_GTT, 402 if (unlikely(r != 0))
268 &rdev->wb.gpu_addr); 403 return r;
404 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
405 &rdev->wb.gpu_addr);
269 if (r) { 406 if (r) {
270 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r); 407 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
408 radeon_bo_unreserve(rdev->wb.wb_obj);
271 return r; 409 return r;
272 } 410 }
273 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 411 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
412 radeon_bo_unreserve(rdev->wb.wb_obj);
274 if (r) { 413 if (r) {
275 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r); 414 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
276 return r; 415 return r;
277 } 416 }
278 } 417 }
@@ -290,11 +429,19 @@ void r100_wb_disable(struct radeon_device *rdev)
290 429
291void r100_wb_fini(struct radeon_device *rdev) 430void r100_wb_fini(struct radeon_device *rdev)
292{ 431{
432 int r;
433
293 r100_wb_disable(rdev); 434 r100_wb_disable(rdev);
294 if (rdev->wb.wb_obj) { 435 if (rdev->wb.wb_obj) {
295 radeon_object_kunmap(rdev->wb.wb_obj); 436 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
296 radeon_object_unpin(rdev->wb.wb_obj); 437 if (unlikely(r != 0)) {
297 radeon_object_unref(&rdev->wb.wb_obj); 438 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
439 return;
440 }
441 radeon_bo_kunmap(rdev->wb.wb_obj);
442 radeon_bo_unpin(rdev->wb.wb_obj);
443 radeon_bo_unreserve(rdev->wb.wb_obj);
444 radeon_bo_unref(&rdev->wb.wb_obj);
298 rdev->wb.wb = NULL; 445 rdev->wb.wb = NULL;
299 rdev->wb.wb_obj = NULL; 446 rdev->wb.wb_obj = NULL;
300 } 447 }
@@ -598,6 +745,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
598 udelay(10); 745 udelay(10);
599 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 746 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
600 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); 747 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
748 /* protect against crazy HW on resume */
749 rdev->cp.wptr &= rdev->cp.ptr_mask;
601 /* Set cp mode to bus mastering & enable cp*/ 750 /* Set cp mode to bus mastering & enable cp*/
602 WREG32(RADEON_CP_CSQ_MODE, 751 WREG32(RADEON_CP_CSQ_MODE,
603 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 752 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -1250,7 +1399,6 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1250 case RADEON_TXFORMAT_ARGB4444: 1399 case RADEON_TXFORMAT_ARGB4444:
1251 case RADEON_TXFORMAT_VYUY422: 1400 case RADEON_TXFORMAT_VYUY422:
1252 case RADEON_TXFORMAT_YVYU422: 1401 case RADEON_TXFORMAT_YVYU422:
1253 case RADEON_TXFORMAT_DXT1:
1254 case RADEON_TXFORMAT_SHADOW16: 1402 case RADEON_TXFORMAT_SHADOW16:
1255 case RADEON_TXFORMAT_LDUDV655: 1403 case RADEON_TXFORMAT_LDUDV655:
1256 case RADEON_TXFORMAT_DUDV88: 1404 case RADEON_TXFORMAT_DUDV88:
@@ -1258,12 +1406,19 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1258 break; 1406 break;
1259 case RADEON_TXFORMAT_ARGB8888: 1407 case RADEON_TXFORMAT_ARGB8888:
1260 case RADEON_TXFORMAT_RGBA8888: 1408 case RADEON_TXFORMAT_RGBA8888:
1261 case RADEON_TXFORMAT_DXT23:
1262 case RADEON_TXFORMAT_DXT45:
1263 case RADEON_TXFORMAT_SHADOW32: 1409 case RADEON_TXFORMAT_SHADOW32:
1264 case RADEON_TXFORMAT_LDUDUV8888: 1410 case RADEON_TXFORMAT_LDUDUV8888:
1265 track->textures[i].cpp = 4; 1411 track->textures[i].cpp = 4;
1266 break; 1412 break;
1413 case RADEON_TXFORMAT_DXT1:
1414 track->textures[i].cpp = 1;
1415 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1416 break;
1417 case RADEON_TXFORMAT_DXT23:
1418 case RADEON_TXFORMAT_DXT45:
1419 track->textures[i].cpp = 1;
1420 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1421 break;
1267 } 1422 }
1268 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1423 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1269 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1424 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
@@ -1288,17 +1443,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1288 1443
1289int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1444int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1290 struct radeon_cs_packet *pkt, 1445 struct radeon_cs_packet *pkt,
1291 struct radeon_object *robj) 1446 struct radeon_bo *robj)
1292{ 1447{
1293 unsigned idx; 1448 unsigned idx;
1294 u32 value; 1449 u32 value;
1295 idx = pkt->idx + 1; 1450 idx = pkt->idx + 1;
1296 value = radeon_get_ib_value(p, idx + 2); 1451 value = radeon_get_ib_value(p, idx + 2);
1297 if ((value + 1) > radeon_object_size(robj)) { 1452 if ((value + 1) > radeon_bo_size(robj)) {
1298 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1453 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1299 "(need %u have %lu) !\n", 1454 "(need %u have %lu) !\n",
1300 value + 1, 1455 value + 1,
1301 radeon_object_size(robj)); 1456 radeon_bo_size(robj));
1302 return -EINVAL; 1457 return -EINVAL;
1303 } 1458 }
1304 return 0; 1459 return 0;
@@ -1363,6 +1518,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1363 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1518 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1364 return -EINVAL; 1519 return -EINVAL;
1365 } 1520 }
1521 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1366 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1522 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1367 track->immd_dwords = pkt->count - 1; 1523 track->immd_dwords = pkt->count - 1;
1368 r = r100_cs_track_check(p->rdev, track); 1524 r = r100_cs_track_check(p->rdev, track);
@@ -1553,7 +1709,7 @@ int r100_gui_wait_for_idle(struct radeon_device *rdev)
1553 } 1709 }
1554 for (i = 0; i < rdev->usec_timeout; i++) { 1710 for (i = 0; i < rdev->usec_timeout; i++) {
1555 tmp = RREG32(RADEON_RBBM_STATUS); 1711 tmp = RREG32(RADEON_RBBM_STATUS);
1556 if (!(tmp & (1 << 31))) { 1712 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1557 return 0; 1713 return 0;
1558 } 1714 }
1559 DRM_UDELAY(1); 1715 DRM_UDELAY(1);
@@ -1568,8 +1724,8 @@ int r100_mc_wait_for_idle(struct radeon_device *rdev)
1568 1724
1569 for (i = 0; i < rdev->usec_timeout; i++) { 1725 for (i = 0; i < rdev->usec_timeout; i++) {
1570 /* read MC_STATUS */ 1726 /* read MC_STATUS */
1571 tmp = RREG32(0x0150); 1727 tmp = RREG32(RADEON_MC_STATUS);
1572 if (tmp & (1 << 2)) { 1728 if (tmp & RADEON_MC_IDLE) {
1573 return 0; 1729 return 0;
1574 } 1730 }
1575 DRM_UDELAY(1); 1731 DRM_UDELAY(1);
@@ -1642,7 +1798,7 @@ int r100_gpu_reset(struct radeon_device *rdev)
1642 } 1798 }
1643 /* Check if GPU is idle */ 1799 /* Check if GPU is idle */
1644 status = RREG32(RADEON_RBBM_STATUS); 1800 status = RREG32(RADEON_RBBM_STATUS);
1645 if (status & (1 << 31)) { 1801 if (status & RADEON_RBBM_ACTIVE) {
1646 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); 1802 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1647 return -1; 1803 return -1;
1648 } 1804 }
@@ -1650,6 +1806,89 @@ int r100_gpu_reset(struct radeon_device *rdev)
1650 return 0; 1806 return 0;
1651} 1807}
1652 1808
1809void r100_set_common_regs(struct radeon_device *rdev)
1810{
1811 struct drm_device *dev = rdev->ddev;
1812 bool force_dac2 = false;
1813 u32 tmp;
1814
1815 /* set these so they don't interfere with anything */
1816 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1817 WREG32(RADEON_SUBPIC_CNTL, 0);
1818 WREG32(RADEON_VIPH_CONTROL, 0);
1819 WREG32(RADEON_I2C_CNTL_1, 0);
1820 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1821 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1822 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1823
1824 /* always set up dac2 on rn50 and some rv100 as lots
1825 * of servers seem to wire it up to a VGA port but
1826 * don't report it in the bios connector
1827 * table.
1828 */
1829 switch (dev->pdev->device) {
1830 /* RN50 */
1831 case 0x515e:
1832 case 0x5969:
1833 force_dac2 = true;
1834 break;
1835 /* RV100*/
1836 case 0x5159:
1837 case 0x515a:
1838 /* DELL triple head servers */
1839 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1840 ((dev->pdev->subsystem_device == 0x016c) ||
1841 (dev->pdev->subsystem_device == 0x016d) ||
1842 (dev->pdev->subsystem_device == 0x016e) ||
1843 (dev->pdev->subsystem_device == 0x016f) ||
1844 (dev->pdev->subsystem_device == 0x0170) ||
1845 (dev->pdev->subsystem_device == 0x017d) ||
1846 (dev->pdev->subsystem_device == 0x017e) ||
1847 (dev->pdev->subsystem_device == 0x0183) ||
1848 (dev->pdev->subsystem_device == 0x018a) ||
1849 (dev->pdev->subsystem_device == 0x019a)))
1850 force_dac2 = true;
1851 break;
1852 }
1853
1854 if (force_dac2) {
1855 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1856 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1857 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1858
1859 /* For CRT on DAC2, don't turn it on if BIOS didn't
1860 enable it, even it's detected.
1861 */
1862
1863 /* force it to crtc0 */
1864 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1865 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1866 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1867
1868 /* set up the TV DAC */
1869 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1870 RADEON_TV_DAC_STD_MASK |
1871 RADEON_TV_DAC_RDACPD |
1872 RADEON_TV_DAC_GDACPD |
1873 RADEON_TV_DAC_BDACPD |
1874 RADEON_TV_DAC_BGADJ_MASK |
1875 RADEON_TV_DAC_DACADJ_MASK);
1876 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1877 RADEON_TV_DAC_NHOLD |
1878 RADEON_TV_DAC_STD_PS2 |
1879 (0x58 << 16));
1880
1881 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1882 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1883 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1884 }
1885
1886 /* switch PM block to ACPI mode */
1887 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1888 tmp &= ~RADEON_PM_MODE_SEL;
1889 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1890
1891}
1653 1892
1654/* 1893/*
1655 * VRAM info 1894 * VRAM info
@@ -1730,17 +1969,20 @@ static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1730void r100_vram_init_sizes(struct radeon_device *rdev) 1969void r100_vram_init_sizes(struct radeon_device *rdev)
1731{ 1970{
1732 u64 config_aper_size; 1971 u64 config_aper_size;
1733 u32 accessible;
1734 1972
1973 /* work out accessible VRAM */
1974 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1975 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1976 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1977 /* FIXME we don't use the second aperture yet when we could use it */
1978 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1979 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1735 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 1980 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1736
1737 if (rdev->flags & RADEON_IS_IGP) { 1981 if (rdev->flags & RADEON_IS_IGP) {
1738 uint32_t tom; 1982 uint32_t tom;
1739 /* read NB_TOM to get the amount of ram stolen for the GPU */ 1983 /* read NB_TOM to get the amount of ram stolen for the GPU */
1740 tom = RREG32(RADEON_NB_TOM); 1984 tom = RREG32(RADEON_NB_TOM);
1741 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 1985 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1742 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1743 rdev->mc.vram_location = (tom & 0xffff) << 16;
1744 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 1986 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1745 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 1987 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1746 } else { 1988 } else {
@@ -1752,30 +1994,19 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
1752 rdev->mc.real_vram_size = 8192 * 1024; 1994 rdev->mc.real_vram_size = 8192 * 1024;
1753 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 1995 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1754 } 1996 }
1755 /* let driver place VRAM */ 1997 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1756 rdev->mc.vram_location = 0xFFFFFFFFUL; 1998 * Novell bug 204882 + along with lots of ubuntu ones
1757 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1999 */
1758 * Novell bug 204882 + along with lots of ubuntu ones */
1759 if (config_aper_size > rdev->mc.real_vram_size) 2000 if (config_aper_size > rdev->mc.real_vram_size)
1760 rdev->mc.mc_vram_size = config_aper_size; 2001 rdev->mc.mc_vram_size = config_aper_size;
1761 else 2002 else
1762 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2003 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1763 } 2004 }
1764 2005 /* FIXME remove this once we support unmappable VRAM */
1765 /* work out accessible VRAM */ 2006 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1766 accessible = r100_get_accessible_vram(rdev);
1767
1768 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1769 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1770
1771 if (accessible > rdev->mc.aper_size)
1772 accessible = rdev->mc.aper_size;
1773
1774 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1775 rdev->mc.mc_vram_size = rdev->mc.aper_size; 2007 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1776
1777 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1778 rdev->mc.real_vram_size = rdev->mc.aper_size; 2008 rdev->mc.real_vram_size = rdev->mc.aper_size;
2009 }
1779} 2010}
1780 2011
1781void r100_vga_set_state(struct radeon_device *rdev, bool state) 2012void r100_vga_set_state(struct radeon_device *rdev, bool state)
@@ -1792,11 +2023,19 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state)
1792 WREG32(RADEON_CONFIG_CNTL, temp); 2023 WREG32(RADEON_CONFIG_CNTL, temp);
1793} 2024}
1794 2025
1795void r100_vram_info(struct radeon_device *rdev) 2026void r100_mc_init(struct radeon_device *rdev)
1796{ 2027{
1797 r100_vram_get_type(rdev); 2028 u64 base;
1798 2029
2030 r100_vram_get_type(rdev);
1799 r100_vram_init_sizes(rdev); 2031 r100_vram_init_sizes(rdev);
2032 base = rdev->mc.aper_base;
2033 if (rdev->flags & RADEON_IS_IGP)
2034 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2035 radeon_vram_location(rdev, &rdev->mc, base);
2036 if (!(rdev->flags & RADEON_IS_AGP))
2037 radeon_gtt_location(rdev, &rdev->mc);
2038 radeon_update_bandwidth_info(rdev);
1800} 2039}
1801 2040
1802 2041
@@ -2160,6 +2399,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2160 uint32_t pixel_bytes1 = 0; 2399 uint32_t pixel_bytes1 = 0;
2161 uint32_t pixel_bytes2 = 0; 2400 uint32_t pixel_bytes2 = 0;
2162 2401
2402 radeon_update_display_priority(rdev);
2403
2163 if (rdev->mode_info.crtcs[0]->base.enabled) { 2404 if (rdev->mode_info.crtcs[0]->base.enabled) {
2164 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2405 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2165 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2406 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
@@ -2188,11 +2429,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2188 /* 2429 /*
2189 * determine is there is enough bw for current mode 2430 * determine is there is enough bw for current mode
2190 */ 2431 */
2191 mclk_ff.full = rfixed_const(rdev->clock.default_mclk); 2432 sclk_ff = rdev->pm.sclk;
2192 temp_ff.full = rfixed_const(100); 2433 mclk_ff = rdev->pm.mclk;
2193 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2194 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2195 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2196 2434
2197 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2435 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2198 temp_ff.full = rfixed_const(temp); 2436 temp_ff.full = rfixed_const(temp);
@@ -2588,13 +2826,14 @@ static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2588 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2826 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2589 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2827 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2590 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2828 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2829 DRM_ERROR("compress format %d\n", t->compress_format);
2591} 2830}
2592 2831
2593static int r100_cs_track_cube(struct radeon_device *rdev, 2832static int r100_cs_track_cube(struct radeon_device *rdev,
2594 struct r100_cs_track *track, unsigned idx) 2833 struct r100_cs_track *track, unsigned idx)
2595{ 2834{
2596 unsigned face, w, h; 2835 unsigned face, w, h;
2597 struct radeon_object *cube_robj; 2836 struct radeon_bo *cube_robj;
2598 unsigned long size; 2837 unsigned long size;
2599 2838
2600 for (face = 0; face < 5; face++) { 2839 for (face = 0; face < 5; face++) {
@@ -2607,9 +2846,9 @@ static int r100_cs_track_cube(struct radeon_device *rdev,
2607 2846
2608 size += track->textures[idx].cube_info[face].offset; 2847 size += track->textures[idx].cube_info[face].offset;
2609 2848
2610 if (size > radeon_object_size(cube_robj)) { 2849 if (size > radeon_bo_size(cube_robj)) {
2611 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2850 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2612 size, radeon_object_size(cube_robj)); 2851 size, radeon_bo_size(cube_robj));
2613 r100_cs_track_texture_print(&track->textures[idx]); 2852 r100_cs_track_texture_print(&track->textures[idx]);
2614 return -1; 2853 return -1;
2615 } 2854 }
@@ -2617,12 +2856,42 @@ static int r100_cs_track_cube(struct radeon_device *rdev,
2617 return 0; 2856 return 0;
2618} 2857}
2619 2858
2859static int r100_track_compress_size(int compress_format, int w, int h)
2860{
2861 int block_width, block_height, block_bytes;
2862 int wblocks, hblocks;
2863 int min_wblocks;
2864 int sz;
2865
2866 block_width = 4;
2867 block_height = 4;
2868
2869 switch (compress_format) {
2870 case R100_TRACK_COMP_DXT1:
2871 block_bytes = 8;
2872 min_wblocks = 4;
2873 break;
2874 default:
2875 case R100_TRACK_COMP_DXT35:
2876 block_bytes = 16;
2877 min_wblocks = 2;
2878 break;
2879 }
2880
2881 hblocks = (h + block_height - 1) / block_height;
2882 wblocks = (w + block_width - 1) / block_width;
2883 if (wblocks < min_wblocks)
2884 wblocks = min_wblocks;
2885 sz = wblocks * hblocks * block_bytes;
2886 return sz;
2887}
2888
2620static int r100_cs_track_texture_check(struct radeon_device *rdev, 2889static int r100_cs_track_texture_check(struct radeon_device *rdev,
2621 struct r100_cs_track *track) 2890 struct r100_cs_track *track)
2622{ 2891{
2623 struct radeon_object *robj; 2892 struct radeon_bo *robj;
2624 unsigned long size; 2893 unsigned long size;
2625 unsigned u, i, w, h; 2894 unsigned u, i, w, h, d;
2626 int ret; 2895 int ret;
2627 2896
2628 for (u = 0; u < track->num_texture; u++) { 2897 for (u = 0; u < track->num_texture; u++) {
@@ -2654,14 +2923,25 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
2654 h = h / (1 << i); 2923 h = h / (1 << i);
2655 if (track->textures[u].roundup_h) 2924 if (track->textures[u].roundup_h)
2656 h = roundup_pow_of_two(h); 2925 h = roundup_pow_of_two(h);
2657 size += w * h; 2926 if (track->textures[u].tex_coord_type == 1) {
2927 d = (1 << track->textures[u].txdepth) / (1 << i);
2928 if (!d)
2929 d = 1;
2930 } else {
2931 d = 1;
2932 }
2933 if (track->textures[u].compress_format) {
2934
2935 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2936 /* compressed textures are block based */
2937 } else
2938 size += w * h * d;
2658 } 2939 }
2659 size *= track->textures[u].cpp; 2940 size *= track->textures[u].cpp;
2941
2660 switch (track->textures[u].tex_coord_type) { 2942 switch (track->textures[u].tex_coord_type) {
2661 case 0: 2943 case 0:
2662 break;
2663 case 1: 2944 case 1:
2664 size *= (1 << track->textures[u].txdepth);
2665 break; 2945 break;
2666 case 2: 2946 case 2:
2667 if (track->separate_cube) { 2947 if (track->separate_cube) {
@@ -2676,9 +2956,9 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
2676 "%u\n", track->textures[u].tex_coord_type, u); 2956 "%u\n", track->textures[u].tex_coord_type, u);
2677 return -EINVAL; 2957 return -EINVAL;
2678 } 2958 }
2679 if (size > radeon_object_size(robj)) { 2959 if (size > radeon_bo_size(robj)) {
2680 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2960 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2681 "%lu\n", u, size, radeon_object_size(robj)); 2961 "%lu\n", u, size, radeon_bo_size(robj));
2682 r100_cs_track_texture_print(&track->textures[u]); 2962 r100_cs_track_texture_print(&track->textures[u]);
2683 return -EINVAL; 2963 return -EINVAL;
2684 } 2964 }
@@ -2695,15 +2975,19 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2695 2975
2696 for (i = 0; i < track->num_cb; i++) { 2976 for (i = 0; i < track->num_cb; i++) {
2697 if (track->cb[i].robj == NULL) { 2977 if (track->cb[i].robj == NULL) {
2978 if (!(track->zb_cb_clear || track->color_channel_mask ||
2979 track->blend_read_enable)) {
2980 continue;
2981 }
2698 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2982 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2699 return -EINVAL; 2983 return -EINVAL;
2700 } 2984 }
2701 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2985 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2702 size += track->cb[i].offset; 2986 size += track->cb[i].offset;
2703 if (size > radeon_object_size(track->cb[i].robj)) { 2987 if (size > radeon_bo_size(track->cb[i].robj)) {
2704 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2988 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2705 "(need %lu have %lu) !\n", i, size, 2989 "(need %lu have %lu) !\n", i, size,
2706 radeon_object_size(track->cb[i].robj)); 2990 radeon_bo_size(track->cb[i].robj));
2707 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2991 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2708 i, track->cb[i].pitch, track->cb[i].cpp, 2992 i, track->cb[i].pitch, track->cb[i].cpp,
2709 track->cb[i].offset, track->maxy); 2993 track->cb[i].offset, track->maxy);
@@ -2717,10 +3001,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2717 } 3001 }
2718 size = track->zb.pitch * track->zb.cpp * track->maxy; 3002 size = track->zb.pitch * track->zb.cpp * track->maxy;
2719 size += track->zb.offset; 3003 size += track->zb.offset;
2720 if (size > radeon_object_size(track->zb.robj)) { 3004 if (size > radeon_bo_size(track->zb.robj)) {
2721 DRM_ERROR("[drm] Buffer too small for z buffer " 3005 DRM_ERROR("[drm] Buffer too small for z buffer "
2722 "(need %lu have %lu) !\n", size, 3006 "(need %lu have %lu) !\n", size,
2723 radeon_object_size(track->zb.robj)); 3007 radeon_bo_size(track->zb.robj));
2724 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 3008 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2725 track->zb.pitch, track->zb.cpp, 3009 track->zb.pitch, track->zb.cpp,
2726 track->zb.offset, track->maxy); 3010 track->zb.offset, track->maxy);
@@ -2728,7 +3012,11 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2728 } 3012 }
2729 } 3013 }
2730 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3014 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2731 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3015 if (track->vap_vf_cntl & (1 << 14)) {
3016 nverts = track->vap_alt_nverts;
3017 } else {
3018 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3019 }
2732 switch (prim_walk) { 3020 switch (prim_walk) {
2733 case 1: 3021 case 1:
2734 for (i = 0; i < track->num_arrays; i++) { 3022 for (i = 0; i < track->num_arrays; i++) {
@@ -2738,11 +3026,12 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2738 "bound\n", prim_walk, i); 3026 "bound\n", prim_walk, i);
2739 return -EINVAL; 3027 return -EINVAL;
2740 } 3028 }
2741 if (size > radeon_object_size(track->arrays[i].robj)) { 3029 if (size > radeon_bo_size(track->arrays[i].robj)) {
2742 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " 3030 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2743 "have %lu dwords\n", prim_walk, i, 3031 "need %lu dwords have %lu dwords\n",
2744 size >> 2, 3032 prim_walk, i, size >> 2,
2745 radeon_object_size(track->arrays[i].robj) >> 2); 3033 radeon_bo_size(track->arrays[i].robj)
3034 >> 2);
2746 DRM_ERROR("Max indices %u\n", track->max_indx); 3035 DRM_ERROR("Max indices %u\n", track->max_indx);
2747 return -EINVAL; 3036 return -EINVAL;
2748 } 3037 }
@@ -2756,10 +3045,12 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2756 "bound\n", prim_walk, i); 3045 "bound\n", prim_walk, i);
2757 return -EINVAL; 3046 return -EINVAL;
2758 } 3047 }
2759 if (size > radeon_object_size(track->arrays[i].robj)) { 3048 if (size > radeon_bo_size(track->arrays[i].robj)) {
2760 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords " 3049 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2761 "have %lu dwords\n", prim_walk, i, size >> 2, 3050 "need %lu dwords have %lu dwords\n",
2762 radeon_object_size(track->arrays[i].robj) >> 2); 3051 prim_walk, i, size >> 2,
3052 radeon_bo_size(track->arrays[i].robj)
3053 >> 2);
2763 return -EINVAL; 3054 return -EINVAL;
2764 } 3055 }
2765 } 3056 }
@@ -2821,6 +3112,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
2821 track->arrays[i].esize = 0x7F; 3112 track->arrays[i].esize = 0x7F;
2822 } 3113 }
2823 for (i = 0; i < track->num_texture; i++) { 3114 for (i = 0; i < track->num_texture; i++) {
3115 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2824 track->textures[i].pitch = 16536; 3116 track->textures[i].pitch = 16536;
2825 track->textures[i].width = 16536; 3117 track->textures[i].width = 16536;
2826 track->textures[i].height = 16536; 3118 track->textures[i].height = 16536;
@@ -3022,10 +3314,9 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3022void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3314void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3023{ 3315{
3024 /* Update base address for crtc */ 3316 /* Update base address for crtc */
3025 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); 3317 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3026 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3318 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3027 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, 3319 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3028 rdev->mc.vram_location);
3029 } 3320 }
3030 /* Restore CRTC registers */ 3321 /* Restore CRTC registers */
3031 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3322 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
@@ -3101,6 +3392,9 @@ static int r100_startup(struct radeon_device *rdev)
3101{ 3392{
3102 int r; 3393 int r;
3103 3394
3395 /* set common regs */
3396 r100_set_common_regs(rdev);
3397 /* program mc */
3104 r100_mc_program(rdev); 3398 r100_mc_program(rdev);
3105 /* Resume clock */ 3399 /* Resume clock */
3106 r100_clock_startup(rdev); 3400 r100_clock_startup(rdev);
@@ -3108,14 +3402,15 @@ static int r100_startup(struct radeon_device *rdev)
3108 r100_gpu_init(rdev); 3402 r100_gpu_init(rdev);
3109 /* Initialize GART (initialize after TTM so we can allocate 3403 /* Initialize GART (initialize after TTM so we can allocate
3110 * memory through TTM but finalize after TTM) */ 3404 * memory through TTM but finalize after TTM) */
3405 r100_enable_bm(rdev);
3111 if (rdev->flags & RADEON_IS_PCI) { 3406 if (rdev->flags & RADEON_IS_PCI) {
3112 r = r100_pci_gart_enable(rdev); 3407 r = r100_pci_gart_enable(rdev);
3113 if (r) 3408 if (r)
3114 return r; 3409 return r;
3115 } 3410 }
3116 /* Enable IRQ */ 3411 /* Enable IRQ */
3117 rdev->irq.sw_int = true;
3118 r100_irq_set(rdev); 3412 r100_irq_set(rdev);
3413 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3119 /* 1M ring buffer */ 3414 /* 1M ring buffer */
3120 r = r100_cp_init(rdev, 1024 * 1024); 3415 r = r100_cp_init(rdev, 1024 * 1024);
3121 if (r) { 3416 if (r) {
@@ -3150,6 +3445,8 @@ int r100_resume(struct radeon_device *rdev)
3150 radeon_combios_asic_init(rdev->ddev); 3445 radeon_combios_asic_init(rdev->ddev);
3151 /* Resume clock after posting */ 3446 /* Resume clock after posting */
3152 r100_clock_startup(rdev); 3447 r100_clock_startup(rdev);
3448 /* Initialize surface registers */
3449 radeon_surface_init(rdev);
3153 return r100_startup(rdev); 3450 return r100_startup(rdev);
3154} 3451}
3155 3452
@@ -3165,49 +3462,22 @@ int r100_suspend(struct radeon_device *rdev)
3165 3462
3166void r100_fini(struct radeon_device *rdev) 3463void r100_fini(struct radeon_device *rdev)
3167{ 3464{
3168 r100_suspend(rdev); 3465 radeon_pm_fini(rdev);
3169 r100_cp_fini(rdev); 3466 r100_cp_fini(rdev);
3170 r100_wb_fini(rdev); 3467 r100_wb_fini(rdev);
3171 r100_ib_fini(rdev); 3468 r100_ib_fini(rdev);
3172 radeon_gem_fini(rdev); 3469 radeon_gem_fini(rdev);
3173 if (rdev->flags & RADEON_IS_PCI) 3470 if (rdev->flags & RADEON_IS_PCI)
3174 r100_pci_gart_fini(rdev); 3471 r100_pci_gart_fini(rdev);
3472 radeon_agp_fini(rdev);
3175 radeon_irq_kms_fini(rdev); 3473 radeon_irq_kms_fini(rdev);
3176 radeon_fence_driver_fini(rdev); 3474 radeon_fence_driver_fini(rdev);
3177 radeon_object_fini(rdev); 3475 radeon_bo_fini(rdev);
3178 radeon_atombios_fini(rdev); 3476 radeon_atombios_fini(rdev);
3179 kfree(rdev->bios); 3477 kfree(rdev->bios);
3180 rdev->bios = NULL; 3478 rdev->bios = NULL;
3181} 3479}
3182 3480
3183int r100_mc_init(struct radeon_device *rdev)
3184{
3185 int r;
3186 u32 tmp;
3187
3188 /* Setup GPU memory space */
3189 rdev->mc.vram_location = 0xFFFFFFFFUL;
3190 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3191 if (rdev->flags & RADEON_IS_IGP) {
3192 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3193 rdev->mc.vram_location = tmp << 16;
3194 }
3195 if (rdev->flags & RADEON_IS_AGP) {
3196 r = radeon_agp_init(rdev);
3197 if (r) {
3198 printk(KERN_WARNING "[drm] Disabling AGP\n");
3199 rdev->flags &= ~RADEON_IS_AGP;
3200 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3201 } else {
3202 rdev->mc.gtt_location = rdev->mc.agp_base;
3203 }
3204 }
3205 r = radeon_mc_setup(rdev);
3206 if (r)
3207 return r;
3208 return 0;
3209}
3210
3211int r100_init(struct radeon_device *rdev) 3481int r100_init(struct radeon_device *rdev)
3212{ 3482{
3213 int r; 3483 int r;
@@ -3242,20 +3512,23 @@ int r100_init(struct radeon_device *rdev)
3242 RREG32(R_0007C0_CP_STAT)); 3512 RREG32(R_0007C0_CP_STAT));
3243 } 3513 }
3244 /* check if cards are posted or not */ 3514 /* check if cards are posted or not */
3245 if (!radeon_card_posted(rdev) && rdev->bios) { 3515 if (radeon_boot_test_post_card(rdev) == false)
3246 DRM_INFO("GPU not posted. posting now...\n"); 3516 return -EINVAL;
3247 radeon_combios_asic_init(rdev->ddev);
3248 }
3249 /* Set asic errata */ 3517 /* Set asic errata */
3250 r100_errata(rdev); 3518 r100_errata(rdev);
3251 /* Initialize clocks */ 3519 /* Initialize clocks */
3252 radeon_get_clock_info(rdev->ddev); 3520 radeon_get_clock_info(rdev->ddev);
3253 /* Get vram informations */ 3521 /* Initialize power management */
3254 r100_vram_info(rdev); 3522 radeon_pm_init(rdev);
3255 /* Initialize memory controller (also test AGP) */ 3523 /* initialize AGP */
3256 r = r100_mc_init(rdev); 3524 if (rdev->flags & RADEON_IS_AGP) {
3257 if (r) 3525 r = radeon_agp_init(rdev);
3258 return r; 3526 if (r) {
3527 radeon_agp_disable(rdev);
3528 }
3529 }
3530 /* initialize VRAM */
3531 r100_mc_init(rdev);
3259 /* Fence driver */ 3532 /* Fence driver */
3260 r = radeon_fence_driver_init(rdev); 3533 r = radeon_fence_driver_init(rdev);
3261 if (r) 3534 if (r)
@@ -3264,7 +3537,7 @@ int r100_init(struct radeon_device *rdev)
3264 if (r) 3537 if (r)
3265 return r; 3538 return r;
3266 /* Memory manager */ 3539 /* Memory manager */
3267 r = radeon_object_init(rdev); 3540 r = radeon_bo_init(rdev);
3268 if (r) 3541 if (r)
3269 return r; 3542 return r;
3270 if (rdev->flags & RADEON_IS_PCI) { 3543 if (rdev->flags & RADEON_IS_PCI) {
@@ -3278,13 +3551,12 @@ int r100_init(struct radeon_device *rdev)
3278 if (r) { 3551 if (r) {
3279 /* Somethings want wront with the accel init stop accel */ 3552 /* Somethings want wront with the accel init stop accel */
3280 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 3553 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3281 r100_suspend(rdev);
3282 r100_cp_fini(rdev); 3554 r100_cp_fini(rdev);
3283 r100_wb_fini(rdev); 3555 r100_wb_fini(rdev);
3284 r100_ib_fini(rdev); 3556 r100_ib_fini(rdev);
3557 radeon_irq_kms_fini(rdev);
3285 if (rdev->flags & RADEON_IS_PCI) 3558 if (rdev->flags & RADEON_IS_PCI)
3286 r100_pci_gart_fini(rdev); 3559 r100_pci_gart_fini(rdev);
3287 radeon_irq_kms_fini(rdev);
3288 rdev->accel_working = false; 3560 rdev->accel_working = false;
3289 } 3561 }
3290 return 0; 3562 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-13 00:12:40 -0400