diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/ni_dpm.c')
-rw-r--r-- | drivers/gpu/drm/radeon/ni_dpm.c | 28 |
1 files changed, 11 insertions, 17 deletions
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index cdc003085a76..49c4d48f54d6 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c | |||
@@ -785,8 +785,8 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, | |||
785 | struct ni_ps *ps = ni_get_ps(rps); | 785 | struct ni_ps *ps = ni_get_ps(rps); |
786 | struct radeon_clock_and_voltage_limits *max_limits; | 786 | struct radeon_clock_and_voltage_limits *max_limits; |
787 | bool disable_mclk_switching; | 787 | bool disable_mclk_switching; |
788 | u32 mclk, sclk; | 788 | u32 mclk; |
789 | u16 vddc, vddci; | 789 | u16 vddci; |
790 | u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; | 790 | u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; |
791 | int i; | 791 | int i; |
792 | 792 | ||
@@ -839,24 +839,14 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, | |||
839 | 839 | ||
840 | /* XXX validate the min clocks required for display */ | 840 | /* XXX validate the min clocks required for display */ |
841 | 841 | ||
842 | /* adjust low state */ | ||
842 | if (disable_mclk_switching) { | 843 | if (disable_mclk_switching) { |
843 | mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; | 844 | ps->performance_levels[0].mclk = |
844 | sclk = ps->performance_levels[0].sclk; | 845 | ps->performance_levels[ps->performance_level_count - 1].mclk; |
845 | vddc = ps->performance_levels[0].vddc; | 846 | ps->performance_levels[0].vddci = |
846 | vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; | 847 | ps->performance_levels[ps->performance_level_count - 1].vddci; |
847 | } else { | ||
848 | sclk = ps->performance_levels[0].sclk; | ||
849 | mclk = ps->performance_levels[0].mclk; | ||
850 | vddc = ps->performance_levels[0].vddc; | ||
851 | vddci = ps->performance_levels[0].vddci; | ||
852 | } | 848 | } |
853 | 849 | ||
854 | /* adjusted low state */ | ||
855 | ps->performance_levels[0].sclk = sclk; | ||
856 | ps->performance_levels[0].mclk = mclk; | ||
857 | ps->performance_levels[0].vddc = vddc; | ||
858 | ps->performance_levels[0].vddci = vddci; | ||
859 | |||
860 | btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, | 850 | btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, |
861 | &ps->performance_levels[0].sclk, | 851 | &ps->performance_levels[0].sclk, |
862 | &ps->performance_levels[0].mclk); | 852 | &ps->performance_levels[0].mclk); |
@@ -868,11 +858,15 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, | |||
868 | ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; | 858 | ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; |
869 | } | 859 | } |
870 | 860 | ||
861 | /* adjust remaining states */ | ||
871 | if (disable_mclk_switching) { | 862 | if (disable_mclk_switching) { |
872 | mclk = ps->performance_levels[0].mclk; | 863 | mclk = ps->performance_levels[0].mclk; |
864 | vddci = ps->performance_levels[0].vddci; | ||
873 | for (i = 1; i < ps->performance_level_count; i++) { | 865 | for (i = 1; i < ps->performance_level_count; i++) { |
874 | if (mclk < ps->performance_levels[i].mclk) | 866 | if (mclk < ps->performance_levels[i].mclk) |
875 | mclk = ps->performance_levels[i].mclk; | 867 | mclk = ps->performance_levels[i].mclk; |
868 | if (vddci < ps->performance_levels[i].vddci) | ||
869 | vddci = ps->performance_levels[i].vddci; | ||
876 | } | 870 | } |
877 | for (i = 0; i < ps->performance_level_count; i++) { | 871 | for (i = 0; i < ps->performance_level_count; i++) { |
878 | ps->performance_levels[i].mclk = mclk; | 872 | ps->performance_levels[i].mclk = mclk; |