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path: root/drivers/gpu/drm/radeon/ni_dpm.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/ni_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c24
1 files changed, 3 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 559cf24d51af..f0f5f748938a 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -1054,10 +1054,6 @@ static int ni_restrict_performance_levels_before_switch(struct radeon_device *rd
1054int ni_dpm_force_performance_level(struct radeon_device *rdev, 1054int ni_dpm_force_performance_level(struct radeon_device *rdev,
1055 enum radeon_dpm_forced_level level) 1055 enum radeon_dpm_forced_level level)
1056{ 1056{
1057 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1058 struct ni_ps *ps = ni_get_ps(rps);
1059 u32 levels;
1060
1061 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1057 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1062 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 1058 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1063 return -EINVAL; 1059 return -EINVAL;
@@ -1068,8 +1064,7 @@ int ni_dpm_force_performance_level(struct radeon_device *rdev,
1068 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 1064 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1069 return -EINVAL; 1065 return -EINVAL;
1070 1066
1071 levels = ps->performance_level_count - 1; 1067 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
1072 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
1073 return -EINVAL; 1068 return -EINVAL;
1074 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 1069 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1075 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 1070 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
@@ -4072,9 +4067,6 @@ int ni_dpm_init(struct radeon_device *rdev)
4072 struct rv7xx_power_info *pi; 4067 struct rv7xx_power_info *pi;
4073 struct evergreen_power_info *eg_pi; 4068 struct evergreen_power_info *eg_pi;
4074 struct ni_power_info *ni_pi; 4069 struct ni_power_info *ni_pi;
4075 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
4076 u16 data_offset, size;
4077 u8 frev, crev;
4078 struct atom_clock_dividers dividers; 4070 struct atom_clock_dividers dividers;
4079 int ret; 4071 int ret;
4080 4072
@@ -4167,16 +4159,7 @@ int ni_dpm_init(struct radeon_device *rdev)
4167 eg_pi->vddci_control = 4159 eg_pi->vddci_control =
4168 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 4160 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
4169 4161
4170 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 4162 rv770_get_engine_memory_ss(rdev);
4171 &frev, &crev, &data_offset)) {
4172 pi->sclk_ss = true;
4173 pi->mclk_ss = true;
4174 pi->dynamic_ss = true;
4175 } else {
4176 pi->sclk_ss = false;
4177 pi->mclk_ss = false;
4178 pi->dynamic_ss = true;
4179 }
4180 4163
4181 pi->asi = RV770_ASI_DFLT; 4164 pi->asi = RV770_ASI_DFLT;
4182 pi->pasi = CYPRESS_HASI_DFLT; 4165 pi->pasi = CYPRESS_HASI_DFLT;
@@ -4193,8 +4176,7 @@ int ni_dpm_init(struct radeon_device *rdev)
4193 4176
4194 pi->dynamic_pcie_gen2 = true; 4177 pi->dynamic_pcie_gen2 = true;
4195 4178
4196 if (pi->gfx_clock_gating && 4179 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
4197 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
4198 pi->thermal_protection = true; 4180 pi->thermal_protection = true;
4199 else 4181 else
4200 pi->thermal_protection = false; 4182 pi->thermal_protection = false;