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path: root/drivers/gpu/drm/radeon/ni.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c76
1 files changed, 0 insertions, 76 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index cac2866d79da..11aab2ab54ce 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -174,11 +174,6 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174extern void evergreen_program_aspm(struct radeon_device *rdev); 174extern void evergreen_program_aspm(struct radeon_device *rdev);
175extern void sumo_rlc_fini(struct radeon_device *rdev); 175extern void sumo_rlc_fini(struct radeon_device *rdev);
176extern int sumo_rlc_init(struct radeon_device *rdev); 176extern int sumo_rlc_init(struct radeon_device *rdev);
177extern void cayman_dma_vm_set_page(struct radeon_device *rdev,
178 struct radeon_ib *ib,
179 uint64_t pe,
180 uint64_t addr, unsigned count,
181 uint32_t incr, uint32_t flags);
182 177
183/* Firmware Names */ 178/* Firmware Names */
184MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); 179MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
@@ -2400,77 +2395,6 @@ void cayman_vm_decode_fault(struct radeon_device *rdev,
2400 block, mc_id); 2395 block, mc_id);
2401} 2396}
2402 2397
2403#define R600_ENTRY_VALID (1 << 0)
2404#define R600_PTE_SYSTEM (1 << 1)
2405#define R600_PTE_SNOOPED (1 << 2)
2406#define R600_PTE_READABLE (1 << 5)
2407#define R600_PTE_WRITEABLE (1 << 6)
2408
2409uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
2410{
2411 uint32_t r600_flags = 0;
2412 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
2413 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
2414 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
2415 if (flags & RADEON_VM_PAGE_SYSTEM) {
2416 r600_flags |= R600_PTE_SYSTEM;
2417 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
2418 }
2419 return r600_flags;
2420}
2421
2422/**
2423 * cayman_vm_set_page - update the page tables using the CP
2424 *
2425 * @rdev: radeon_device pointer
2426 * @ib: indirect buffer to fill with commands
2427 * @pe: addr of the page entry
2428 * @addr: dst addr to write into pe
2429 * @count: number of page entries to update
2430 * @incr: increase next addr by incr bytes
2431 * @flags: access flags
2432 *
2433 * Update the page tables using the CP (cayman/TN).
2434 */
2435void cayman_vm_set_page(struct radeon_device *rdev,
2436 struct radeon_ib *ib,
2437 uint64_t pe,
2438 uint64_t addr, unsigned count,
2439 uint32_t incr, uint32_t flags)
2440{
2441 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
2442 uint64_t value;
2443 unsigned ndw;
2444
2445 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
2446 while (count) {
2447 ndw = 1 + count * 2;
2448 if (ndw > 0x3FFF)
2449 ndw = 0x3FFF;
2450
2451 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
2452 ib->ptr[ib->length_dw++] = pe;
2453 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2454 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
2455 if (flags & RADEON_VM_PAGE_SYSTEM) {
2456 value = radeon_vm_map_gart(rdev, addr);
2457 value &= 0xFFFFFFFFFFFFF000ULL;
2458 } else if (flags & RADEON_VM_PAGE_VALID) {
2459 value = addr;
2460 } else {
2461 value = 0;
2462 }
2463 addr += incr;
2464 value |= r600_flags;
2465 ib->ptr[ib->length_dw++] = value;
2466 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2467 }
2468 }
2469 } else {
2470 cayman_dma_vm_set_page(rdev, ib, pe, addr, count, incr, flags);
2471 }
2472}
2473
2474/** 2398/**
2475 * cayman_vm_flush - vm flush using the CP 2399 * cayman_vm_flush - vm flush using the CP
2476 * 2400 *