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path: root/drivers/gpu/drm/radeon/evergreen_blit_kms.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_blit_kms.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c561
1 files changed, 321 insertions, 240 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index ba06a69c6de8..57f3bc17b87e 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -31,6 +31,7 @@
31 31
32#include "evergreend.h" 32#include "evergreend.h"
33#include "evergreen_blit_shaders.h" 33#include "evergreen_blit_shaders.h"
34#include "cayman_blit_shaders.h"
34 35
35#define DI_PT_RECTLIST 0x11 36#define DI_PT_RECTLIST 0x11
36#define DI_INDEX_SIZE_16_BIT 0x0 37#define DI_INDEX_SIZE_16_BIT 0x0
@@ -152,6 +153,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
152 153
153 if ((rdev->family == CHIP_CEDAR) || 154 if ((rdev->family == CHIP_CEDAR) ||
154 (rdev->family == CHIP_PALM) || 155 (rdev->family == CHIP_PALM) ||
156 (rdev->family == CHIP_SUMO) ||
157 (rdev->family == CHIP_SUMO2) ||
155 (rdev->family == CHIP_CAICOS)) 158 (rdev->family == CHIP_CAICOS))
156 cp_set_surface_sync(rdev, 159 cp_set_surface_sync(rdev,
157 PACKET3_TC_ACTION_ENA, 48, gpu_addr); 160 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
@@ -199,6 +202,16 @@ static void
199set_scissors(struct radeon_device *rdev, int x1, int y1, 202set_scissors(struct radeon_device *rdev, int x1, int y1,
200 int x2, int y2) 203 int x2, int y2)
201{ 204{
205 /* workaround some hw bugs */
206 if (x2 == 0)
207 x1 = 1;
208 if (y2 == 0)
209 y1 = 1;
210 if (rdev->family == CHIP_CAYMAN) {
211 if ((x2 == 1) && (y2 == 1))
212 x2 = 2;
213 }
214
202 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 215 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
203 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); 216 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
204 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); 217 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
@@ -255,238 +268,284 @@ set_default_state(struct radeon_device *rdev)
255 u64 gpu_addr; 268 u64 gpu_addr;
256 int dwords; 269 int dwords;
257 270
258 switch (rdev->family) {
259 case CHIP_CEDAR:
260 default:
261 num_ps_gprs = 93;
262 num_vs_gprs = 46;
263 num_temp_gprs = 4;
264 num_gs_gprs = 31;
265 num_es_gprs = 31;
266 num_hs_gprs = 23;
267 num_ls_gprs = 23;
268 num_ps_threads = 96;
269 num_vs_threads = 16;
270 num_gs_threads = 16;
271 num_es_threads = 16;
272 num_hs_threads = 16;
273 num_ls_threads = 16;
274 num_ps_stack_entries = 42;
275 num_vs_stack_entries = 42;
276 num_gs_stack_entries = 42;
277 num_es_stack_entries = 42;
278 num_hs_stack_entries = 42;
279 num_ls_stack_entries = 42;
280 break;
281 case CHIP_REDWOOD:
282 num_ps_gprs = 93;
283 num_vs_gprs = 46;
284 num_temp_gprs = 4;
285 num_gs_gprs = 31;
286 num_es_gprs = 31;
287 num_hs_gprs = 23;
288 num_ls_gprs = 23;
289 num_ps_threads = 128;
290 num_vs_threads = 20;
291 num_gs_threads = 20;
292 num_es_threads = 20;
293 num_hs_threads = 20;
294 num_ls_threads = 20;
295 num_ps_stack_entries = 42;
296 num_vs_stack_entries = 42;
297 num_gs_stack_entries = 42;
298 num_es_stack_entries = 42;
299 num_hs_stack_entries = 42;
300 num_ls_stack_entries = 42;
301 break;
302 case CHIP_JUNIPER:
303 num_ps_gprs = 93;
304 num_vs_gprs = 46;
305 num_temp_gprs = 4;
306 num_gs_gprs = 31;
307 num_es_gprs = 31;
308 num_hs_gprs = 23;
309 num_ls_gprs = 23;
310 num_ps_threads = 128;
311 num_vs_threads = 20;
312 num_gs_threads = 20;
313 num_es_threads = 20;
314 num_hs_threads = 20;
315 num_ls_threads = 20;
316 num_ps_stack_entries = 85;
317 num_vs_stack_entries = 85;
318 num_gs_stack_entries = 85;
319 num_es_stack_entries = 85;
320 num_hs_stack_entries = 85;
321 num_ls_stack_entries = 85;
322 break;
323 case CHIP_CYPRESS:
324 case CHIP_HEMLOCK:
325 num_ps_gprs = 93;
326 num_vs_gprs = 46;
327 num_temp_gprs = 4;
328 num_gs_gprs = 31;
329 num_es_gprs = 31;
330 num_hs_gprs = 23;
331 num_ls_gprs = 23;
332 num_ps_threads = 128;
333 num_vs_threads = 20;
334 num_gs_threads = 20;
335 num_es_threads = 20;
336 num_hs_threads = 20;
337 num_ls_threads = 20;
338 num_ps_stack_entries = 85;
339 num_vs_stack_entries = 85;
340 num_gs_stack_entries = 85;
341 num_es_stack_entries = 85;
342 num_hs_stack_entries = 85;
343 num_ls_stack_entries = 85;
344 break;
345 case CHIP_PALM:
346 num_ps_gprs = 93;
347 num_vs_gprs = 46;
348 num_temp_gprs = 4;
349 num_gs_gprs = 31;
350 num_es_gprs = 31;
351 num_hs_gprs = 23;
352 num_ls_gprs = 23;
353 num_ps_threads = 96;
354 num_vs_threads = 16;
355 num_gs_threads = 16;
356 num_es_threads = 16;
357 num_hs_threads = 16;
358 num_ls_threads = 16;
359 num_ps_stack_entries = 42;
360 num_vs_stack_entries = 42;
361 num_gs_stack_entries = 42;
362 num_es_stack_entries = 42;
363 num_hs_stack_entries = 42;
364 num_ls_stack_entries = 42;
365 break;
366 case CHIP_BARTS:
367 num_ps_gprs = 93;
368 num_vs_gprs = 46;
369 num_temp_gprs = 4;
370 num_gs_gprs = 31;
371 num_es_gprs = 31;
372 num_hs_gprs = 23;
373 num_ls_gprs = 23;
374 num_ps_threads = 128;
375 num_vs_threads = 20;
376 num_gs_threads = 20;
377 num_es_threads = 20;
378 num_hs_threads = 20;
379 num_ls_threads = 20;
380 num_ps_stack_entries = 85;
381 num_vs_stack_entries = 85;
382 num_gs_stack_entries = 85;
383 num_es_stack_entries = 85;
384 num_hs_stack_entries = 85;
385 num_ls_stack_entries = 85;
386 break;
387 case CHIP_TURKS:
388 num_ps_gprs = 93;
389 num_vs_gprs = 46;
390 num_temp_gprs = 4;
391 num_gs_gprs = 31;
392 num_es_gprs = 31;
393 num_hs_gprs = 23;
394 num_ls_gprs = 23;
395 num_ps_threads = 128;
396 num_vs_threads = 20;
397 num_gs_threads = 20;
398 num_es_threads = 20;
399 num_hs_threads = 20;
400 num_ls_threads = 20;
401 num_ps_stack_entries = 42;
402 num_vs_stack_entries = 42;
403 num_gs_stack_entries = 42;
404 num_es_stack_entries = 42;
405 num_hs_stack_entries = 42;
406 num_ls_stack_entries = 42;
407 break;
408 case CHIP_CAICOS:
409 num_ps_gprs = 93;
410 num_vs_gprs = 46;
411 num_temp_gprs = 4;
412 num_gs_gprs = 31;
413 num_es_gprs = 31;
414 num_hs_gprs = 23;
415 num_ls_gprs = 23;
416 num_ps_threads = 128;
417 num_vs_threads = 10;
418 num_gs_threads = 10;
419 num_es_threads = 10;
420 num_hs_threads = 10;
421 num_ls_threads = 10;
422 num_ps_stack_entries = 42;
423 num_vs_stack_entries = 42;
424 num_gs_stack_entries = 42;
425 num_es_stack_entries = 42;
426 num_hs_stack_entries = 42;
427 num_ls_stack_entries = 42;
428 break;
429 }
430
431 if ((rdev->family == CHIP_CEDAR) ||
432 (rdev->family == CHIP_PALM) ||
433 (rdev->family == CHIP_CAICOS))
434 sq_config = 0;
435 else
436 sq_config = VC_ENABLE;
437
438 sq_config |= (EXPORT_SRC_C |
439 CS_PRIO(0) |
440 LS_PRIO(0) |
441 HS_PRIO(0) |
442 PS_PRIO(0) |
443 VS_PRIO(1) |
444 GS_PRIO(2) |
445 ES_PRIO(3));
446
447 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
448 NUM_VS_GPRS(num_vs_gprs) |
449 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
450 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
451 NUM_ES_GPRS(num_es_gprs));
452 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
453 NUM_LS_GPRS(num_ls_gprs));
454 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
455 NUM_VS_THREADS(num_vs_threads) |
456 NUM_GS_THREADS(num_gs_threads) |
457 NUM_ES_THREADS(num_es_threads));
458 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
459 NUM_LS_THREADS(num_ls_threads));
460 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
461 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
462 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
463 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
464 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
465 NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
466
467 /* set clear context state */ 271 /* set clear context state */
468 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 272 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
469 radeon_ring_write(rdev, 0); 273 radeon_ring_write(rdev, 0);
470 274
471 /* disable dyn gprs */ 275 if (rdev->family < CHIP_CAYMAN) {
472 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 276 switch (rdev->family) {
473 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); 277 case CHIP_CEDAR:
474 radeon_ring_write(rdev, 0); 278 default:
279 num_ps_gprs = 93;
280 num_vs_gprs = 46;
281 num_temp_gprs = 4;
282 num_gs_gprs = 31;
283 num_es_gprs = 31;
284 num_hs_gprs = 23;
285 num_ls_gprs = 23;
286 num_ps_threads = 96;
287 num_vs_threads = 16;
288 num_gs_threads = 16;
289 num_es_threads = 16;
290 num_hs_threads = 16;
291 num_ls_threads = 16;
292 num_ps_stack_entries = 42;
293 num_vs_stack_entries = 42;
294 num_gs_stack_entries = 42;
295 num_es_stack_entries = 42;
296 num_hs_stack_entries = 42;
297 num_ls_stack_entries = 42;
298 break;
299 case CHIP_REDWOOD:
300 num_ps_gprs = 93;
301 num_vs_gprs = 46;
302 num_temp_gprs = 4;
303 num_gs_gprs = 31;
304 num_es_gprs = 31;
305 num_hs_gprs = 23;
306 num_ls_gprs = 23;
307 num_ps_threads = 128;
308 num_vs_threads = 20;
309 num_gs_threads = 20;
310 num_es_threads = 20;
311 num_hs_threads = 20;
312 num_ls_threads = 20;
313 num_ps_stack_entries = 42;
314 num_vs_stack_entries = 42;
315 num_gs_stack_entries = 42;
316 num_es_stack_entries = 42;
317 num_hs_stack_entries = 42;
318 num_ls_stack_entries = 42;
319 break;
320 case CHIP_JUNIPER:
321 num_ps_gprs = 93;
322 num_vs_gprs = 46;
323 num_temp_gprs = 4;
324 num_gs_gprs = 31;
325 num_es_gprs = 31;
326 num_hs_gprs = 23;
327 num_ls_gprs = 23;
328 num_ps_threads = 128;
329 num_vs_threads = 20;
330 num_gs_threads = 20;
331 num_es_threads = 20;
332 num_hs_threads = 20;
333 num_ls_threads = 20;
334 num_ps_stack_entries = 85;
335 num_vs_stack_entries = 85;
336 num_gs_stack_entries = 85;
337 num_es_stack_entries = 85;
338 num_hs_stack_entries = 85;
339 num_ls_stack_entries = 85;
340 break;
341 case CHIP_CYPRESS:
342 case CHIP_HEMLOCK:
343 num_ps_gprs = 93;
344 num_vs_gprs = 46;
345 num_temp_gprs = 4;
346 num_gs_gprs = 31;
347 num_es_gprs = 31;
348 num_hs_gprs = 23;
349 num_ls_gprs = 23;
350 num_ps_threads = 128;
351 num_vs_threads = 20;
352 num_gs_threads = 20;
353 num_es_threads = 20;
354 num_hs_threads = 20;
355 num_ls_threads = 20;
356 num_ps_stack_entries = 85;
357 num_vs_stack_entries = 85;
358 num_gs_stack_entries = 85;
359 num_es_stack_entries = 85;
360 num_hs_stack_entries = 85;
361 num_ls_stack_entries = 85;
362 break;
363 case CHIP_PALM:
364 num_ps_gprs = 93;
365 num_vs_gprs = 46;
366 num_temp_gprs = 4;
367 num_gs_gprs = 31;
368 num_es_gprs = 31;
369 num_hs_gprs = 23;
370 num_ls_gprs = 23;
371 num_ps_threads = 96;
372 num_vs_threads = 16;
373 num_gs_threads = 16;
374 num_es_threads = 16;
375 num_hs_threads = 16;
376 num_ls_threads = 16;
377 num_ps_stack_entries = 42;
378 num_vs_stack_entries = 42;
379 num_gs_stack_entries = 42;
380 num_es_stack_entries = 42;
381 num_hs_stack_entries = 42;
382 num_ls_stack_entries = 42;
383 break;
384 case CHIP_SUMO:
385 num_ps_gprs = 93;
386 num_vs_gprs = 46;
387 num_temp_gprs = 4;
388 num_gs_gprs = 31;
389 num_es_gprs = 31;
390 num_hs_gprs = 23;
391 num_ls_gprs = 23;
392 num_ps_threads = 96;
393 num_vs_threads = 25;
394 num_gs_threads = 25;
395 num_es_threads = 25;
396 num_hs_threads = 25;
397 num_ls_threads = 25;
398 num_ps_stack_entries = 42;
399 num_vs_stack_entries = 42;
400 num_gs_stack_entries = 42;
401 num_es_stack_entries = 42;
402 num_hs_stack_entries = 42;
403 num_ls_stack_entries = 42;
404 break;
405 case CHIP_SUMO2:
406 num_ps_gprs = 93;
407 num_vs_gprs = 46;
408 num_temp_gprs = 4;
409 num_gs_gprs = 31;
410 num_es_gprs = 31;
411 num_hs_gprs = 23;
412 num_ls_gprs = 23;
413 num_ps_threads = 96;
414 num_vs_threads = 25;
415 num_gs_threads = 25;
416 num_es_threads = 25;
417 num_hs_threads = 25;
418 num_ls_threads = 25;
419 num_ps_stack_entries = 85;
420 num_vs_stack_entries = 85;
421 num_gs_stack_entries = 85;
422 num_es_stack_entries = 85;
423 num_hs_stack_entries = 85;
424 num_ls_stack_entries = 85;
425 break;
426 case CHIP_BARTS:
427 num_ps_gprs = 93;
428 num_vs_gprs = 46;
429 num_temp_gprs = 4;
430 num_gs_gprs = 31;
431 num_es_gprs = 31;
432 num_hs_gprs = 23;
433 num_ls_gprs = 23;
434 num_ps_threads = 128;
435 num_vs_threads = 20;
436 num_gs_threads = 20;
437 num_es_threads = 20;
438 num_hs_threads = 20;
439 num_ls_threads = 20;
440 num_ps_stack_entries = 85;
441 num_vs_stack_entries = 85;
442 num_gs_stack_entries = 85;
443 num_es_stack_entries = 85;
444 num_hs_stack_entries = 85;
445 num_ls_stack_entries = 85;
446 break;
447 case CHIP_TURKS:
448 num_ps_gprs = 93;
449 num_vs_gprs = 46;
450 num_temp_gprs = 4;
451 num_gs_gprs = 31;
452 num_es_gprs = 31;
453 num_hs_gprs = 23;
454 num_ls_gprs = 23;
455 num_ps_threads = 128;
456 num_vs_threads = 20;
457 num_gs_threads = 20;
458 num_es_threads = 20;
459 num_hs_threads = 20;
460 num_ls_threads = 20;
461 num_ps_stack_entries = 42;
462 num_vs_stack_entries = 42;
463 num_gs_stack_entries = 42;
464 num_es_stack_entries = 42;
465 num_hs_stack_entries = 42;
466 num_ls_stack_entries = 42;
467 break;
468 case CHIP_CAICOS:
469 num_ps_gprs = 93;
470 num_vs_gprs = 46;
471 num_temp_gprs = 4;
472 num_gs_gprs = 31;
473 num_es_gprs = 31;
474 num_hs_gprs = 23;
475 num_ls_gprs = 23;
476 num_ps_threads = 128;
477 num_vs_threads = 10;
478 num_gs_threads = 10;
479 num_es_threads = 10;
480 num_hs_threads = 10;
481 num_ls_threads = 10;
482 num_ps_stack_entries = 42;
483 num_vs_stack_entries = 42;
484 num_gs_stack_entries = 42;
485 num_es_stack_entries = 42;
486 num_hs_stack_entries = 42;
487 num_ls_stack_entries = 42;
488 break;
489 }
475 490
476 /* SQ config */ 491 if ((rdev->family == CHIP_CEDAR) ||
477 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); 492 (rdev->family == CHIP_PALM) ||
478 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); 493 (rdev->family == CHIP_SUMO) ||
479 radeon_ring_write(rdev, sq_config); 494 (rdev->family == CHIP_SUMO2) ||
480 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); 495 (rdev->family == CHIP_CAICOS))
481 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); 496 sq_config = 0;
482 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3); 497 else
483 radeon_ring_write(rdev, 0); 498 sq_config = VC_ENABLE;
484 radeon_ring_write(rdev, 0); 499
485 radeon_ring_write(rdev, sq_thread_resource_mgmt); 500 sq_config |= (EXPORT_SRC_C |
486 radeon_ring_write(rdev, sq_thread_resource_mgmt_2); 501 CS_PRIO(0) |
487 radeon_ring_write(rdev, sq_stack_resource_mgmt_1); 502 LS_PRIO(0) |
488 radeon_ring_write(rdev, sq_stack_resource_mgmt_2); 503 HS_PRIO(0) |
489 radeon_ring_write(rdev, sq_stack_resource_mgmt_3); 504 PS_PRIO(0) |
505 VS_PRIO(1) |
506 GS_PRIO(2) |
507 ES_PRIO(3));
508
509 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
510 NUM_VS_GPRS(num_vs_gprs) |
511 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
512 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
513 NUM_ES_GPRS(num_es_gprs));
514 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
515 NUM_LS_GPRS(num_ls_gprs));
516 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
517 NUM_VS_THREADS(num_vs_threads) |
518 NUM_GS_THREADS(num_gs_threads) |
519 NUM_ES_THREADS(num_es_threads));
520 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
521 NUM_LS_THREADS(num_ls_threads));
522 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
523 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
524 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
525 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
526 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
527 NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
528
529 /* disable dyn gprs */
530 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
531 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
532 radeon_ring_write(rdev, 0);
533
534 /* SQ config */
535 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
536 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
537 radeon_ring_write(rdev, sq_config);
538 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
539 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
540 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
541 radeon_ring_write(rdev, 0);
542 radeon_ring_write(rdev, 0);
543 radeon_ring_write(rdev, sq_thread_resource_mgmt);
544 radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
545 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
546 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
547 radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
548 }
490 549
491 /* CONTEXT_CONTROL */ 550 /* CONTEXT_CONTROL */
492 radeon_ring_write(rdev, 0xc0012800); 551 radeon_ring_write(rdev, 0xc0012800);
@@ -560,7 +619,10 @@ int evergreen_blit_init(struct radeon_device *rdev)
560 mutex_init(&rdev->r600_blit.mutex); 619 mutex_init(&rdev->r600_blit.mutex);
561 rdev->r600_blit.state_offset = 0; 620 rdev->r600_blit.state_offset = 0;
562 621
563 rdev->r600_blit.state_len = evergreen_default_size; 622 if (rdev->family < CHIP_CAYMAN)
623 rdev->r600_blit.state_len = evergreen_default_size;
624 else
625 rdev->r600_blit.state_len = cayman_default_size;
564 626
565 dwords = rdev->r600_blit.state_len; 627 dwords = rdev->r600_blit.state_len;
566 while (dwords & 0xf) { 628 while (dwords & 0xf) {
@@ -572,11 +634,17 @@ int evergreen_blit_init(struct radeon_device *rdev)
572 obj_size = ALIGN(obj_size, 256); 634 obj_size = ALIGN(obj_size, 256);
573 635
574 rdev->r600_blit.vs_offset = obj_size; 636 rdev->r600_blit.vs_offset = obj_size;
575 obj_size += evergreen_vs_size * 4; 637 if (rdev->family < CHIP_CAYMAN)
638 obj_size += evergreen_vs_size * 4;
639 else
640 obj_size += cayman_vs_size * 4;
576 obj_size = ALIGN(obj_size, 256); 641 obj_size = ALIGN(obj_size, 256);
577 642
578 rdev->r600_blit.ps_offset = obj_size; 643 rdev->r600_blit.ps_offset = obj_size;
579 obj_size += evergreen_ps_size * 4; 644 if (rdev->family < CHIP_CAYMAN)
645 obj_size += evergreen_ps_size * 4;
646 else
647 obj_size += cayman_ps_size * 4;
580 obj_size = ALIGN(obj_size, 256); 648 obj_size = ALIGN(obj_size, 256);
581 649
582 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 650 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
@@ -599,16 +667,29 @@ int evergreen_blit_init(struct radeon_device *rdev)
599 return r; 667 return r;
600 } 668 }
601 669
602 memcpy_toio(ptr + rdev->r600_blit.state_offset, 670 if (rdev->family < CHIP_CAYMAN) {
603 evergreen_default_state, rdev->r600_blit.state_len * 4); 671 memcpy_toio(ptr + rdev->r600_blit.state_offset,
604 672 evergreen_default_state, rdev->r600_blit.state_len * 4);
605 if (num_packet2s) 673
606 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), 674 if (num_packet2s)
607 packet2s, num_packet2s * 4); 675 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
608 for (i = 0; i < evergreen_vs_size; i++) 676 packet2s, num_packet2s * 4);
609 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); 677 for (i = 0; i < evergreen_vs_size; i++)
610 for (i = 0; i < evergreen_ps_size; i++) 678 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
611 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); 679 for (i = 0; i < evergreen_ps_size; i++)
680 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
681 } else {
682 memcpy_toio(ptr + rdev->r600_blit.state_offset,
683 cayman_default_state, rdev->r600_blit.state_len * 4);
684
685 if (num_packet2s)
686 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
687 packet2s, num_packet2s * 4);
688 for (i = 0; i < cayman_vs_size; i++)
689 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
690 for (i = 0; i < cayman_ps_size; i++)
691 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
692 }
612 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 693 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
613 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 694 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
614 695
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-05 11:34:45 -0500