diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 63a1e6ec7f5a..54d1d736dee2 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -4167,6 +4167,7 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
4167 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | 4167 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
4168 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; | 4168 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; |
4169 | u32 dma_cntl, dma_cntl1 = 0; | 4169 | u32 dma_cntl, dma_cntl1 = 0; |
4170 | u32 thermal_int = 0; | ||
4170 | 4171 | ||
4171 | if (!rdev->irq.installed) { | 4172 | if (!rdev->irq.installed) { |
4172 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); | 4173 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
@@ -4186,6 +4187,8 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
4186 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4187 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4187 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4188 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4188 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4189 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4190 | thermal_int = RREG32(CG_THERMAL_INT) & | ||
4191 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); | ||
4189 | 4192 | ||
4190 | afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | 4193 | afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
4191 | afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | 4194 | afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
@@ -4231,6 +4234,11 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
4231 | } | 4234 | } |
4232 | } | 4235 | } |
4233 | 4236 | ||
4237 | if (rdev->irq.dpm_thermal) { | ||
4238 | DRM_DEBUG("dpm thermal\n"); | ||
4239 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; | ||
4240 | } | ||
4241 | |||
4234 | if (rdev->irq.crtc_vblank_int[0] || | 4242 | if (rdev->irq.crtc_vblank_int[0] || |
4235 | atomic_read(&rdev->irq.pflip[0])) { | 4243 | atomic_read(&rdev->irq.pflip[0])) { |
4236 | DRM_DEBUG("evergreen_irq_set: vblank 0\n"); | 4244 | DRM_DEBUG("evergreen_irq_set: vblank 0\n"); |
@@ -4352,6 +4360,7 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
4352 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | 4360 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
4353 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | 4361 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
4354 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | 4362 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
4363 | WREG32(CG_THERMAL_INT, thermal_int); | ||
4355 | 4364 | ||
4356 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); | 4365 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); |
4357 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); | 4366 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); |
@@ -4543,6 +4552,7 @@ int evergreen_irq_process(struct radeon_device *rdev) | |||
4543 | u32 ring_index; | 4552 | u32 ring_index; |
4544 | bool queue_hotplug = false; | 4553 | bool queue_hotplug = false; |
4545 | bool queue_hdmi = false; | 4554 | bool queue_hdmi = false; |
4555 | bool queue_thermal = false; | ||
4546 | 4556 | ||
4547 | if (!rdev->ih.enabled || rdev->shutdown) | 4557 | if (!rdev->ih.enabled || rdev->shutdown) |
4548 | return IRQ_NONE; | 4558 | return IRQ_NONE; |
@@ -4864,6 +4874,16 @@ restart_ih: | |||
4864 | DRM_DEBUG("IH: DMA trap\n"); | 4874 | DRM_DEBUG("IH: DMA trap\n"); |
4865 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); | 4875 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); |
4866 | break; | 4876 | break; |
4877 | case 230: /* thermal low to high */ | ||
4878 | DRM_DEBUG("IH: thermal low to high\n"); | ||
4879 | rdev->pm.dpm.thermal.high_to_low = false; | ||
4880 | queue_thermal = true; | ||
4881 | break; | ||
4882 | case 231: /* thermal high to low */ | ||
4883 | DRM_DEBUG("IH: thermal high to low\n"); | ||
4884 | rdev->pm.dpm.thermal.high_to_low = true; | ||
4885 | queue_thermal = true; | ||
4886 | break; | ||
4867 | case 233: /* GUI IDLE */ | 4887 | case 233: /* GUI IDLE */ |
4868 | DRM_DEBUG("IH: GUI idle\n"); | 4888 | DRM_DEBUG("IH: GUI idle\n"); |
4869 | break; | 4889 | break; |
@@ -4886,6 +4906,8 @@ restart_ih: | |||
4886 | schedule_work(&rdev->hotplug_work); | 4906 | schedule_work(&rdev->hotplug_work); |
4887 | if (queue_hdmi) | 4907 | if (queue_hdmi) |
4888 | schedule_work(&rdev->audio_work); | 4908 | schedule_work(&rdev->audio_work); |
4909 | if (queue_thermal && rdev->pm.dpm_enabled) | ||
4910 | schedule_work(&rdev->pm.dpm.thermal.work); | ||
4889 | rdev->ih.rptr = rptr; | 4911 | rdev->ih.rptr = rptr; |
4890 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | 4912 | WREG32(IH_RB_RPTR, rdev->ih.rptr); |
4891 | atomic_set(&rdev->ih.lock, 0); | 4913 | atomic_set(&rdev->ih.lock, 0); |