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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 15e4f28015e1..4fedd14e670a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2424,7 +2424,6 @@ static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
2424 r = radeon_gart_table_vram_pin(rdev); 2424 r = radeon_gart_table_vram_pin(rdev);
2425 if (r) 2425 if (r)
2426 return r; 2426 return r;
2427 radeon_gart_restore(rdev);
2428 /* Setup L2 cache */ 2427 /* Setup L2 cache */
2429 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 2428 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
2430 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2429 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
@@ -2677,7 +2676,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
2677 if (save->crtc_enabled[i]) { 2676 if (save->crtc_enabled[i]) {
2678 if (ASIC_IS_DCE6(rdev)) { 2677 if (ASIC_IS_DCE6(rdev)) {
2679 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 2678 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
2680 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; 2679 tmp &= ~EVERGREEN_CRTC_BLANK_DATA_EN;
2681 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 2680 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2682 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 2681 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2683 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 2682 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
@@ -4023,7 +4022,8 @@ int sumo_rlc_init(struct radeon_device *rdev)
4023 /* save restore block */ 4022 /* save restore block */
4024 if (rdev->rlc.save_restore_obj == NULL) { 4023 if (rdev->rlc.save_restore_obj == NULL) {
4025 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, 4024 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4026 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj); 4025 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4026 &rdev->rlc.save_restore_obj);
4027 if (r) { 4027 if (r) {
4028 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); 4028 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
4029 return r; 4029 return r;
@@ -4101,7 +4101,8 @@ int sumo_rlc_init(struct radeon_device *rdev)
4101 4101
4102 if (rdev->rlc.clear_state_obj == NULL) { 4102 if (rdev->rlc.clear_state_obj == NULL) {
4103 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, 4103 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4104 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj); 4104 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4105 &rdev->rlc.clear_state_obj);
4105 if (r) { 4106 if (r) {
4106 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); 4107 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
4107 sumo_rlc_fini(rdev); 4108 sumo_rlc_fini(rdev);
@@ -4175,8 +4176,10 @@ int sumo_rlc_init(struct radeon_device *rdev)
4175 4176
4176 if (rdev->rlc.cp_table_size) { 4177 if (rdev->rlc.cp_table_size) {
4177 if (rdev->rlc.cp_table_obj == NULL) { 4178 if (rdev->rlc.cp_table_obj == NULL) {
4178 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, PAGE_SIZE, true, 4179 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4179 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.cp_table_obj); 4180 PAGE_SIZE, true,
4181 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
4182 &rdev->rlc.cp_table_obj);
4180 if (r) { 4183 if (r) {
4181 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r); 4184 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);
4182 sumo_rlc_fini(rdev); 4185 sumo_rlc_fini(rdev);
@@ -4961,7 +4964,8 @@ restart_ih:
4961 case 16: /* D5 page flip */ 4964 case 16: /* D5 page flip */
4962 case 18: /* D6 page flip */ 4965 case 18: /* D6 page flip */
4963 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); 4966 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
4964 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); 4967 if (radeon_use_pflipirq > 0)
4968 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
4965 break; 4969 break;
4966 case 42: /* HPD hotplug */ 4970 case 42: /* HPD hotplug */
4967 switch (src_data) { 4971 switch (src_data) {