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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c44
1 files changed, 0 insertions, 44 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e8a746712b5b..c4ffa14fb2f4 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1590 return backend_map; 1590 return backend_map;
1591} 1591}
1592 1592
1593static void evergreen_program_channel_remap(struct radeon_device *rdev)
1594{
1595 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1596
1597 tmp = RREG32(MC_SHARED_CHMAP);
1598 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1599 case 0:
1600 case 1:
1601 case 2:
1602 case 3:
1603 default:
1604 /* default mapping */
1605 mc_shared_chremap = 0x00fac688;
1606 break;
1607 }
1608
1609 switch (rdev->family) {
1610 case CHIP_HEMLOCK:
1611 case CHIP_CYPRESS:
1612 case CHIP_BARTS:
1613 tcp_chan_steer_lo = 0x54763210;
1614 tcp_chan_steer_hi = 0x0000ba98;
1615 break;
1616 case CHIP_JUNIPER:
1617 case CHIP_REDWOOD:
1618 case CHIP_CEDAR:
1619 case CHIP_PALM:
1620 case CHIP_SUMO:
1621 case CHIP_SUMO2:
1622 case CHIP_TURKS:
1623 case CHIP_CAICOS:
1624 default:
1625 tcp_chan_steer_lo = 0x76543210;
1626 tcp_chan_steer_hi = 0x0000ba98;
1627 break;
1628 }
1629
1630 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1631 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1632 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1633}
1634
1635static void evergreen_gpu_init(struct radeon_device *rdev) 1593static void evergreen_gpu_init(struct radeon_device *rdev)
1636{ 1594{
1637 u32 cc_rb_backend_disable = 0; 1595 u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2078 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2036 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2079 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2037 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2080 2038
2081 evergreen_program_channel_remap(rdev);
2082
2083 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 2039 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2084 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 2040 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2085 2041