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path: root/drivers/gpu/drm/radeon/cik_sdma.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/cik_sdma.c')
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index d7e51c06d597..9abea87a9213 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -168,13 +168,21 @@ static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,
168 int ridx) 168 int ridx)
169{ 169{
170 struct radeon_ring *ring = &rdev->ring[ridx]; 170 struct radeon_ring *ring = &rdev->ring[ridx];
171 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
172 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
173 u32 ref_and_mask;
171 174
172 /* We should be using the new POLL_REG_MEM special op packet here 175 if (ridx == R600_RING_TYPE_DMA_INDEX)
173 * but it causes sDMA to hang sometimes 176 ref_and_mask = SDMA0;
174 */ 177 else
175 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 178 ref_and_mask = SDMA1;
176 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); 179
177 radeon_ring_write(ring, 0); 180 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
181 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
182 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
183 radeon_ring_write(ring, ref_and_mask); /* reference */
184 radeon_ring_write(ring, ref_and_mask); /* mask */
185 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
178} 186}
179 187
180/** 188/**